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/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/mips/lib/
H A Dcache_init.S38 .macro cache_loop curr, end, line_sz, op
40 PTR_ADDU \curr, \curr, \line_sz
44 .macro l1_info sz, line_sz, off
51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
52 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
54 beqz \line_sz, 10f
56 sllv \line_sz, \sz, \line_sz
64 mul \sz, \sz, \line_sz

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