| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-tools/u-boot-2020.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-bananapim2/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-rpi4/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
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| /dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
|