/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-pinebook/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-bananapi/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1680 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1744 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1745 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1757 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1758 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1759 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1911 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1912 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1914 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1915 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-bananapim2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local 1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst() 1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst() 1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst() 1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() 1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst() [all …]
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