| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
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| /dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
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| /dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
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| /dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
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| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/cpu/armv7/exynos/ |
| H A D | spl_boot.c | 113 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
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| /dports/sysutils/u-boot-bananapim2/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
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| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
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| /dports/sysutils/u-boot-tools/u-boot-2020.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 115 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-rpi4/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 112 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-rpi2/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-riotboard/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|
| /dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
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| /dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
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| /dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | spl_boot.c | 116 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ in exynos_spi_copy()
|