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/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c291 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause() local
293 cause = readl(&src_regs->srsr); in get_reset_cause()
294 writel(cause, &src_regs->srsr); in get_reset_cause()
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c291 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause() local
293 cause = readl(&src_regs->srsr); in get_reset_cause()
294 writel(cause, &src_regs->srsr); in get_reset_cause()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c291 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause() local
293 cause = readl(&src_regs->srsr); in get_reset_cause()
294 writel(cause, &src_regs->srsr); in get_reset_cause()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c291 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause() local
293 cause = readl(&src_regs->srsr); in get_reset_cause()
294 writel(cause, &src_regs->srsr); in get_reset_cause()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/
H A Dcpu.c34 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause() local
36 cause = readl(&src_regs->srsr); in get_reset_cause()
37 writel(cause, &src_regs->srsr); in get_reset_cause()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/mx7/
H A Dddr.c31 struct src *const src_regs = (struct src *)SRC_BASE_ADDR; in mx7_dram_cfg() local
41 writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr); in mx7_dram_cfg()
75 clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK); in mx7_dram_cfg()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c283 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause() local
285 cause = readl(&src_regs->srsr); in get_reset_cause()
286 writel(cause, &src_regs->srsr); in get_reset_cause()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-imx/
H A Dcpu.c34 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause() local
36 cause = readl(&src_regs->srsr); in get_reset_cause()
37 writel(cause, &src_regs->srsr); in get_reset_cause()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c283 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause() local
285 cause = readl(&src_regs->srsr); in get_reset_cause()
286 writel(cause, &src_regs->srsr); in get_reset_cause()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c291 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause() local
293 cause = readl(&src_regs->srsr); in get_reset_cause()
294 writel(cause, &src_regs->srsr); in get_reset_cause()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c291 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause() local
293 cause = readl(&src_regs->srsr); in get_reset_cause()
294 writel(cause, &src_regs->srsr); in get_reset_cause()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c291 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause() local
293 cause = readl(&src_regs->srsr); in get_reset_cause()
294 writel(cause, &src_regs->srsr); in get_reset_cause()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-imx/
H A Dcpu.c38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause() local
41 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
44 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()

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