| /dports/math/boolector/boolector-3.2.2/test/log/ |
| H A D | hd11.btor | 9 7 srl 32 6 2
10 8 srl 32 4 2
14 11 srl 32 1 2
20 16 srl 32 15 2
21 17 srl 32 1 2
26 21 srl 32 1 3
34 28 srl 32 27 2
|
| /dports/devel/z88dk/z88dk/libsrc/games/ |
| H A D | synth_phase.asm | 28 srl a
29 srl a
30 srl a
31 srl a
37 srl a
38 srl a
39 srl a
40 srl a
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
|
| /dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/gas/testsuite/gas/mips/ |
| H A D | ush.d | 11 0+0004 <[^>]*> srl at,a0,0x8
14 0+0010 <[^>]*> srl at,a0,0x8
18 0+0020 <[^>]*> srl a0,a0,0x8
24 0+0038 <[^>]*> srl at,a0,0x8
28 0+0048 <[^>]*> srl a0,a0,0x8
36 0+0068 <[^>]*> srl a0,a0,0x8
42 0+0080 <[^>]*> srl at,a0,0x8
45 0+008c <[^>]*> srl at,a0,0x8
52 0+00a0 <[^>]*> srl a0,a0,0x8
62 0+00c0 <[^>]*> srl a0,a0,0x8
[all …]
|
| /dports/lang/gnatdroid-binutils-x86/binutils-2.27/gas/testsuite/gas/mips/ |
| H A D | ush.d | 11 0+0004 <[^>]*> srl at,a0,0x8
14 0+0010 <[^>]*> srl at,a0,0x8
18 0+0020 <[^>]*> srl a0,a0,0x8
24 0+0038 <[^>]*> srl at,a0,0x8
28 0+0048 <[^>]*> srl a0,a0,0x8
36 0+0068 <[^>]*> srl a0,a0,0x8
42 0+0080 <[^>]*> srl at,a0,0x8
45 0+008c <[^>]*> srl at,a0,0x8
52 0+00a0 <[^>]*> srl a0,a0,0x8
62 0+00c0 <[^>]*> srl a0,a0,0x8
[all …]
|
| /dports/lang/gnatdroid-binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| H A D | ush.d | 11 0+0004 <[^>]*> srl at,a0,0x8
14 0+0010 <[^>]*> srl at,a0,0x8
18 0+0020 <[^>]*> srl a0,a0,0x8
24 0+0038 <[^>]*> srl at,a0,0x8
28 0+0048 <[^>]*> srl a0,a0,0x8
36 0+0068 <[^>]*> srl a0,a0,0x8
42 0+0080 <[^>]*> srl at,a0,0x8
45 0+008c <[^>]*> srl at,a0,0x8
52 0+00a0 <[^>]*> srl a0,a0,0x8
62 0+00c0 <[^>]*> srl a0,a0,0x8
[all …]
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/gas/testsuite/gas/mips/ |
| H A D | ush.d | 11 0+0004 <[^>]*> srl at,a0,0x8
14 0+0010 <[^>]*> srl at,a0,0x8
18 0+0020 <[^>]*> srl a0,a0,0x8
24 0+0038 <[^>]*> srl at,a0,0x8
28 0+0048 <[^>]*> srl a0,a0,0x8
36 0+0068 <[^>]*> srl a0,a0,0x8
42 0+0080 <[^>]*> srl at,a0,0x8
45 0+008c <[^>]*> srl at,a0,0x8
52 0+00a0 <[^>]*> srl a0,a0,0x8
62 0+00c0 <[^>]*> srl a0,a0,0x8
[all …]
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/gas/testsuite/gas/mips/ |
| H A D | ush.d | 11 0+0004 <[^>]*> srl at,a0,0x8
14 0+0010 <[^>]*> srl at,a0,0x8
18 0+0020 <[^>]*> srl a0,a0,0x8
24 0+0038 <[^>]*> srl at,a0,0x8
28 0+0048 <[^>]*> srl a0,a0,0x8
36 0+0068 <[^>]*> srl a0,a0,0x8
42 0+0080 <[^>]*> srl at,a0,0x8
45 0+008c <[^>]*> srl at,a0,0x8
52 0+00a0 <[^>]*> srl a0,a0,0x8
62 0+00c0 <[^>]*> srl a0,a0,0x8
[all …]
|
| /dports/devel/djgpp-binutils/binutils-2.17/gas/testsuite/gas/mips/ |
| H A D | ush.d | 11 0+0004 <[^>]*> srl at,a0,0x8
14 0+0010 <[^>]*> srl at,a0,0x8
18 0+0020 <[^>]*> srl a0,a0,0x8
24 0+0038 <[^>]*> srl at,a0,0x8
28 0+0048 <[^>]*> srl a0,a0,0x8
36 0+0068 <[^>]*> srl a0,a0,0x8
42 0+0080 <[^>]*> srl at,a0,0x8
45 0+008c <[^>]*> srl at,a0,0x8
52 0+00a0 <[^>]*> srl a0,a0,0x8
62 0+00c0 <[^>]*> srl a0,a0,0x8
[all …]
|
| /dports/devel/gettext-tools/gettext-0.21/gettext-tools/tests/ |
| H A D | recode-sr-latin-1 | 25 cat <<\EOF > rec-srl-1.in
36 ${RECODE}-sr-latin < rec-srl-1.in > rec-srl-1.tmp.out \
38 LC_ALL=C tr -d '\r' < rec-srl-1.tmp.out > rec-srl-1.out || Exit 1
40 cat <<\EOF > rec-srl-1.ok
50 ${DIFF} rec-srl-1.ok rec-srl-1.out
|
| /dports/lang/gauche/Gauche-0.9.10/ext/sxml/ |
| H A D | sxml-serializer.scm.in | 11 ;;; Prefix for global identifiers in this module is `srl:'
19 (export srl:sxml->string srl:display-sxml srl:parameterizable
20 srl:sxml->xml srl:sxml->xml-noindent srl:sxml->html
21 srl:sxml->html-noindent ))
|