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/dports/misc/mxnet/incubator-mxnet-1.9.0/3rdparty/mkldnn/src/cpu/
H A Dcpu_pooling_list.cpp54 CPU_INSTANCE_X64(jit_uni_pooling_fwd_t<sse41, f32>)
55 CPU_INSTANCE_X64(jit_uni_pooling_bwd_t<sse41, f32>)
73 CPU_INSTANCE_X64(jit_uni_i8i8_pooling_fwd_t<sse41>)
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/X86/
H A Dpr14161.ll3 declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>)
13 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
32 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/X86/
H A Dpr14161.ll3 declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>)
13 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
32 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/X86/
H A Dpr14161.ll3 declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>)
13 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
32 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
/dports/math/onednn/oneDNN-2.5.1/src/cpu/
H A Dcpu_pooling_list.cpp51 CPU_INSTANCE_X64(jit_uni_pooling_fwd_t<sse41, f32>)
62 CPU_INSTANCE_X64(jit_uni_i8i8_pooling_fwd_t<sse41>)
75 CPU_INSTANCE_X64(jit_uni_pooling_bwd_t<sse41, f32>)
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/X86/
H A Dpr14161.ll3 declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>)
13 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
32 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
/dports/devel/ispc/ispc-1.16.1/builtins/
H A Dtarget-avx-common.ll47 declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone
68 %xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 8)
77 %xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 9)
86 %xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 10)
98 %xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 8)
107 %xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 9)
116 %xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 10)
251 declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
252 declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
253 declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
[all …]
H A Dtarget-avx1-i32x8.ll41 binary4to8(ret, i32, @llvm.x86.sse41.pminsd, %0, %1)
46 binary4to8(ret, i32, @llvm.x86.sse41.pmaxsd, %0, %1)
55 binary4to8(ret, i32, @llvm.x86.sse41.pminud, %0, %1)
60 binary4to8(ret, i32, @llvm.x86.sse41.pmaxud, %0, %1)
H A Dtarget-avx1-i32x16.ll40 binary4to16(ret, i32, @llvm.x86.sse41.pminsd, %0, %1)
45 binary4to16(ret, i32, @llvm.x86.sse41.pmaxsd, %0, %1)
54 binary4to16(ret, i32, @llvm.x86.sse41.pminud, %0, %1)
59 binary4to16(ret, i32, @llvm.x86.sse41.pmaxud, %0, %1)
/dports/lang/rust/rustc-1.58.1-src/library/stdarch/crates/core_arch/src/x86_64/
H A Dmod.rs15 mod sse41; module
16 pub use self::sse41::*;
/dports/misc/mxnet/incubator-mxnet-1.9.0/3rdparty/mkldnn/src/cpu/x64/
H A Dcpu_isa_traits.hpp105 sse41 = sse41_bit, enumerator
106 avx = avx_bit | sse41,
199 struct cpu_isa_traits<sse41> {
294 case sse41: return cpu().has(Cpu::tSSE41); in mayiuse()
349 ((isa) == sse41 ? prefix STRINGIFY(sse41) : \
/dports/math/onednn/oneDNN-2.5.1/src/cpu/x64/
H A Dcpu_isa_traits.hpp107 sse41 = sse41_bit, enumerator
108 avx = avx_bit | sse41,
199 struct cpu_isa_traits<sse41> {
304 case sse41: return cpu().has(Cpu::tSSE41); in mayiuse()
360 ((isa) == sse41 ? prefix STRINGIFY(sse41) : \
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/X86/
H A Dpr14161.ll4 declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>)
14 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
33 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
H A Dvector-shuffle-sse41.ll15 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
16 %p1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a2, <4 x i32> %a3)
51 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
59 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>)
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/X86/
H A Dpr14161.ll4 declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>)
14 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
33 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
H A Dvector-shuffle-sse41.ll15 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
16 %p1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a2, <4 x i32> %a3)
51 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
59 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>)
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/X86/
H A Dpr14161.ll4 declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>)
14 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
33 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
H A Dvector-shuffle-sse41.ll15 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
16 %p1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a2, <4 x i32> %a3)
51 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
59 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>)
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/X86/
H A Dvector-shuffle-sse41.ll15 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
16 %p1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a2, <4 x i32> %a3)
51 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
59 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>)
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dvector-shuffle-sse41.ll15 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
16 %p1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a2, <4 x i32> %a3)
51 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
59 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>)
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/X86/
H A Dvector-shuffle-sse41.ll15 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
16 %p1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a2, <4 x i32> %a3)
51 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
59 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>)
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dvector-shuffle-sse41.ll15 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
16 %p1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a2, <4 x i32> %a3)
51 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
59 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>)
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dvector-shuffle-sse41.ll15 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
16 %p1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a2, <4 x i32> %a3)
51 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
59 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>)
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/X86/
H A Dpr14161.ll3 declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>)
14 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
34 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/X86/
H A Dpr14161.ll3 declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>)
14 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…
34 …%3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32…

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