/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-st1-addressing-mode-reg-imm.ll | 13 ; CHECK: st1b { z0.b }, p0, [x0, #7, mul vl] 24 ; CHECK: st1b { z0.b }, p0, [x0, #1, mul vl] 35 ; CHECK: st1b { z0.b }, p0, [x0, #-8, mul vl] 47 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]] 59 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]] 70 ; CHECK: st1b { z0.s }, p0, [x0, #7, mul vl] 82 ; CHECK: st1b { z0.h }, p0, [x0, #1, mul vl] 94 ; CHECK: st1b { z0.d }, p0, [x0, #-7, mul vl]
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H A D | sve-masked-ldst-trunc.ll | 13 ; CHECK-NEXT: st1b { z0.d }, p0, [x1] 40 ; CHECK-NEXT: st1b { z0.s }, p0, [x1] 58 ; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-st1-addressing-mode-reg-imm.ll | 9 ; CHECK: st1b { z0.b }, p0, [x0, #7, mul vl] 20 ; CHECK: st1b { z0.b }, p0, [x0, #1, mul vl] 31 ; CHECK: st1b { z0.b }, p0, [x0, #-8, mul vl] 43 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]] 55 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]] 66 ; CHECK: st1b { z0.s }, p0, [x0, #7, mul vl] 78 ; CHECK: st1b { z0.h }, p0, [x0, #1, mul vl] 90 ; CHECK: st1b { z0.d }, p0, [x0, #-7, mul vl]
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H A D | sve-fixed-length-int-log.ll | 56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 450 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 465 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 480 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 495 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 766 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 781 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 796 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] [all …]
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H A D | sve-split-store.ll | 10 ; CHECK-NEXT: st1b { z0.s }, p0, [x0] 62 ; CHECK-NEXT: st1b { z0.d }, p0, [x0] 71 ; CHECK-NEXT: st1b { z1.b }, p1, [x0, #1, mul vl] 72 ; CHECK-NEXT: st1b { z0.b }, p0, [x0]
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H A D | sve-masked-ldst-trunc.ll | 9 ; CHECK-NEXT: st1b { z0.d }, p0, [x1] 36 ; CHECK-NEXT: st1b { z0.s }, p0, [x1] 54 ; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-st1-addressing-mode-reg-imm.ll | 9 ; CHECK: st1b { z0.b }, p0, [x0, #7, mul vl] 20 ; CHECK: st1b { z0.b }, p0, [x0, #1, mul vl] 31 ; CHECK: st1b { z0.b }, p0, [x0, #-8, mul vl] 43 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]] 55 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]] 66 ; CHECK: st1b { z0.s }, p0, [x0, #7, mul vl] 78 ; CHECK: st1b { z0.h }, p0, [x0, #1, mul vl] 90 ; CHECK: st1b { z0.d }, p0, [x0, #-7, mul vl]
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H A D | sve-fixed-length-int-log.ll | 56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 450 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 465 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 480 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 495 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 766 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 781 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 796 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] [all …]
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H A D | sve-masked-ldst-trunc.ll | 9 ; CHECK-NEXT: st1b { z0.d }, p0, [x1] 36 ; CHECK-NEXT: st1b { z0.s }, p0, [x1] 54 ; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-st1-addressing-mode-reg-imm.ll | 13 ; CHECK: st1b { z0.b }, p0, [x0, #7, mul vl] 24 ; CHECK: st1b { z0.b }, p0, [x0, #1, mul vl] 35 ; CHECK: st1b { z0.b }, p0, [x0, #-8, mul vl] 47 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]] 59 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]] 70 ; CHECK: st1b { z0.s }, p0, [x0, #7, mul vl] 82 ; CHECK: st1b { z0.h }, p0, [x0, #1, mul vl] 94 ; CHECK: st1b { z0.d }, p0, [x0, #-7, mul vl]
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H A D | sve-fixed-length-int-log.ll | 56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 450 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 465 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 480 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 495 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 766 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 781 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 796 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-intrinsics-st1-addressing-mode-reg-imm.ll | 9 ; CHECK: st1b { z0.b }, p0, [x0, #7, mul vl] 20 ; CHECK: st1b { z0.b }, p0, [x0, #1, mul vl] 31 ; CHECK: st1b { z0.b }, p0, [x0, #-8, mul vl] 43 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]] 55 ; CHECK: st1b { z0.b }, p0, [x0, x[[OFFSET]]] 66 ; CHECK: st1b { z0.s }, p0, [x0, #7, mul vl] 78 ; CHECK: st1b { z0.h }, p0, [x0, #1, mul vl] 90 ; CHECK: st1b { z0.d }, p0, [x0, #-7, mul vl]
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H A D | sve-fixed-length-int-log.ll | 56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 450 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 465 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 480 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 495 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 766 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 781 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 796 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/VE/ |
H A D | store.ll | 79 ; CHECK-NEXT: st1b %s1, (, %s0) 89 ; CHECK-NEXT: st1b %s1, (, %s0) 155 ; CHECK-NEXT: st1b %s0, 176(, %s11)
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/VE/ |
H A D | store.ll | 79 ; CHECK-NEXT: st1b %s1, (, %s0) 89 ; CHECK-NEXT: st1b %s1, (, %s0) 155 ; CHECK-NEXT: st1b %s0, 176(, %s11)
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/ |
H A D | sve-fixed-length-int-log.ll | 56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 450 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 465 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 480 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 495 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 766 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 781 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 796 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] [all …]
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H A D | sve-masked-ldst-trunc.ll | 13 ; CHECK-NEXT: st1b { z0.d }, p0, [x1] 40 ; CHECK-NEXT: st1b { z0.s }, p0, [x1] 58 ; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-fixed-length-int-log.ll | 56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 450 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 465 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 480 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 495 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 766 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 781 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 796 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] [all …]
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H A D | sve-masked-ldst-trunc.ll | 9 ; CHECK-NEXT: st1b { z0.d }, p0, [x1] 36 ; CHECK-NEXT: st1b { z0.s }, p0, [x1] 54 ; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/ |
H A D | sve-fixed-length-int-log.ll | 56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 450 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 465 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 480 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 495 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 766 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 781 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 796 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] [all …]
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H A D | sve-masked-ldst-trunc.ll | 9 ; CHECK-NEXT: st1b { z0.d }, p0, [x1] 36 ; CHECK-NEXT: st1b { z0.s }, p0, [x1] 54 ; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | sve-fixed-length-int-log.ll | 56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 450 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 465 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 480 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 495 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 766 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 781 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 796 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] [all …]
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H A D | sve-masked-ldst-trunc.ll | 13 ; CHECK-NEXT: st1b { z0.d }, p0, [x1] 40 ; CHECK-NEXT: st1b { z0.s }, p0, [x1] 58 ; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AArch64/ |
H A D | sve-masked-ldst-trunc.ll | 13 ; CHECK-NEXT: st1b { z0.d }, p0, [x1] 40 ; CHECK-NEXT: st1b { z0.s }, p0, [x1] 58 ; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AArch64/ |
H A D | sve-masked-ldst-trunc.ll | 9 ; CHECK-NEXT: st1b { z0.d }, p0, [x1] 36 ; CHECK-NEXT: st1b { z0.s }, p0, [x1] 54 ; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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