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Searched refs:stsr (Results 26 – 50 of 85) sorted by relevance

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/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/ic/
H A Datw.c2946 u_int32_t ackmask = 0, opmode, stsr, test0; in atw_idle() local
2966 stsr = ATW_READ(sc, ATW_STSR); in atw_idle()
2967 if ((stsr & ackmask) == ackmask) in atw_idle()
2972 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); in atw_idle()
2974 if ((stsr & ackmask) == ackmask) in atw_idle()
2979 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && in atw_idle()
2985 device_xname(sc->sc_dev), bits, test0, stsr); in atw_idle()
2988 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && in atw_idle()
2994 device_xname(sc->sc_dev), bits, test0, stsr)); in atw_idle()
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/v850/
H A DChangeLog358 (stsr, ldsr): Correct src, dest fields. Fix tracing.
376 v850.insn (movea, stsr): Use.
407 * simops.c (OP_2007E0, OP_4007E0): Move "ldsr", "stsr"
409 * v850.igen (ldsr, stsr): To here. Mask out reserved bits when
1117 register within the sregs array. Handle "ldsr" and "stsr".
H A Dv850.igen1047 rrrrr,111111,regID + 0000000001000000:IX:::stsr
1048 "stsr s<regID>, r<reg2>"
/dports/devel/avr-gdb/gdb-7.3.1/sim/v850/
H A DChangeLog482 (stsr, ldsr): Correct src, dest fields. Fix tracing.
500 v850.insn (movea, stsr): Use.
531 * simops.c (OP_2007E0, OP_4007E0): Move "ldsr", "stsr"
533 * v850.igen (ldsr, stsr): To here. Mask out reserved bits when
1241 register within the sregs array. Handle "ldsr" and "stsr".
H A Dv850.igen1047 rrrrr,111111,regID + 0000000001000000:IX:::stsr
1048 "stsr s<regID>, r<reg2>"
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/v850/
H A DChangeLog358 (stsr, ldsr): Correct src, dest fields. Fix tracing.
376 v850.insn (movea, stsr): Use.
407 * simops.c (OP_2007E0, OP_4007E0): Move "ldsr", "stsr"
409 * v850.igen (ldsr, stsr): To here. Mask out reserved bits when
1117 register within the sregs array. Handle "ldsr" and "stsr".
H A Dv850.igen1047 rrrrr,111111,regID + 0000000001000000:IX:::stsr
1048 "stsr s<regID>, r<reg2>"
/dports/devel/gdb761/gdb-7.6.1/sim/v850/
H A DChangeLog599 (stsr, ldsr): Correct src, dest fields. Fix tracing.
617 v850.insn (movea, stsr): Use.
648 * simops.c (OP_2007E0, OP_4007E0): Move "ldsr", "stsr"
650 * v850.igen (ldsr, stsr): To here. Mask out reserved bits when
1358 register within the sregs array. Handle "ldsr" and "stsr".
H A Dv850.igen2076 rrrrr,111111,regID + 0000000001000000:IX:::stsr
2077 "stsr s<regID>, r<reg2>"
/dports/textproc/link-grammar/link-grammar-5.8.0/data/ar/words/
H A Dwords.PV_V1074 <stsr.PVV
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/gcc/config/v850/
H A Dv850.md1725 output_asm_insn (\"stsr ctpc, r10\", operands);
1727 output_asm_insn (\"stsr ctpsw, r10\", operands);
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gcc/gcc/config/v850/
H A Dv850.md1725 output_asm_insn (\"stsr ctpc, r10\", operands);
1727 output_asm_insn (\"stsr ctpsw, r10\", operands);
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/gcc-4.1-20060728/gcc/config/v850/
H A Dv850.md1736 output_asm_insn (\"stsr ctpc, r10\", operands);
1738 output_asm_insn (\"stsr ctpsw, r10\", operands);
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/v850/
H A Dv850.md2838 output_asm_insn ("stsr ctpc, r10", operands);
2840 output_asm_insn ("stsr ctpsw, r10", operands);
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/v850/
H A Dv850.md2838 output_asm_insn ("stsr ctpc, r10", operands);
2840 output_asm_insn ("stsr ctpsw, r10", operands);
/dports/lang/gnat_util/gcc-6-20180516/gcc/config/v850/
H A Dv850.md2838 output_asm_insn ("stsr ctpc, r10", operands);
2840 output_asm_insn ("stsr ctpsw, r10", operands);
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/v850/
H A Dv850.md2838 output_asm_insn ("stsr ctpc, r10", operands);
2840 output_asm_insn ("stsr ctpsw, r10", operands);
/dports/lang/gcc48/gcc-4.8.5/gcc/config/v850/
H A Dv850.md2850 output_asm_insn ("stsr ctpc, r10", operands);
2852 output_asm_insn ("stsr ctpsw, r10", operands);
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/config/v850/
H A Dv850.md2850 output_asm_insn ("stsr ctpc, r10", operands);
2852 output_asm_insn ("stsr ctpsw, r10", operands);
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/v850/
H A Dv850.md2838 output_asm_insn ("stsr ctpc, r10", operands);
2840 output_asm_insn ("stsr ctpsw, r10", operands);
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/v850/
H A Dv850.md2838 output_asm_insn ("stsr ctpc, r10", operands);
2840 output_asm_insn ("stsr ctpsw, r10", operands);
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/v850/
H A Dv850.md2838 output_asm_insn ("stsr ctpc, r10", operands);
2840 output_asm_insn ("stsr ctpsw, r10", operands);
/dports/lang/gcc8/gcc-8.5.0/gcc/config/v850/
H A Dv850.md2838 output_asm_insn ("stsr ctpc, r10", operands);
2840 output_asm_insn ("stsr ctpsw, r10", operands);
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/v850/
H A Dv850.md2838 output_asm_insn ("stsr ctpc, r10", operands);
2840 output_asm_insn ("stsr ctpsw, r10", operands);
/dports/lang/gcc9/gcc-9.4.0/gcc/config/v850/
H A Dv850.md2897 output_asm_insn ("stsr ctpc, r10", operands);
2899 output_asm_insn ("stsr ctpsw, r10", operands);

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