| /dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/arm/ |
| H A D | neon.md | 2635 (define_insn "neon_v<r>subhn<mode>"
2641 "v<r>subhn.<V_if_elem>\t%P0, %q1, %q2"
|
| /dports/lang/gcc10/gcc-10.3.0/gcc/config/arm/ |
| H A D | neon.md | 2635 (define_insn "neon_v<r>subhn<mode>"
2641 "v<r>subhn.<V_if_elem>\t%P0, %q1, %q2"
|
| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/arm/ |
| H A D | neon.md | 2920 (define_insn "neon_v<r>subhn<mode>"
2926 "v<r>subhn.<V_if_elem>\t%P0, %q1, %q2"
|
| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/arm/ |
| H A D | neon.md | 2920 (define_insn "neon_v<r>subhn<mode>"
2926 "v<r>subhn.<V_if_elem>\t%P0, %q1, %q2"
|
| /dports/lang/v8/v8-9.6.180.12/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 4427 subhn(vf, rd, rn, rm); in VisitNEON3Different()
|
| H A D | simulator-logic-arm64.cc | 2790 LogicVRegister Simulator::subhn(VectorFormat vform, LogicVRegister dst, in subhn() function in v8::internal::Simulator
|
| /dports/www/firefox-esr/firefox-91.8.0/js/src/jit/arm64/vixl/ |
| H A D | Logic-vixl.cpp | 3121 LogicVRegister Simulator::subhn(VectorFormat vform, in subhn() function in vixl::Simulator
|
| H A D | Assembler-vixl.cpp | 2139 V(subhn, NEON_SUBHN, vd.IsD()) \
|
| /dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 2790 LogicVRegister Simulator::subhn(VectorFormat vform, LogicVRegister dst, in subhn() function in v8::internal::Simulator
|
| H A D | simulator-arm64.cc | 4353 subhn(vf, rd, rn, rm); in VisitNEON3Different()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 4356 subhn(vf, rd, rn, rm); in VisitNEON3Different()
|
| H A D | simulator-logic-arm64.cc | 2790 LogicVRegister Simulator::subhn(VectorFormat vform, LogicVRegister dst, in subhn() function in v8::internal::Simulator
|
| /dports/www/firefox/firefox-99.0/js/src/jit/arm64/vixl/ |
| H A D | Logic-vixl.cpp | 3121 LogicVRegister Simulator::subhn(VectorFormat vform, in subhn() function in vixl::Simulator
|
| /dports/www/node10/node-v10.24.1/deps/v8/src/arm64/ |
| H A D | simulator-logic-arm64.cc | 2791 LogicVRegister Simulator::subhn(VectorFormat vform, LogicVRegister dst, in subhn() function in v8::internal::Simulator
|
| H A D | simulator-arm64.cc | 4127 subhn(vf, rd, rn, rm); in VisitNEON3Different()
|
| /dports/www/firefox-legacy/firefox-52.8.0esr/js/src/jit/arm64/vixl/ |
| H A D | Logic-vixl.cpp | 3352 LogicVRegister Simulator::subhn(VectorFormat vform, in subhn() function in vixl::Simulator
|
| /dports/lang/spidermonkey60/firefox-60.9.0/js/src/jit/arm64/vixl/ |
| H A D | Logic-vixl.cpp | 3352 LogicVRegister Simulator::subhn(VectorFormat vform, in subhn() function in vixl::Simulator
|
| /dports/mail/thunderbird/thunderbird-91.8.0/js/src/jit/arm64/vixl/ |
| H A D | Logic-vixl.cpp | 3121 LogicVRegister Simulator::subhn(VectorFormat vform, in subhn() function in vixl::Simulator
|
| /dports/lang/spidermonkey78/firefox-78.9.0/js/src/jit/arm64/vixl/ |
| H A D | Logic-vixl.cpp | 3058 LogicVRegister Simulator::subhn(VectorFormat vform, in subhn() function in vixl::Simulator
|
| H A D | Assembler-vixl.cpp | 2130 V(subhn, NEON_SUBHN, vd.IsD()) \
|
| /dports/databases/mongodb36/mongodb-src-r3.6.23/src/third_party/mozjs-45/extract/js/src/jit/arm64/vixl/ |
| H A D | Logic-vixl.cpp | 3350 LogicVRegister Simulator::subhn(VectorFormat vform, in subhn() function in vixl::Simulator
|
| /dports/devel/binutils/binutils-2.37/gas/ |
| H A D | ChangeLog-2006 | 1997 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
|
| /dports/lang/gnatdroid-binutils-x86/binutils-2.27/gas/ |
| H A D | ChangeLog-2006 | 1997 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
|
| /dports/devel/arm-elf-binutils/binutils-2.37/gas/ |
| H A D | ChangeLog-2006 | 1997 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
|
| /dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.cc | 1444 V(subhn, NEON_SUBHN, vd.IsD()) \
|