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/dports/devel/llvm13/llvm-project-13.0.1.src/polly/test/ScopInfo/
H A Dassume_gep_bounds_many.ll550 %j22.0 = phi i64 [ 0, %bb242 ], [ %tmp275, %bb274 ]
605 %tmp275 = add nuw nsw i64 %j22.0, 1
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsi-spill-cf.ll415 %tmp275 = fmul float %tmp272, undef
418 %tmp278 = call float @llvm.maxnum.f32(float %tmp269, float %tmp275)
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/math/fftw-float/fftw-2.1.5/fftw/
H A Dftwi_64.c1746 fftw_real tmp275; in fftwi_twiddle_64() local
1751 tmp275 = c_re(inout[45 * iostride]); in fftwi_twiddle_64()
1755 tmp278 = (tmp274 * tmp275) + (tmp276 * tmp277); in fftwi_twiddle_64()
1756 tmp500 = (tmp274 * tmp277) - (tmp276 * tmp275); in fftwi_twiddle_64()
H A Dftw_64.c1746 fftw_real tmp275; in fftw_twiddle_64() local
1751 tmp275 = c_re(inout[45 * iostride]); in fftw_twiddle_64()
1755 tmp278 = (tmp274 * tmp275) - (tmp276 * tmp277); in fftw_twiddle_64()
1756 tmp495 = (tmp276 * tmp275) + (tmp274 * tmp277); in fftw_twiddle_64()
/dports/math/fftw/fftw-2.1.5/fftw/
H A Dftw_64.c1746 fftw_real tmp275; in fftw_twiddle_64() local
1751 tmp275 = c_re(inout[45 * iostride]); in fftw_twiddle_64()
1755 tmp278 = (tmp274 * tmp275) - (tmp276 * tmp277); in fftw_twiddle_64()
1756 tmp495 = (tmp276 * tmp275) + (tmp274 * tmp277); in fftw_twiddle_64()
H A Dftwi_64.c1746 fftw_real tmp275; in fftwi_twiddle_64() local
1751 tmp275 = c_re(inout[45 * iostride]); in fftwi_twiddle_64()
1755 tmp278 = (tmp274 * tmp275) + (tmp276 * tmp277); in fftwi_twiddle_64()
1756 tmp500 = (tmp274 * tmp277) - (tmp276 * tmp275); in fftwi_twiddle_64()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
H A Dvgpr-spill-emergency-stack-slot-compute.ll475 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 125
476 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 126
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
H A Dvgpr-spill-emergency-stack-slot-compute.ll475 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 125
476 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 126
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dvgpr-spill-emergency-stack-slot.ll338 %tmp275 = insertelement <128 x float> %tmp274, float %tmp139, i32 113
339 %tmp276 = insertelement <128 x float> %tmp275, float %tmp140, i32 114
/dports/graphics/appleseed/appleseed-2.1.0-beta/sandbox/tests/test scenes/osl/_shaders/
H A Das_color_texture.oso374 temp int $tmp275 %read{344,344} %write{343,343}
899 add $tmp275 $tmp274 $const12 %argrw{"wrr"}
900 add $tmp276 $tmp275 $const4 %argrw{"wrr"}
H A Das_scalar_texture.oso374 temp int $tmp275 %read{344,344} %write{343,343}
899 add $tmp275 $tmp274 $const12 %argrw{"wrr"}
900 add $tmp276 $tmp275 $const4 %argrw{"wrr"}

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