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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit.ll363 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
366 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-regpressure-limit3.ll362 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
365 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dschedule-ilp.ll360 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
363 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-regpressure-limit.ll363 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
366 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-regpressure-limit3.ll362 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
365 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit.ll363 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
366 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-regpressure-limit3.ll362 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
365 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-ilp.ll360 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
363 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit.ll363 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
366 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-ilp.ll360 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
363 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-regpressure-limit3.ll362 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
365 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit3.ll362 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
365 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-regpressure-limit.ll363 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
366 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-ilp.ll360 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
363 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-ilp.ll360 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
363 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit.ll363 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
366 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-regpressure-limit3.ll362 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
365 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-ilp.ll360 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
363 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit.ll363 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
366 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-regpressure-limit3.ll362 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
365 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-ilp.ll360 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
363 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit3.ll362 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
365 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-ilp.ll360 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
363 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
H A Dschedule-regpressure-limit.ll363 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
366 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-ilp.ll360 %tmp354 = load float, float addrspace(3)* %tmp353, align 4
363 %tmp357 = tail call float @llvm.fmuladd.f32(float %tmp352, float %tmp354, float %tmp356)

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