Home
last modified time | relevance | path

Searched refs:tmp406 (Results 126 – 150 of 217) sorted by relevance

123456789

/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit3.ll414 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
571 store float %tmp406, float addrspace(1)* %tmp505, align 4
H A Dschedule-ilp.ll412 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
569 store float %tmp406, float addrspace(1)* %tmp505, align 4
H A Dschedule-regpressure-limit.ll415 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
572 store float %tmp406, float addrspace(1)* %tmp505, align 4
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-ilp.ll412 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
569 store float %tmp406, float addrspace(1)* %tmp505, align 4
H A Dschedule-regpressure-limit3.ll414 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
571 store float %tmp406, float addrspace(1)* %tmp505, align 4
H A Dschedule-regpressure-limit.ll415 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
572 store float %tmp406, float addrspace(1)* %tmp505, align 4
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit.ll415 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
572 store float %tmp406, float addrspace(1)* %tmp505, align 4
H A Dschedule-ilp.ll412 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
569 store float %tmp406, float addrspace(1)* %tmp505, align 4
H A Dschedule-regpressure-limit3.ll414 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
571 store float %tmp406, float addrspace(1)* %tmp505, align 4
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-ilp.ll412 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
569 store float %tmp406, float addrspace(1)* %tmp505, align 4
H A Dschedule-regpressure-limit.ll415 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
572 store float %tmp406, float addrspace(1)* %tmp505, align 4
H A Dschedule-regpressure-limit3.ll414 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
571 store float %tmp406, float addrspace(1)* %tmp505, align 4
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dschedule-ilp.ll412 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
569 store float %tmp406, float addrspace(1)* %tmp505, align 4
H A Dschedule-regpressure-limit3.ll414 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
571 store float %tmp406, float addrspace(1)* %tmp505, align 4
H A Dschedule-regpressure-limit.ll415 %tmp406 = tail call float @llvm.fmuladd.f32(float %tmp401, float %tmp403, float %tmp405)
572 store float %tmp406, float addrspace(1)* %tmp505, align 4
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/LoopStrengthReduce/
H A Dlsr-comp-time.ll601 …%tmp406 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %tmp9, i64 0, i64 %tmp4…
602 %tmp407 = load i32, i32* %tmp406, align 4
604 store i32 %tmp408, i32* %tmp406, align 4
/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/LoopStrengthReduce/
H A Dlsr-comp-time.ll601 …%tmp406 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %tmp9, i64 0, i64 %tmp4…
602 %tmp407 = load i32, i32* %tmp406, align 4
604 store i32 %tmp408, i32* %tmp406, align 4
/dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/LoopStrengthReduce/
H A Dlsr-comp-time.ll601 …%tmp406 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %tmp9, i64 0, i64 %tmp4…
602 %tmp407 = load i32, i32* %tmp406, align 4
604 store i32 %tmp408, i32* %tmp406, align 4
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/LoopStrengthReduce/
H A Dlsr-comp-time.ll601 …%tmp406 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %tmp9, i64 0, i64 %tmp4…
602 %tmp407 = load i32, i32* %tmp406, align 4
604 store i32 %tmp408, i32* %tmp406, align 4
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/LoopStrengthReduce/
H A Dlsr-comp-time.ll601 …%tmp406 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %tmp9, i64 0, i64 %tmp4…
602 %tmp407 = load i32, i32* %tmp406, align 4
604 store i32 %tmp408, i32* %tmp406, align 4
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/LoopStrengthReduce/
H A Dlsr-comp-time.ll601 …%tmp406 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %tmp9, i64 0, i64 %tmp4…
602 %tmp407 = load i32, i32* %tmp406, align 4
604 store i32 %tmp408, i32* %tmp406, align 4
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/LoopStrengthReduce/
H A Dlsr-comp-time.ll601 …%tmp406 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %tmp9, i64 0, i64 %tmp4…
602 %tmp407 = load i32, i32* %tmp406, align 4
604 store i32 %tmp408, i32* %tmp406, align 4
/dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/LoopStrengthReduce/
H A Dlsr-comp-time.ll601 …%tmp406 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %tmp9, i64 0, i64 %tmp4…
602 %tmp407 = load i32, i32* %tmp406, align 4
604 store i32 %tmp408, i32* %tmp406, align 4
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/LoopStrengthReduce/
H A Dlsr-comp-time.ll601 …%tmp406 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %tmp9, i64 0, i64 %tmp4…
602 %tmp407 = load i32, i32* %tmp406, align 4
604 store i32 %tmp408, i32* %tmp406, align 4
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/LoopStrengthReduce/
H A Dlsr-comp-time.ll601 …%tmp406 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %tmp9, i64 0, i64 %tmp4…
602 %tmp407 = load i32, i32* %tmp406, align 4
604 store i32 %tmp408, i32* %tmp406, align 4

123456789