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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/
H A DADSP-EDN-BF544-extended_cdef.h11 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
14 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) argument
17 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) argument
20 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) argument
23 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) argument
26 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) argument
29 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) argument
32 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) argument
35 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) argument
38 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) argument
[all …]
H A DADSP-EDN-BF549-extended_cdef.h11 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
14 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) argument
17 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) argument
20 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) argument
23 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) argument
26 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) argument
29 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) argument
32 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) argument
35 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) argument
38 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) argument
[all …]
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/
H A DADSP-EDN-BF544-extended_cdef.h11 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
14 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) argument
17 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) argument
20 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) argument
23 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) argument
26 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) argument
29 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) argument
32 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) argument
35 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) argument
38 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) argument
[all …]
H A DADSP-EDN-BF549-extended_cdef.h11 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
14 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) argument
17 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) argument
20 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) argument
23 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) argument
26 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) argument
29 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) argument
32 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) argument
35 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) argument
38 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) argument
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/
H A DADSP-EDN-BF544-extended_cdef.h11 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
14 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) argument
17 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) argument
20 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) argument
23 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) argument
26 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) argument
29 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) argument
32 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) argument
35 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) argument
38 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) argument
[all …]
H A DADSP-EDN-BF549-extended_cdef.h11 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
14 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) argument
17 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) argument
20 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) argument
23 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) argument
26 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) argument
29 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) argument
32 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) argument
35 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) argument
38 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) argument
[all …]
/dports/archivers/c-blosc2/c-blosc2-2.0.4/contrib/bitshuffle_neon/bitunshuffle8_neon/
H A Dbitunshuffle8_neon.c48 r1[0].val[0] = vpadd_u8(r1[0].val[0], r1[0].val[0]); in bitunshuffle8_neon()
49 r1[0].val[0] = vpadd_u8(r1[0].val[0], r1[0].val[0]); in bitunshuffle8_neon()
50 r1[0].val[0] = vpadd_u8(r1[0].val[0], r1[0].val[0]); in bitunshuffle8_neon()
51 r1[0].val[1] = vpadd_u8(r1[0].val[1], r1[0].val[1]); in bitunshuffle8_neon()
52 r1[0].val[1] = vpadd_u8(r1[0].val[1], r1[0].val[1]); in bitunshuffle8_neon()
53 r1[0].val[1] = vpadd_u8(r1[0].val[1], r1[0].val[1]); in bitunshuffle8_neon()
54 r1[1].val[0] = vpadd_u8(r1[1].val[0], r1[1].val[0]); in bitunshuffle8_neon()
55 r1[1].val[0] = vpadd_u8(r1[1].val[0], r1[1].val[0]); in bitunshuffle8_neon()
56 r1[1].val[0] = vpadd_u8(r1[1].val[0], r1[1].val[0]); in bitunshuffle8_neon()
57 r1[1].val[1] = vpadd_u8(r1[1].val[1], r1[1].val[1]); in bitunshuffle8_neon()
[all …]
/dports/games/libretro-mame2003_plus/mame2003-plus-libretro-17e9889/src/machine/
H A Ddecoprot.c1307 …val=((val&0x0003)<<6) | ((val&0x000c)<<2) | ((val&0x00f0)<<4) | ((val&0x0f00)<<4) | ((val&0xf000)>… in READ16_HANDLER()
1312 …val=((val&0x0003)<<10) | ((val&0x000c)<<6) | ((val&0x00f0)<<8) | ((val&0x0f00)>>8) | ((val&0xf000)… in READ16_HANDLER()
1327 …val=((val&0x000e)<<3) | ((val&0x0001)<<7) | ((val&0x00f0)<<4) | ((val&0x0f00)<<4) | ((val&0xf000)>… in READ16_HANDLER()
1332 val=((val&0x000f)<<0) | ((val&0x00f0)<<4) | ((val&0x0f00)<<4) | ((val&0xf000)>>8); in READ16_HANDLER()
1367 …val=((val&0x000e)<<3) | ((val&0x0001)<<7) | ((val&0x00f0)<<4) | ((val&0xf000)>>12) | ((val&0x0f00)… in READ16_HANDLER()
1412 val=((val&0xf000)>>4) | ((val&0x0f00)>>8)| ((val&0x00f0)<<8) | ((val&0x000f)<<4); in READ16_HANDLER()
1543 val=((val&0xff00)>>8) | ((val&0x00f0)<<8)| ((val&0x0007)<<9) | ((val&0x0008)<<5); in READ16_HANDLER()
1556 …val=((val&0xf000)>>12) | ((val&0x0f00)<<4)| ((val&0x00f0)<<4) | ((val&0x000e)<<3) | ((val&0x0001)<… in READ16_HANDLER()
1566 val=((val&0xf000)>>4) | ((val&0x0f00)>>4)| ((val&0x00f0)<<8) | ((val&0x000f)<<0); in READ16_HANDLER()
1571 val=((val&0xf000)>>4) | ((val&0x0f00)<<4)| ((val&0x00f0)<<0) | ((val&0x000f)<<0); in READ16_HANDLER()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/
H A DADSP-EDN-BF549-extended_cdef.h11 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
14 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) argument
17 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) argument
20 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) argument
23 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) argument
26 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) argument
29 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) argument
32 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) argument
35 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) argument
38 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) argument
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/
H A DADSP-EDN-BF549-extended_cdef.h11 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
14 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) argument
17 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) argument
20 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) argument
23 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) argument
26 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) argument
29 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) argument
32 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) argument
35 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) argument
38 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) argument
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/
H A DADSP-EDN-BF549-extended_cdef.h11 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
14 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
17 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
20 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
23 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
26 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
29 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
32 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
35 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
38 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/
H A DADSP-EDN-BF549-extended_cdef.h11 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
14 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) argument
17 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) argument
20 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) argument
23 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) argument
26 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) argument
29 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) argument
32 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) argument
35 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) argument
38 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) argument
[all …]
/dports/emulators/mess/mame-mame0226/src/devices/video/
H A Dvoodoo.h516 (a) = (((val) >> 8) & 0xf8) | (((val) >> 13) & 0x07); \
517 (b) = (((val) >> 3) & 0xfc) | (((val) >> 9) & 0x03); \
518 (c) = (((val) << 3) & 0xf8) | (((val) >> 2) & 0x07);
520 (a) = (((val) >> 7) & 0xf8) | (((val) >> 12) & 0x07); \
522 (c) = (((val) << 3) & 0xf8) | (((val) >> 2) & 0x07);
526 (c) = (((val) << 2) & 0xf8) | (((val) >> 3) & 0x07);
550 (d) = (((val) << 4) & 0xf0) | (((val) >> 0) & 0x0f);
552 (a) = (((val) >> 0) & 0xe0) | (((val) >> 3) & 0x1c) | (((val) >> 6) & 0x03); \
553 (b) = (((val) << 3) & 0xe0) | (((val) >> 0) & 0x1c) | (((val) >> 3) & 0x03); \
554 …(c) = (((val) << 6) & 0xc0) | (((val) << 4) & 0x30) | (((val) << 2) & 0x0c) | (((val) << 0) & 0x03…
[all …]
/dports/emulators/mame/mame-mame0226/src/devices/video/
H A Dvoodoo.h516 (a) = (((val) >> 8) & 0xf8) | (((val) >> 13) & 0x07); \
517 (b) = (((val) >> 3) & 0xfc) | (((val) >> 9) & 0x03); \
518 (c) = (((val) << 3) & 0xf8) | (((val) >> 2) & 0x07);
520 (a) = (((val) >> 7) & 0xf8) | (((val) >> 12) & 0x07); \
522 (c) = (((val) << 3) & 0xf8) | (((val) >> 2) & 0x07);
526 (c) = (((val) << 2) & 0xf8) | (((val) >> 3) & 0x07);
550 (d) = (((val) << 4) & 0xf0) | (((val) >> 0) & 0x0f);
552 (a) = (((val) >> 0) & 0xe0) | (((val) >> 3) & 0x1c) | (((val) >> 6) & 0x03); \
553 (b) = (((val) << 3) & 0xe0) | (((val) >> 0) & 0x1c) | (((val) >> 3) & 0x03); \
554 …(c) = (((val) << 6) & 0xc0) | (((val) << 4) & 0x30) | (((val) << 2) & 0x0c) | (((val) << 0) & 0x03…
[all …]
/dports/archivers/c-blosc2/c-blosc2-2.0.4/blosc/
H A Dbitshuffle-neon.c273 r0[0].val[0] = vpadd_u8(r0[0].val[0], r0[0].val[0]); in bitshuffle8_neon()
274 r0[0].val[0] = vpadd_u8(r0[0].val[0], r0[0].val[0]); in bitshuffle8_neon()
275 r0[0].val[0] = vpadd_u8(r0[0].val[0], r0[0].val[0]); in bitshuffle8_neon()
276 r0[0].val[1] = vpadd_u8(r0[0].val[1], r0[0].val[1]); in bitshuffle8_neon()
277 r0[0].val[1] = vpadd_u8(r0[0].val[1], r0[0].val[1]); in bitshuffle8_neon()
278 r0[0].val[1] = vpadd_u8(r0[0].val[1], r0[0].val[1]); in bitshuffle8_neon()
279 r0[1].val[0] = vpadd_u8(r0[1].val[0], r0[1].val[0]); in bitshuffle8_neon()
280 r0[1].val[0] = vpadd_u8(r0[1].val[0], r0[1].val[0]); in bitshuffle8_neon()
281 r0[1].val[0] = vpadd_u8(r0[1].val[0], r0[1].val[0]); in bitshuffle8_neon()
282 r0[1].val[1] = vpadd_u8(r0[1].val[1], r0[1].val[1]); in bitshuffle8_neon()
[all …]
/dports/lang/zig-devel/zig-0.9.0/lib/std/fmt/errol/
H A Dlookup.zig2 val: f64,
6 HP{ .val = 1.000000e+308, .off = -1.097906362944045488e+291 },
7 HP{ .val = 1.000000e+307, .off = 1.396894023974354241e+290 },
8 HP{ .val = 1.000000e+306, .off = -1.721606459673645508e+289 },
9 HP{ .val = 1.000000e+305, .off = 6.074644749446353973e+288 },
10 HP{ .val = 1.000000e+304, .off = 6.074644749446353567e+287 },
11 HP{ .val = 1.000000e+303, .off = -1.617650767864564452e+284 },
12 HP{ .val = 1.000000e+302, .off = -7.629703079084895055e+285 },
13 HP{ .val = 1.000000e+301, .off = -5.250476025520442286e+284 },
14 HP{ .val = 1.000000e+300, .off = -5.250476025520441956e+283 },
[all …]
/dports/lang/zig/zig-0.9.0/lib/std/fmt/errol/
H A Dlookup.zig2 val: f64,
6 HP{ .val = 1.000000e+308, .off = -1.097906362944045488e+291 },
7 HP{ .val = 1.000000e+307, .off = 1.396894023974354241e+290 },
8 HP{ .val = 1.000000e+306, .off = -1.721606459673645508e+289 },
9 HP{ .val = 1.000000e+305, .off = 6.074644749446353973e+288 },
10 HP{ .val = 1.000000e+304, .off = 6.074644749446353567e+287 },
11 HP{ .val = 1.000000e+303, .off = -1.617650767864564452e+284 },
12 HP{ .val = 1.000000e+302, .off = -7.629703079084895055e+285 },
13 HP{ .val = 1.000000e+301, .off = -5.250476025520442286e+284 },
14 HP{ .val = 1.000000e+300, .off = -5.250476025520441956e+283 },
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/drivers/net/vxge/
H A Dvxge_reg.h29 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
30 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
67 #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF) argument
78 #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff) argument
79 #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff) argument
899 #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) argument
1959 #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) argument
1993 #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) argument
4002 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) argument
4405 #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) argument
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/drivers/net/vxge/
H A Dvxge_reg.h29 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
30 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
67 #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF) argument
78 #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff) argument
79 #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff) argument
899 #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) argument
1959 #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) argument
1993 #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) argument
4002 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) argument
4405 #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) argument
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/drivers/net/vxge/
H A Dvxge_reg.h29 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
30 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
67 #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF) argument
78 #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff) argument
79 #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff) argument
899 #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) argument
1959 #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) argument
1993 #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) argument
4002 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) argument
4405 #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) argument
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/drivers/net/vxge/
H A Dvxge_reg.h29 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
30 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
67 #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF) argument
78 #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff) argument
79 #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff) argument
899 #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) argument
1959 #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) argument
1993 #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) argument
4002 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) argument
4405 #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) argument
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/drivers/net/vxge/
H A Dvxge_reg.h29 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
30 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
67 #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF) argument
78 #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff) argument
79 #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff) argument
899 #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) argument
1959 #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) argument
1993 #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) argument
4002 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) argument
4405 #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) argument
[all …]
/dports/net/ipxe/ipxe-2265a65/src/drivers/net/vxge/
H A Dvxge_reg.h29 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
30 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
67 #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF) argument
78 #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff) argument
79 #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff) argument
899 #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) argument
1959 #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) argument
1993 #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) argument
4002 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) argument
4405 #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) argument
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/drivers/net/vxge/
H A Dvxge_reg.h29 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
30 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
67 #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF) argument
78 #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff) argument
79 #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff) argument
899 #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) argument
1959 #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) argument
1993 #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) argument
4002 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) argument
4405 #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) argument
[all …]
/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/drivers/net/vxge/
H A Dvxge_reg.h29 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
30 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
67 #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF) argument
78 #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff) argument
79 #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff) argument
899 #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) argument
1959 #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) argument
1993 #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) argument
4002 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) argument
4405 #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) argument
[all …]

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