/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankcombiner-umed3.mir | 11 liveins: $vgpr0, $sgpr30_sgpr31 23 %0:vgpr(s32) = COPY $vgpr0 31 $vgpr0 = COPY %5(s32) 55 %0:vgpr(s32) = COPY $vgpr0 63 $vgpr0 = COPY %5(s32) 95 $vgpr0 = COPY %5(s32) 127 $vgpr0 = COPY %5(s32) 159 $vgpr0 = COPY %5(s32) 191 $vgpr0 = COPY %5(s32) 223 $vgpr0 = COPY %5(s32) [all …]
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H A D | inst-select-sextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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H A D | inst-select-zextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/ |
H A D | vmem-vcc-hazard.mir | 18 $vgpr0 = IMPLICIT_DEF 38 $vgpr0 = IMPLICIT_DEF 55 $vgpr0 = IMPLICIT_DEF 76 $vgpr0 = IMPLICIT_DEF 97 $vgpr0 = IMPLICIT_DEF 124 $vgpr0 = IMPLICIT_DEF 129 $vgpr0 = IMPLICIT_DEF 148 $vgpr0 = IMPLICIT_DEF 173 $vgpr0 = IMPLICIT_DEF 194 $vgpr0 = IMPLICIT_DEF [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/ |
H A D | vmem-vcc-hazard.mir | 18 $vgpr0 = IMPLICIT_DEF 38 $vgpr0 = IMPLICIT_DEF 55 $vgpr0 = IMPLICIT_DEF 76 $vgpr0 = IMPLICIT_DEF 97 $vgpr0 = IMPLICIT_DEF 124 $vgpr0 = IMPLICIT_DEF 129 $vgpr0 = IMPLICIT_DEF 148 $vgpr0 = IMPLICIT_DEF 173 $vgpr0 = IMPLICIT_DEF 194 $vgpr0 = IMPLICIT_DEF [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/ |
H A D | vmem-vcc-hazard.mir | 18 $vgpr0 = IMPLICIT_DEF 38 $vgpr0 = IMPLICIT_DEF 55 $vgpr0 = IMPLICIT_DEF 76 $vgpr0 = IMPLICIT_DEF 97 $vgpr0 = IMPLICIT_DEF 124 $vgpr0 = IMPLICIT_DEF 129 $vgpr0 = IMPLICIT_DEF 148 $vgpr0 = IMPLICIT_DEF 173 $vgpr0 = IMPLICIT_DEF 194 $vgpr0 = IMPLICIT_DEF [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/ |
H A D | vmem-vcc-hazard.mir | 18 $vgpr0 = IMPLICIT_DEF 38 $vgpr0 = IMPLICIT_DEF 55 $vgpr0 = IMPLICIT_DEF 76 $vgpr0 = IMPLICIT_DEF 97 $vgpr0 = IMPLICIT_DEF 124 $vgpr0 = IMPLICIT_DEF 129 $vgpr0 = IMPLICIT_DEF 148 $vgpr0 = IMPLICIT_DEF 173 $vgpr0 = IMPLICIT_DEF 194 $vgpr0 = IMPLICIT_DEF [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/ |
H A D | vmem-vcc-hazard.mir | 18 $vgpr0 = IMPLICIT_DEF 38 $vgpr0 = IMPLICIT_DEF 55 $vgpr0 = IMPLICIT_DEF 76 $vgpr0 = IMPLICIT_DEF 97 $vgpr0 = IMPLICIT_DEF 124 $vgpr0 = IMPLICIT_DEF 129 $vgpr0 = IMPLICIT_DEF 148 $vgpr0 = IMPLICIT_DEF 173 $vgpr0 = IMPLICIT_DEF 194 $vgpr0 = IMPLICIT_DEF [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/ |
H A D | spill-special-sgpr.mir | 50 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 52 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 53 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 59 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 61 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 62 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit killed $vcc 67 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 87 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 88 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 96 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | spill-special-sgpr.mir | 50 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 52 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 53 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 59 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 61 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 62 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit killed $vcc 67 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 87 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 88 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 96 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/ |
H A D | spill-special-sgpr.mir | 50 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 52 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 53 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 59 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 61 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 62 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit killed $vcc 67 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 87 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 88 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 96 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/ |
H A D | spill-special-sgpr.mir | 50 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 52 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 53 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 59 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 61 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 62 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit killed $vcc 67 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 87 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 88 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 96 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | spill-special-sgpr.mir | 50 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 52 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 53 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 59 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 61 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 62 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit killed $vcc 67 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 87 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 88 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 96 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | spill-special-sgpr.mir | 50 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 52 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 53 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 59 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 61 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 62 ; GFX9: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit killed $vcc 67 ; GFX9: $exec = S_MOV_B64 3, implicit-def $vgpr0 87 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc 88 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc 96 ; GFX10: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | inst-select-sextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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H A D | inst-select-zextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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H A D | inst-select-fptosi.mir | 13 liveins: $vgpr0 27 $vgpr0 = COPY %1 52 $vgpr0 = COPY %1 63 liveins: $vgpr0 78 $vgpr0 = COPY %2 89 liveins: $vgpr0 106 $vgpr0 = COPY %2 134 $vgpr0 = COPY %2 145 liveins: $vgpr0 178 liveins: $vgpr0 [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | inst-select-zextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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H A D | inst-select-sextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | inst-select-sextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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H A D | inst-select-zextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | inst-select-sextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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H A D | inst-select-zextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | inst-select-sextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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H A D | inst-select-zextload-local.mir | 16 liveins: $vgpr0 19 ; GFX6: liveins: $vgpr0 24 ; GFX7: liveins: $vgpr0 29 ; GFX9: liveins: $vgpr0 35 $vgpr0 = COPY %1 47 liveins: $vgpr0 66 $vgpr0 = COPY %1 78 # liveins: $vgpr0 83 # $vgpr0 = COPY %2 95 liveins: $vgpr0 [all …]
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