/freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEISelLowering.cpp | 2193 Register DstReg; in emitEHSjLjSetJmp() local 2195 DstReg = MI.getOperand(0).getReg(); in emitEHSjLjSetJmp() 2196 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); in emitEHSjLjSetJmp() 2278 BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(VE::PHI), DstReg) in emitEHSjLjSetJmp()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFrameLowering.cpp | 286 void copyToScratchSGPR(Register DstReg) const { in copyToScratchSGPR() 287 BuildMI(MBB, MI, DL, TII->get(AMDGPU::COPY), DstReg) in copyToScratchSGPR()
|
H A D | SIISelLowering.cpp | 4319 Register DstReg = MI.getOperand(0).getReg(); in loadM0FromVGPR() local 4338 InitResultReg, DstReg, PhiReg, TmpExec, in loadM0FromVGPR() 4612 Register DstReg = MI.getOperand(0).getReg(); in lowerWaveReduce() local 4617 BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addReg(SrcReg); in lowerWaveReduce() 4638 const TargetRegisterClass *DstRegClass = MRI.getRegClass(DstReg); in lowerWaveReduce() 4682 auto NewAccumulator = BuildMI(*ComputeLoop, I, DL, TII->get(Opc), DstReg) in lowerWaveReduce() 5259 const Register DstReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local 5268 BuildMI(*BB, &MI, DL, TII->get(AMDGPU::COPY), DstReg).addReg(MaskReg); in EmitInstrWithCustomInserter()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 516 unsigned DstReg = createResultReg(&AArch64::GPR64commonRegClass); in materializeGV() local 518 DstReg) in materializeGV() 523 ADRPReg = DstReg; in materializeGV() 2996 Register DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC); in fastLowerArguments() local 3003 .addReg(DstReg, getKillRegState(true)); in fastLowerArguments()
|
H A D | AArch64FrameLowering.cpp | 3660 Register DstReg = RS->FindUnusedReg(&AArch64::GPR64commonRegClass); in processFunctionBeforeFrameFinalized() local 3661 assert(DstReg && "There must be a free register after frame setup"); in processFunctionBeforeFrameFinalized() 3662 BuildMI(MBB, MBBI, DL, TII.get(AArch64::MOVi64imm), DstReg).addImm(-2); in processFunctionBeforeFrameFinalized() 3664 .addReg(DstReg, getKillRegState(true)) in processFunctionBeforeFrameFinalized()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.td | 229 def RET : IForm16<0b0100, DstReg, SrcPostInc, 2, 302 def POP16r : IForm16<0b0100, DstReg, SrcPostInc, 2,
|
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | IRTranslator.cpp | 1775 void IRTranslator::getStackGuard(Register DstReg, in getStackGuard() argument 1778 MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF)); in getStackGuard() 1780 MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {}); in getStackGuard()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 1629 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, in emitSignExtendToI32InReg() argument 1635 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); in emitSignExtendToI32InReg() 1640 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); in emitSignExtendToI32InReg() 1653 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 1867 Register DstReg = MI.getOperand(0).getReg(); in insertShift() local 1895 BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg) in insertShift()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 1036 Register &SrcReg, Register &DstReg, in isCoalescableExtInstr() argument 1044 DstReg = MI.getOperand(0).getReg(); in isCoalescableExtInstr() 1507 Register DstReg, Register TrueReg, in canInsertSelect() argument
|
H A D | PPCISelLowering.cpp | 12242 Register DstReg = MI.getOperand(0).getReg(); in emitEHSjLjSetJmp() local 12243 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); in emitEHSjLjSetJmp() 12363 TII->get(PPC::PHI), DstReg) in emitEHSjLjSetJmp() 12544 Register DstReg = MI.getOperand(0).getReg(); in emitProbedAlloca() local 12647 BuildMI(TailMBB, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4), DstReg) in emitProbedAlloca()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 3975 MCRegister DstReg = Inst.getOperand(0).getReg(); in validateMFMA() local 3976 if (Src2Reg == DstReg) in validateMFMA() 3983 if (TRI->regsOverlap(Src2Reg, DstReg)) { in validateMFMA()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 9229 Register DstReg = MRI->createVirtualRegister(RC); in emitLoadAndTestCmp0() local 9233 BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg) in emitLoadAndTestCmp0() 9248 Register DstReg = MI.getOperand(0).getReg(); in emitProbedAlloca() local 9324 BuildMI(*MBB, MBB->begin(), DL, TII->get(TargetOpcode::COPY), DstReg) in emitProbedAlloca()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 16655 Register DstReg = MI.getOperand(0).getReg(); in emitBuildPairF64Pseudo() local 16679 TII.loadRegFromStackSlot(*BB, MI, DstReg, FI, DstRC, RI, Register()); in emitBuildPairF64Pseudo() 16704 Register DstReg = MI.getOperand(0).getReg(); in emitQuietFCMP() local 16714 auto MIB = BuildMI(*BB, MI, DL, TII.get(RelOpcode), DstReg) in emitQuietFCMP() 17109 Register DstReg = MI.getOperand(0).getReg(); in emitFROUND() local 17152 BuildMI(*DoneMBB, DoneMBB->begin(), DL, TII.get(RISCV::PHI), DstReg) in emitFROUND()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 33972 Register DstReg = MI.getOperand(0).getReg(); in emitXBegin() local 33973 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); in emitXBegin() 34002 BuildMI(*sinkMBB, sinkMBB->begin(), MIMD, TII->get(X86::PHI), DstReg) in emitXBegin() 35265 unsigned DstReg; in emitEHSjLjSetJmp() local 35270 DstReg = MI.getOperand(CurOp++).getReg(); in emitEHSjLjSetJmp() 35271 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); in emitEHSjLjSetJmp() 35378 BuildMI(*sinkMBB, sinkMBB->begin(), MIMD, TII->get(X86::PHI), DstReg) in emitEHSjLjSetJmp()
|