Home
last modified time | relevance | path

Searched refs:ST (Results 101 – 125 of 675) sorted by relevance

12345678910>>...27

/freebsd/contrib/llvm-project/openmp/runtime/src/
H A Dkmp_dispatch.cpp212 traits_t<ST>::spec, traits_t<ST>::spec, in __kmp_dispatch_init_algorithm()
1235 test_then_inc<ST>((volatile ST *)&sh->u.s.ordered_iteration); in __kmp_dispatch_finish()
1312 test_then_add<ST>((volatile ST *)&sh->u.s.ordered_iteration, inc); in __kmp_dispatch_finish_chunk()
1334 ST incr; in __kmp_dispatch_next_algorithm()
1835 if (compare_and_swap<ST>(RCAST(volatile ST *, &sh->u.s.iteration), in __kmp_dispatch_next_algorithm()
1836 (ST)init, (ST)limit)) { in __kmp_dispatch_next_algorithm()
1910 if (compare_and_swap<ST>(RCAST(volatile ST *, &sh->u.s.iteration), in __kmp_dispatch_next_algorithm()
1911 (ST)init, (ST)limit)) { in __kmp_dispatch_next_algorithm()
2042 index = test_then_inc<ST>((volatile ST *)&sh->u.s.iteration); in __kmp_dispatch_next_algorithm()
2230 ST incr; in __kmp_dispatch_next()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILateBranchLowering.cpp85 const GCNSubtarget &ST = MBB.getParent()->getSubtarget<GCNSubtarget>(); in generateEndPgm() local
87 ST.hasNullExportTarget() in generateEndPgm()
149 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
150 TII = ST.getInstrInfo(); in runOnMachineFunction()
154 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in runOnMachineFunction()
155 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
H A DSIFormMemoryClauses.cpp70 const GCNSubtarget *ST; member in __anonc3f4ae940111::SIFormMemoryClauses
195 unsigned Occupancy = MaxPressure.getOccupancy(*ST); in checkPressure()
207 MaxPressure.getVGPRNum(ST->hasGFX90AInsts()) <= MaxVGPRs / 2 && in checkPressure()
261 ST = &MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
262 if (!ST->isXNACKEnabled()) in runOnMachineFunction()
265 const SIInstrInfo *TII = ST->getInstrInfo(); in runOnMachineFunction()
266 TRI = ST->getRegisterInfo(); in runOnMachineFunction()
H A DGCNNSAReassign.cpp67 const GCNSubtarget *ST; member in __anonc64e7db10111::GCNNSAReassign
239 ST = &MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
240 if (!ST->hasNSAEncoding() || !ST->hasNonNSAEncoding()) in runOnMachineFunction()
244 TRI = ST->getRegisterInfo(); in runOnMachineFunction()
250 MaxNumVGPRs = ST->getMaxNumVGPRs(MF); in runOnMachineFunction()
251 MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(MFI->getOccupancy()), MaxNumVGPRs); in runOnMachineFunction()
H A DSILowerSGPRSpills.cpp93 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in insertCSRSaves() local
94 const SIRegisterInfo *RI = ST.getRegisterInfo(); in insertCSRSaves()
136 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in insertCSRRestores() local
137 const SIRegisterInfo *RI = ST.getRegisterInfo(); in insertCSRRestores()
213 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in spillCalleeSavedRegs() local
214 const SIFrameLowering *TFI = ST.getFrameLowering(); in spillCalleeSavedRegs()
309 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
310 TII = ST.getInstrInfo(); in runOnMachineFunction()
H A DR600MCInstLower.cpp26 R600MCInstLower(MCContext &ctx, const R600Subtarget &ST,
34 R600MCInstLower::R600MCInstLower(MCContext &Ctx, const R600Subtarget &ST, in R600MCInstLower() argument
36 : AMDGPUMCInstLower(Ctx, ST, AP) {} in R600MCInstLower()
H A DAMDGPUSubtarget.cpp952 if (!ST.hasMAIInsts()) in apply()
1037 const GCNSubtarget &ST) in GCNUserSGPRUsageInfo() argument
1038 : ST(ST) { in GCNUserSGPRUsageInfo()
1052 bool IsAmdHsaOrMesa = ST.isAmdHsaOrMesa(F); in GCNUserSGPRUsageInfo()
1053 if (IsAmdHsaOrMesa && !ST.enableFlatScratch()) in GCNUserSGPRUsageInfo()
1055 else if (ST.isMesaGfxShader(F)) in GCNUserSGPRUsageInfo()
1073 if (ST.hasFlatAddressSpace() && AMDGPU::isEntryFunctionCC(CC) && in GCNUserSGPRUsageInfo()
1074 (IsAmdHsaOrMesa || ST.enableFlatScratch()) && in GCNUserSGPRUsageInfo()
1075 (HasCalls || HasStackObjects || ST.enableFlatScratch()) && in GCNUserSGPRUsageInfo()
1076 !ST.flatScratchIsArchitected()) { in GCNUserSGPRUsageInfo()
[all …]
H A DGCNPreRAOptimizations.cpp219 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
220 TII = ST.getInstrInfo(); in runOnMachineFunction()
223 TRI = ST.getRegisterInfo(); in runOnMachineFunction()
233 (ST.hasGFX90AInsts() || !TRI->isAGPRClass(RC))) in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertReadWriteCSR.cpp94 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction() local
95 if (!ST.hasVInstructions()) in runOnMachineFunction()
98 TII = ST.getInstrInfo(); in runOnMachineFunction()
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dste-hrefprev60-stuib.dts3 * Copyright 2012 ST-Ericsson AB
13 model = "ST-Ericsson HREF (pre-v60) and ST UIB";
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PreTileConfig.cpp240 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
241 const TargetInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
242 const TargetRegisterInfo *TRI = ST.getRegisterInfo(); in runOnMachineFunction()
338 ST.getTileConfigSize(), ST.getTileConfigAlignment(), false); in runOnMachineFunction()
380 if (ST.hasAVX512()) { in runOnMachineFunction()
385 } else if (ST.hasAVX2()) { in runOnMachineFunction()
393 assert(ST.hasSSE2() && "AMX should assume SSE2 enabled"); in runOnMachineFunction()
394 unsigned StoreOpc = ST.hasAVX() ? X86::VMOVUPSmr : X86::MOVUPSmr; in runOnMachineFunction()
H A DX86FixupInstTuning.cpp59 const X86Subtarget *ST = nullptr; member in __anon703ccb480111::X86FixupInstTuningPass
90 *ST, *(SM->getSchedClassDesc(TII->get(Opcode).getSchedClass()))); in processInstruction()
96 *ST, *(SM->getSchedClassDesc(TII->get(Opcode).getSchedClass()))); in processInstruction()
165 if (!ST->hasNoDomainDelayShuffle() || in processInstruction()
199 if (!ST->hasNoDomainDelayShuffle() || in processInstruction()
278 return ST->hasAVX2() ? ProcessVPERMILPSmi(X86::VPSHUFDYmi) : false; in processInstruction()
503 ST = &MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction()
504 TII = ST->getInstrInfo(); in runOnMachineFunction()
505 SM = &ST->getSchedModel(); in runOnMachineFunction()
H A DX86FixupVectorConstants.cpp53 const X86Subtarget *ST = nullptr; member in __anon94bc96e50111::X86FixupVectorConstantsPass
231 bool HasAVX2 = ST->hasAVX2(); in processInstruction()
232 bool HasDQI = ST->hasDQI(); in processInstruction()
233 bool HasBWI = ST->hasBWI(); in processInstruction()
234 bool HasVLX = ST->hasVLX(); in processInstruction()
445 ST = &MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction()
446 TII = ST->getInstrInfo(); in runOnMachineFunction()
447 SM = &ST->getSchedModel(); in runOnMachineFunction()
/freebsd/sys/amd64/amd64/
H A Ddb_disasm.c97 #define ST 31 /* FP stack top */ macro
523 /*0*/ { "fadd", SNGL, op2(STI,ST), 0 },
524 /*1*/ { "fmul", SNGL, op2(STI,ST), 0 },
525 /*2*/ { "fcom", SNGL, op2(STI,ST), 0 },
526 /*3*/ { "fcomp", SNGL, op2(STI,ST), 0 },
527 /*4*/ { "fsub", SNGL, op2(STI,ST), 0 },
528 /*5*/ { "fsubr", SNGL, op2(STI,ST), 0 },
529 /*6*/ { "fdiv", SNGL, op2(STI,ST), 0 },
530 /*7*/ { "fdivr", SNGL, op2(STI,ST), 0 },
1190 case op2(ST,STI): in db_disasm_esc()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp44 : ST(&ST) { in AArch64LegalizerInfo()
76 if (!ST.hasNEON() || !ST.hasFPARMv8()) { in AArch64LegalizerInfo()
86 const bool HasCSSC = ST.hasCSSC(); in AArch64LegalizerInfo()
87 const bool HasRCPC3 = ST.hasRCPC3(); in AArch64LegalizerInfo()
774 return ST.outlineAtomics() && !ST.hasLSE(); in AArch64LegalizerInfo()
974 if (ST.hasMOPS()) { in AArch64LegalizerInfo()
1184 verify(*ST.getInstrInfo()); in AArch64LegalizerInfo()
1373 (ST->isTargetDarwin() || ST->isTargetWindows()) in legalizeIntrinsic()
1609 ST->hasLSE2() && ST->hasRCPC3() && (IsLoadAcquire || IsStoreRelease); in legalizeLoadStore()
1778 if (!ST->hasNEON() || in legalizeCTPOP()
[all …]
/freebsd/contrib/llvm-project/clang/utils/TableGen/
H A DMveEmitter.cpp1001 return getVectorType(ST, 128 / ST->sizeInBits()); in getVectorType()
1180 if (!ST->requiresFloat()) { in getCodeForDag()
1183 ST, Arg->integerConstantValue()); in getCodeForDag()
1317 if (ST->isInteger() && ST->sizeInBits() < 32) in getCodeForArg()
1777 const ScalarType *ST = kv.second.get(); in EmitHeader() local
1778 if (ST->hasNonstandardName()) in EmitHeader()
1781 const VectorType *VT = getVectorType(ST); in EmitHeader()
2041 const ScalarType *ST = kv.second.get(); in EmitHeader() local
2042 if (ST->hasNonstandardName()) in EmitHeader()
2045 if (ST->kind() == ScalarTypeKind::Float && ST->sizeInBits() == 64) in EmitHeader()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVAsmPrinter.cpp47 : AsmPrinter(TM, std::move(Streamer)), ST(nullptr), TII(nullptr) {} in SPIRVAsmPrinter()
49 const SPIRVSubtarget *ST; member in __anona962702a0111::SPIRVAsmPrinter
113 ST = &MF->getSubtarget<SPIRVSubtarget>(); in emitFunctionHeader()
114 TII = ST->getInstrInfo(); in emitFunctionHeader()
305 if (ST->getSPIRVVersion() >= 14 || SC == SPIRV::StorageClass::Input || in outputEntryPoints()
329 MAI->Reqs.checkSatisfiable(*ST); in outputGlobalRequirements()
479 if (ST->isOpenCLEnv() && !M.getNamedMetadata("spirv.ExecutionMode") && in outputExecutionMode()
529 ST = static_cast<const SPIRVTargetMachine &>(TM).getSubtargetImpl(); in outputModuleSections()
530 TII = ST->getInstrInfo(); in outputModuleSections()
532 assert(ST && TII && MAI && M && "Module analysis is required"); in outputModuleSections()
H A DSPIRVLegalizerInfo.h28 const SPIRVSubtarget *ST; variable
34 SPIRVLegalizerInfo(const SPIRVSubtarget &ST);
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h172 const TargetSubtargetInfo &ST; variable
267 : Schedule(S), MF(MF), ST(MF.getSubtarget()), MRI(MF.getRegInfo()), in ModuloScheduleExpander()
268 TII(ST.getInstrInfo()), LIS(LIS), in ModuloScheduleExpander()
287 : Schedule(S), MF(MF), ST(MF.getSubtarget()), MRI(MF.getRegInfo()), in PeelingModuloScheduleExpander()
288 TII(ST.getInstrInfo()), LIS(LIS) {} in PeelingModuloScheduleExpander()
299 const TargetSubtargetInfo &ST; variable
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dst,nomadik-mtu.yaml8 title: ST Microelectronics Nomadik Multi-Timer Unit MTU Timer
13 description: This timer is found in the ST Microelectronics Nomadik
14 SoCs STn8800, STn8810 and STn8815 as well as in ST-Ericsson DB8500.
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDeadMachineInstructionElim.cpp111 const TargetSubtargetInfo &ST = MF.getSubtarget(); in runOnMachineFunction() local
112 TII = ST.getInstrInfo(); in runOnMachineFunction()
113 LivePhysRegs.init(*ST.getRegisterInfo()); in runOnMachineFunction()
H A DBasicTargetTransformInfo.cpp33 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), in BasicTTIImpl()
34 TLI(ST->getTargetLowering()) {} in BasicTTIImpl()
H A DMachineCycleAnalysis.cpp97 const TargetSubtargetInfo &ST = MF->getSubtarget(); in isCycleInvariant() local
98 const TargetRegisterInfo *TRI = ST.getRegisterInfo(); in isCycleInvariant()
99 const TargetInstrInfo *TII = ST.getInstrInfo(); in isCycleInvariant()
/freebsd/crypto/openssl/test/recipes/80-test_cmp_http_data/Mock/
H A Dsigner.crt1 Subject: C = AU, ST = Some-State, O = Internet Widgits Pty Ltd, CN = leaf
24 Subject: C = AU, ST = Some-State, O = Internet Widgits Pty Ltd, CN = subinterCA
47 Subject: C = AU, ST = Some-State, O = Internet Widgits Pty Ltd, CN = interCA
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DType.cpp378 StructType *ST; in get() local
388 ST = new (Context.pImpl->Alloc) StructType(Context); in get()
390 ST->setBody(ETypes, isPacked); in get()
391 *Insertion.first = ST; in get()
394 ST = *Insertion.first; in get()
397 return ST; in get()
516 ST->setName(Name); in create()
517 return ST; in create()
526 StructType *ST = create(Context, Name); in create() local
527 ST->setBody(Elements, isPacked); in create()
[all …]

12345678910>>...27