| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNDPPCombine.cpp | 57 const GCNSubtarget *ST; member in __anon5094b0140111::GCNDPPCombine
160 if (ST->hasVOP3DPP()) in getDPPOp()
213 bool HasVOP3DPP = ST->hasVOP3DPP(); in createDPPInst()
319 if (!ST->hasDPPSrc1SGPR()) { in createDPPInst()
670 ST->hasVOP3DPP()) || in combineDPPMov()
675 if (OrigMI.modifiesRegister(AMDGPU::EXEC, ST->getRegisterInfo())) { in combineDPPMov()
749 ST = &MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
750 if (!ST->hasDPP() || skipFunction(MF.getFunction())) in runOnMachineFunction()
754 TII = ST->getInstrInfo(); in runOnMachineFunction()
764 if (ST->hasDPALU_DPP() && combineDPPMov(MI)) { in runOnMachineFunction()
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| H A D | AMDGPUInsertDelayAlu.cpp | 426 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
427 if (!ST.hasDelayAlu()) in runOnMachineFunction()
430 SII = ST.getInstrInfo(); in runOnMachineFunction()
431 TRI = ST.getRegisterInfo(); in runOnMachineFunction()
433 SchedModel.init(&ST); in runOnMachineFunction()
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| H A D | SIPreEmitPeephole.cpp | 88 const GCNSubtarget &ST = MBB.getParent()->getSubtarget<GCNSubtarget>(); in optimizeVccBranch() local
89 const bool IsWave32 = ST.isWave32(); in optimizeVccBranch()
366 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
367 TII = ST.getInstrInfo(); in runOnMachineFunction()
389 if (!ST.hasVGPRIndexMode()) in runOnMachineFunction()
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| H A D | AMDGPUTargetTransformInfo.h | 43 const TargetSubtargetInfo *ST; variable
46 const TargetSubtargetInfo *getST() const { return ST; } in getST()
68 const GCNSubtarget *ST; variable
78 const GCNSubtarget *getST() const { return ST; } in getST()
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| H A D | SILowerI1Copies.h | 48 const GCNSubtarget *ST = nullptr; variable
77 ST->getWavefrontSize(); in isLaneMaskReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.h | 33 const X86Subtarget *ST; variable
36 const X86Subtarget *getST() const { return ST; } in getST()
113 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), in X86TTIImpl()
114 TLI(ST->getTargetLowering()) {} in X86TTIImpl()
285 return ST->getMaxInlineSizeThreshold(); in getMaxMemIntrinsicInlineSizeThreshold()
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| H A D | X86RegisterInfo.cpp | 653 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>(); in getNumSupportedRegs() local
654 if (ST.hasEGPR()) in getNumSupportedRegs()
656 if (ST.hasAMXTILE()) in getNumSupportedRegs()
658 if (ST.hasAVX512()) in getNumSupportedRegs()
660 if (ST.hasAVX()) in getNumSupportedRegs()
667 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>(); in isArgumentRegister() local
668 const TargetRegisterInfo &TRI = *ST.getRegisterInfo(); in isArgumentRegister()
673 if (!ST.is64Bit()) in isArgumentRegister()
694 if (ST.hasSSE1() && in isArgumentRegister()
706 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>(); in isFixedRegister() local
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| H A D | X86InsertWait.cpp | 100 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
101 const X86InstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVDuplicatesTracker.h | 265 SPIRVDuplicatesTracker<SPIRV::SpecialTypeDescriptor> ST;
289 ST.add(SPIRV::PointerTypeDescriptor(PointerElementType, AddressSpace), MF,
311 ST.add(TD, MF, R);
320 return ST.find(
342 return ST.find(TD, MF);
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| H A D | SPIRVSubtarget.h | 121 static bool classof(const TargetSubtargetInfo *ST) { in classof() argument
122 return ST->getTargetTriple().isSPIRV(); in classof()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Linker/ |
| H A D | IRMover.h | 32 KeyTy(const StructType *ST);
39 static unsigned getHashValue(const StructType *ST);
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | ste-hrefv60plus-tvk.dts | 3 * Copyright 2012 ST-Ericsson AB
15 model = "ST-Ericsson HREF (v60+) and TVK1281618 R2 UIB";
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVFoldMasks.cpp | 184 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction() local
185 if (!ST.hasVInstructions()) in runOnMachineFunction()
188 TII = ST.getInstrInfo(); in runOnMachineFunction()
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| /freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/ |
| H A D | st,stmfts.txt | 1 * ST-Microelectronics FingerTip touchscreen controller
3 The ST-Microelectronics FingerTip device provides a basic touchscreen
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| H A D | st,stmfts.yaml | 7 title: ST-Microelectronics FingerTip touchscreen controller
13 The ST-Microelectronics FingerTip device provides a basic touchscreen
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.h | 28 AArch64LegalizerInfo(const AArch64Subtarget &ST);
68 const AArch64Subtarget *ST; variable
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 479 StoreSDNode *ST = cast<StoreSDNode>(Op); in LowerSTORE() local
484 ST->getMemoryVT(), *ST->getMemOperand())) in LowerSTORE()
487 SDValue Chain = ST->getChain(); in LowerSTORE()
488 SDValue BasePtr = ST->getBasePtr(); in LowerSTORE()
489 SDValue Value = ST->getValue(); in LowerSTORE()
492 if (ST->getAlign() == Align(2)) { in LowerSTORE()
1685 StoreSDNode *ST = cast<StoreSDNode>(N); in PerformDAGCombine() local
1688 ST->getMemoryVT(), in PerformDAGCombine()
1690 ST->isVolatile() || ST->isIndexed()) { in PerformDAGCombine()
1693 SDValue Chain = ST->getChain(); in PerformDAGCombine()
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | ste-u300.txt | 1 ST-Ericsson U300 Device Tree Bindings
31 model = "ST-Ericsson U300";
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| /freebsd/sys/contrib/device-tree/Bindings/input/ |
| H A D | adafruit,seesaw-gamepad.yaml | 19 | \___/ |ST| |SE| (B) |
24 ST -> Start
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PostRASchedulerList.cpp | 104 const TargetSubtargetInfo &ST, CodeGenOptLevel OptLevel,
263 const TargetSubtargetInfo &ST, CodeGenOptLevel OptLevel, in enablePostRAScheduler() argument
266 Mode = ST.getAntiDepBreakMode(); in enablePostRAScheduler()
267 ST.getCriticalPathRCs(CriticalPathRCs); in enablePostRAScheduler()
273 return ST.enablePostRAScheduler() && in enablePostRAScheduler()
274 OptLevel >= ST.getOptLevelToEnablePostRAScheduler(); in enablePostRAScheduler()
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| H A D | MachineLoopInfo.cpp | 204 const TargetSubtargetInfo &ST = MF->getSubtarget(); in isLoopInvariant() local
205 const TargetRegisterInfo *TRI = ST.getRegisterInfo(); in isLoopInvariant()
206 const TargetInstrInfo *TII = ST.getInstrInfo(); in isLoopInvariant()
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| H A D | MacroFusion.cpp | 185 const TargetSubtargetInfo &ST = DAG.MF.getSubtarget(); in scheduleAdjacentImpl() local
188 if (!shouldScheduleAdjacent(TII, ST, nullptr, AnchorMI)) in scheduleAdjacentImpl()
204 !shouldScheduleAdjacent(TII, ST, DepMI, AnchorMI)) in scheduleAdjacentImpl()
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| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | sti-mailbox.txt | 1 ST Microelectronics Mailbox Driver
3 Each ST Mailbox IP currently consists of 4 instances of 32 channels. Messages
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| /freebsd/contrib/llvm-project/openmp/runtime/src/ |
| H A D | kmp_collapse.h | 55 typedef typename traits_t<T>::signed_t ST; typedef
87 ST step; // signed even if bounds type is unsigned
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineLoadStoreAlloca.cpp | 706 if (auto *ST = dyn_cast<StructType>(T)) { in unpackLoadToAggregate() local
708 auto NumElements = ST->getNumElements(); in unpackLoadToAggregate()
720 auto *SL = DL.getStructLayout(ST); in unpackLoadToAggregate()
740 auto *Ptr = IC.Builder.CreateInBoundsGEP(ST, Addr, ArrayRef(Indices), in unpackLoadToAggregate()
743 ST->getElementType(i), Ptr, in unpackLoadToAggregate()
1149 auto *ST = cast<StructType>(VT); in likeBitCastFromVector() local
1152 for (const auto *EltT : ST->elements()) { in likeBitCastFromVector()
1230 if (auto *ST = dyn_cast<StructType>(T)) { in unpackStoreToAggregate() local
1232 unsigned Count = ST->getNumElements(); in unpackStoreToAggregate()
1242 auto *SL = DL.getStructLayout(ST); in unpackStoreToAggregate()
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