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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVO0PreLegalizerCombiner.cpp130 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction() local
136 /*CSEInfo*/ nullptr, RuleConfig, ST); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp101 const GCNSubtarget *ST = nullptr; member in __anonb81b6ddd0111::AMDGPUCodeGenPrepareImpl
412 if (ST->hasVOP3PInsts()) in needsPromotionToI32()
633 if (Size <= 16 && ST->has16BitInsts()) in replaceMulWithMul24()
779 ST->hasFractBug() in getFrexpResults()
817 if (HasFP32DenormalFlush && ST->hasFractBug() && !ST->hasFastFMAF32() && in emitFrexpDiv()
1271 auto FMAD = !ST->hasMadMacF32Insts() in expandDivRem24Impl()
2042 if (ST->hasFractBug()) in matchFractPat()
2196 Impl.ST = &TM.getSubtarget<GCNSubtarget>(F); in runOnFunction()
2202 SIModeRegisterDefaults Mode(F, *Impl.ST); in runOnFunction()
2214 Impl.ST = &TM.getSubtarget<GCNSubtarget>(F); in run()
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H A DR600RegisterInfo.cpp39 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>(); in getReservedRegs() local
40 const R600InstrInfo *TII = ST.getInstrInfo(); in getReservedRegs()
H A DR600TargetTransformInfo.cpp28 ST(static_cast<const R600Subtarget *>(TM->getSubtargetImpl(F))), in R600TTIImpl()
29 TLI(ST->getTargetLowering()), CommonTTI(TM, F) {} in R600TTIImpl()
H A DAMDGPUHSAMetadataStreamer.cpp387 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitHiddenKernelArgs() local
389 unsigned HiddenArgNumBytes = ST.getImplicitArgNumBytes(Func); in emitHiddenKernelArgs()
397 Offset = alignTo(Offset, ST.getAlignmentForImplicitArgPtr()); in emitHiddenKernelArgs()
568 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitHiddenKernelArgs() local
571 if (ST.getImplicitArgNumBytes(Func) == 0) in emitHiddenKernelArgs()
582 Offset = alignTo(Offset, ST.getAlignmentForImplicitArgPtr()); in emitHiddenKernelArgs()
662 if (!ST.hasApertureRegs()) { in emitHiddenKernelArgs()
/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_segmented_array.h597 auto ST = Tail; in trim() local
598 SFH->Prev = ST; in trim()
599 ST->Next = Freelist; in trim()
600 ST->Prev = &SentinelSegment; in trim()
603 Freelist = ST; in trim()
/freebsd/contrib/llvm-project/llvm/lib/Linker/
H A DIRMover.cpp828 for (StructType *ST : Types) { in computeTypeMapping()
829 if (!ST->hasName()) in computeTypeMapping()
832 if (TypeMap.DstStructTypesSet.hasType(ST)) { in computeTypeMapping()
840 auto STTypePrefix = getTypeNamePrefix(ST->getName()); in computeTypeMapping()
841 if (STTypePrefix.size() == ST->getName().size()) in computeTypeMapping()
867 TypeMap.addTypeMapping(DST, ST); in computeTypeMapping()
942 auto &ST = *cast<StructType>(EltTy); in linkAppendingVarProto() local
943 Type *Tys[3] = {ST.getElementType(0), ST.getElementType(1), VoidPtrTy}; in linkAppendingVarProto()
1682 IRMover::StructTypeKeyInfo::KeyTy::KeyTy(const StructType *ST) in KeyTy() argument
1683 : ETypes(ST->elements()), IsPacked(ST->isPacked()) {} in KeyTy()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp367 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl(); in addIRPasses() local
368 addPass(createNVVMReflectPass(ST.getSmVersion())); in addIRPasses()
413 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl(); in addInstSelector() local
419 if (!ST.hasImageHandles()) in addInstSelector()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredication.cpp88 const ARMSubtarget *ST = nullptr; member in __anon60a30a010111::MVETailPredication
131 ST = &TM.getSubtarget<ARMSubtarget>(F); in runOnLoop()
138 if (!ST->hasMVEIntegerOps() || !ST->hasV8_1MMainlineOps()) { in runOnLoop()
H A DARMBlockPlacement.cpp216 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>(); in runOnMachineFunction() local
217 if (!ST.hasLOB()) in runOnMachineFunction()
221 TII = static_cast<const ARMBaseInstrInfo *>(ST.getInstrInfo()); in runOnMachineFunction()
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DStmtOpenMP.cpp354 Dir->setStrideVariable(Exprs.ST); in Create()
470 Dir->setStrideVariable(Exprs.ST); in Create()
617 Dir->setStrideVariable(Exprs.ST); in Create()
662 Dir->setStrideVariable(Exprs.ST); in Create()
994 Dir->setStrideVariable(Exprs.ST); in Create()
1098 Dir->setStrideVariable(Exprs.ST); in Create()
1143 Dir->setStrideVariable(Exprs.ST); in Create()
1186 Dir->setStrideVariable(Exprs.ST); in Create()
1231 Dir->setStrideVariable(Exprs.ST); in Create()
1276 Dir->setStrideVariable(Exprs.ST); in Create()
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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dste,mcde.txt1 ST-Ericsson Multi Channel Display Engine MCDE
3 The ST-Ericsson MCDE is a display controller with support for compositing
5 LCD displays or bridges. It is used in the ST-Ericsson U8500 platform.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCRegisterInfo.cpp129 ARCRegisterInfo::ARCRegisterInfo(const ARCSubtarget &ST) in ARCRegisterInfo() argument
130 : ARCGenRegisterInfo(ARC::BLINK), ST(ST) {} in ARCRegisterInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBoolRetToInt.cpp96 Type *IntTy = ST->isPPC64() ? Type::getInt64Ty(V->getContext()) in translate()
196 ST = TM.getSubtargetImpl(F); in runOnFunction()
278 const PPCSubtarget *ST; member in __anon23b91c850111::PPCBoolRetToInt
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp328 ST->isNeonAvailable()); in shouldMaximizeVectorBandwidth()
599 if (!ST->hasNEON()) { in getIntrinsicInstrCost()
683 if (ST->hasFullFP16() && in getIntrinsicInstrCost()
2074 if (ST->hasSVE()) in getRegisterBitWidth()
2593 if (ST->hasFullFP16()) in getCastInstrCost()
3003 (ST->hasFullFP16() && in getCmpSelInstrCost()
3058 if (ST->requiresStrictAlign()) { in enableMemCmpExpansion()
3075 return ST->hasSVE(); in prefersVectorizedAddressing()
3285 return ST->getMaxInterleaveFactor(); in getMaxInterleaveFactor()
3411 if (!ST) in getOrCreateResultFromMemIntrinsic()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonScheduleV60.td16 // | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
18 // | SLOT1 | LD ST ALU32 |
H A DHexagonCopyToCombine.cpp62 const HexagonSubtarget *ST; member in __anon9787e64c0111::HexagonCopyToCombine
461 ST = &MF.getSubtarget<HexagonSubtarget>(); in runOnMachineFunction()
462 TRI = ST->getRegisterInfo(); in runOnMachineFunction()
463 TII = ST->getInstrInfo(); in runOnMachineFunction()
473 if (!OptForSize && ST->isTinyCore()) in runOnMachineFunction()
588 assert(ST->useHVXOps()); in combine()
867 assert(ST->useHVXOps()); in emitCombineRR()
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Dst-keyscan.txt1 * ST Keyscan controller Device Tree bindings
3 The ST keyscan controller Device Tree binding is based on the
/freebsd/crypto/openssl/test/recipes/25-test_rusext_data/
H A Dgrfc.utf87 …treet=Дербеневская наб. д. 7 стр. 15, emailAddress=pki-grfc@grfc.ru, C=RU, ST=77 г. Москва, L=Моск…
11 …treet=Дербеневская наб. д. 7 стр. 15, emailAddress=pki-grfc@grfc.ru, C=RU, ST=77 г. Москва, L=Моск…
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp225 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
226 bool IsSlowLEA = ST.slowLEA(); in runOnMachineFunction()
227 bool IsSlow3OpsLEA = ST.slow3OpsLEA(); in runOnMachineFunction()
228 bool LEAUsesAG = ST.leaUsesAG(); in runOnMachineFunction()
230 bool OptIncDec = !ST.slowIncDec() || MF.getFunction().hasOptSize(); in runOnMachineFunction()
231 bool UseLEAForSP = ST.useLeaForSP(); in runOnMachineFunction()
233 TSM.init(&ST); in runOnMachineFunction()
234 TII = ST.getInstrInfo(); in runOnMachineFunction()
235 TRI = ST.getRegisterInfo(); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp433 if (!ISD::isNormalStore(ST)) in OptimizeFloatStore()
443 SDValue Chain = ST->getChain(); in OptimizeFloatStore()
444 SDValue Ptr = ST->getBasePtr(); in OptimizeFloatStore()
445 SDValue Value = ST->getValue(); in OptimizeFloatStore()
448 SDLoc dl(ST); in OptimizeFloatStore()
500 SDValue Chain = ST->getChain(); in LegalizeStoreOps()
501 SDValue Ptr = ST->getBasePtr(); in LegalizeStoreOps()
510 ReplaceNode(ST, OptStore); in LegalizeStoreOps()
555 EVT StVT = ST->getMemoryVT(); in LegalizeStoreOps()
1400 if (ST->isIndexed() || ST->isTruncatingStore() || in ExpandExtractFromVectorThroughStack()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64O0PreLegalizerCombiner.cpp165 const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>(); in runOnMachineFunction() local
171 /*CSEInfo*/ nullptr, RuleConfig, ST); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp323 const StoreSDNode *ST = cast<StoreSDNode>(N); in select() local
324 SDValue BasePtr = ST->getBasePtr(); in select()
339 SDValue Chain = ST->getChain(); in select()
340 EVT VT = ST->getValue().getValueType(); in select()
343 SDValue Ops[] = {BasePtr.getOperand(0), Offset, ST->getValue(), Chain}; in select()
349 CurDAG->setNodeMemRefs(cast<MachineSDNode>(ResNode), {ST->getMemOperand()}); in select()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DStripSymbols.cpp77 static void StripSymtab(ValueSymbolTable &ST, bool PreserveDbgInfo) { in StripSymtab() argument
78 for (ValueSymbolTable::iterator VI = ST.begin(), VE = ST.end(); VI != VE; ) { in StripSymtab()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h503 unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST);
1385 bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
1389 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
1395 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
1401 std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
1406 std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
1415 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);
1420 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);

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