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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dxgene-pci.txt6 - reg: A list of physical base address and length for each set of controller
7 registers. Must contain an entry for each entry in the reg-names
H A Dmediatek-pcie.txt16 - clocks: Must contain an entry for each entry in clock-names.
46 - resets: Must contain an entry for each entry in reset-names.
53 entry for each PCIe port
56 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
58 In addition, the device tree node must have sub-nodes describing each
H A Dnvidia,tegra20-pcie.txt14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
21 entry for each entry in the interrupt-names property.
35 PCI regions. The entries must be 6 cells each, where the first three cells
54 - clocks: Must contain an entry for each entry in clock-names.
61 - resets: Must contain an entry for each entry in reset-names.
77 - phys: Must contain an entry for each entry in phy-names.
81 These properties are deprecated in favour of per-lane PHYs define in each of
154 - phys: Must contain an phandle to a PHY for each entry in phy-names.
155 - phy-names: Must include an entry for each active lane. Note that the number
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dsgpio-aspeed.txt7 - Support interrupt option for each input port and various interrupt
9 - Support reset tolerance option for each output port
H A Dgpio-vf610.yaml15 each, and each PORT module has its own interrupt.
/freebsd/sys/contrib/device-tree/Bindings/display/panel/
H A Dsharp,lq101r1sx01.txt4 - left-right: each channel drives the left or right half of the screen
5 - even-odd: each channel drives the even or odd lines of the screen
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dlp87565.txt10 - xxx-in-supply: Phandle to parent supply node of each regulator
56 - xxx-in-supply: Phandle to parent supply node of each regulator
H A Dwm831x.txt34 - regulators : Contains sub-nodes for each of the regulators supplied by
51 The bindings details of each regulator can be found in:
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dnvidia,tegra186-timer.yaml45 One per each timer channels 0 through 9.
57 One per each timer channels 0 through 15.
/freebsd/sys/contrib/device-tree/Bindings/display/ti/
H A Dti,omap-dss.txt8 Binding details for each OMAP SoC version are described in respective binding
29 and the properties for the ports and endpoints for each encoder are
39 name for each display. If no aliases are defined, a semi-random number is used
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dfsl-edma.txt19 - interrupts : A list of interrupt-specifiers, one for each entry in
35 - clocks : A list of phandle and clock-specifier pairs, one for each entry in
96 in the dma.txt file, using a two-cell specifier for each channel: the 1st
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dhisilicon-hns-dsaf.txt27 attribute. If port node exists, phy-handle in each port node will be used.
43 - port-rst-offset: is offset of reset field for each port in dsaf. Its value
45 - port-mode-offset: is offset of port mode field for each port in dsaf. Its
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Drenesas,gyroadc.txt41 of each MB88101A connects to a shared input pin of
50 to the GyroADC, while MISO line of each TI/ADI ADC
59 to the GyroADC, while MISO line of each Maxim ADC
/freebsd/sys/contrib/device-tree/Bindings/leds/
H A Dleds-lm3532.txt7 method allows for different LED currents in each current sink thus allowing
11 each with 32 internal voltage setting resistors, 8-bit logarithmic and linear
65 - led-max-microamp : Defines the full scale current value for each control
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dfsl-sai.txt19 - clocks : Must contain an entry for each entry in clock-names.
34 - pinctrl-NNN : One property must exist for each entry in
55 - fsl,dataline : configure the dataline. it has 3 value for each configuration
H A Damlogic,axg-sound-card.yaml51 description: Width in bits for each slot
71 Transmit and receive cpu slot masks of each TDM lane
81 One subnode for each codec of the dai-link. dai-link representing
/freebsd/sys/dev/cxgbe/firmware/
H A Dt4fw_cfg.txt46 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
121 # TCAM has 8K cells; each region must start at a multiple of 128 cell.
122 # Each entry in these categories takes 4 cells each. nhash will use the
/freebsd/tools/build/options/
H A DWITHOUT_DEBUG_FILES1 Avoid building or installing standalone debug files for each
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dfsl-lpuart.txt19 - clocks : phandle + clock specifier pairs, one for each entry in clock-names
26 - dmas: A list of two dma specifiers, one for each entry in dma-names.
/freebsd/contrib/sendmail/contrib/
H A Detrn.021 name for which sendmail(1M) accepts email and, for each
23 If any client-hosts are specified, etrn uses each of these
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmedia5200.dts114 device-width = <2>; // Two devices on each bank
121 device-width = <2>; // Two devices on each bank
/freebsd/crypto/openssl/doc/man3/
H A DSCT_print.pod21 similar way. A separator can be specified to delimit each SCT in the output.
25 each SCT (if that log is in the CTLOG_STORE). Alternatively, NULL can be passed
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr-props.yaml11 range of legal values for each. This file defines the common parts that can be
12 reused for each type. Nodes using this schema should generally be nested under
/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dqcom,x1e80100-rpmh.yaml17 associated with each execution environment. Provider nodes must point to at
18 least one RPMh device child node pertaining to their RSC and each provider
/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Dfpga-region.txt44 * The size and specific location of each PRR is fixed.
45 * The connections at the edge of each PRR are fixed. The image that is loaded
47 * The busses within the FPGA are split such that each region gets its own
69 * An FPGA image may create a set of reprogrammable regions, each having its
101 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
150 For partial reconfiguration (PR), each PR region will have an FPGA Region.
158 a different FPGA Manager is used for each region.
300 bridges need to exist in the FPGA that can gate the buses going to each FPGA
303 PRR's with FPGA bridges. The device tree should have an FPGA region for each
318 each with its own requirements. The two parts are:

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