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Searched refs:delay (Results 101 – 125 of 2520) sorted by relevance

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/linux/Documentation/devicetree/bindings/mfd/
H A Dmxs-lradc.txt16 - fsl,ave-delay: delay between consecutive samples. Allowed value is
19 - fsl,settling: delay between plate switch to next sample. Allowed value is
31 fsl,ave-delay = <2>;
43 fsl,ave-delay = <2>;
/linux/arch/powerpc/platforms/cell/
H A Dcpufreq_spudemand.c49 int delay; in spu_gov_work() local
60 delay = usecs_to_jiffies(info->poll_int); in spu_gov_work()
61 schedule_delayed_work_on(info->policy->cpu, &info->work, delay); in spu_gov_work()
66 int delay = usecs_to_jiffies(info->poll_int); in spu_gov_init_work() local
68 schedule_delayed_work_on(info->policy->cpu, &info->work, delay); in spu_gov_init_work()
/linux/drivers/net/wireless/ath/ath9k/
H A Drng.c57 u32 delay; in ath9k_rng_delay_get() local
60 delay = 10; in ath9k_rng_delay_get()
62 delay = 1000; in ath9k_rng_delay_get()
64 delay = 10000; in ath9k_rng_delay_get()
66 return delay; in ath9k_rng_delay_get()
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml80 fsl,rx-frame-sync-delay-bits:
84 Receive frame sync delay in number of bits.
85 Indicates the delay between the Rx sync and the first bit of the Rx
86 frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
88 fsl,tx-frame-sync-delay-bits:
92 Transmit frame sync delay in number of bits.
93 Indicates the delay between the Tx sync and the first bit of the Tx
94 frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
/linux/Documentation/devicetree/bindings/spi/
H A Dspi-peripheral-props.yaml12 controller specific like delay in clock or data lines, etc. These properties
47 spi-cs-setup-delay-ns:
52 spi-cs-hold-delay-ns:
57 spi-cs-inactive-delay-ns:
70 spi-rx-delay-us:
74 rx-sample-delay-ns:
75 description: SPI Rx sample delay offset, unit is nanoseconds.
76 The delay from the default sample time before the actual
87 spi-tx-delay-us:
119 delay in nanoseconds inserted between two consecutive data frames.
H A Dspi-fsl-dspi.txt29 - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
31 - fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
60 fsl,spi-cs-sck-delay = <100>;
61 fsl,spi-sck-cs-delay = <50>;
/linux/arch/arm/boot/dts/gemini/
H A Dgemini-sl93512r.dts190 skew-delay = <5>;
194 skew-delay = <7>;
198 skew-delay = <8>;
202 skew-delay = <7>;
206 skew-delay = <10>;
210 skew-delay = <7>; /* 5 at another place? */
214 skew-delay = <15>;
218 skew-delay = <0>;
228 skew-delay = <7>;
234 skew-delay = <5>;
H A Dgemini-sq201.dts186 skew-delay = <0>;
190 skew-delay = <15>;
194 skew-delay = <7>;
198 skew-delay = <10>;
202 skew-delay = <7>;
206 skew-delay = <8>;
210 skew-delay = <7>;
214 skew-delay = <5>;
226 skew-delay = <7>;
/linux/Documentation/sound/designs/
H A Dtimestamping.rst11 estimate with a delay. In the latter two cases, the low-level driver
15 provides a refined estimate with a delay.
22 and delay, which combined with the trigger and current system
33 When timestamps are enabled, the avail/delay information is reported
53 |< codec delay >|<--hw delay-->|<queued samples>|<---avail->|
54 |<----------------- delay---------------------->| |
110 - including the delay in the audio timestamp may
148 1. DMA timestamp, no compensation for DMA+analog delay
159 2. DMA timestamp, compensation for DMA+analog delay
169 3. link timestamp, compensation for DMA+analog delay
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroidxu3-common.dtsi58 polling-delay-passive = <0>;
59 polling-delay = <0>;
141 polling-delay-passive = <0>;
142 polling-delay = <0>;
214 polling-delay-passive = <0>;
215 polling-delay = <0>;
287 polling-delay-passive = <0>;
288 polling-delay = <0>;
360 polling-delay-passive = <0>;
361 polling-delay = <0>;
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr3-timings.yaml52 Mode register set command delay in pico seconds.
57 Additional READ-to-READ delay in chip-to-chip cases in pico seconds.
72 RAS-to-CAS delay in pico seconds.
97 Internal READ to PRECHARGE command delay in pico seconds.
102 Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.
112 Internal WRITE-to-READ command delay in pico seconds.
117 Exit power-down to next valid command delay in pico seconds.
122 SELF REFRESH exit to next valid command delay in pico seconds.
/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574.dtsi753 polling-delay = <0>;
767 polling-delay = <0>;
781 polling-delay = <0>;
795 polling-delay = <0>;
809 polling-delay = <0>;
823 polling-delay = <0>;
837 polling-delay = <0>;
851 polling-delay = <0>;
881 polling-delay = <0>;
911 polling-delay = <0>;
[all …]
H A Dpm8010.dtsi12 polling-delay-passive = <100>;
13 polling-delay = <0>;
33 polling-delay-passive = <100>;
34 polling-delay = <0>;
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmicrochip,lan937x.yaml55 rx-internal-delay-ps:
58 tx-internal-delay-ps:
126 tx-internal-delay-ps = <2000>;
127 rx-internal-delay-ps = <2000>;
140 tx-internal-delay-ps = <2000>;
141 rx-internal-delay-ps = <2000>;
/linux/Documentation/devicetree/bindings/sound/
H A Drt5682.txt45 - realtek,btndet-delay
46 The debounce delay for push button.
47 The delay time is realtek,btndet-delay value multiple of 8.192 ms.
59 - realtek,dmic-delay-ms : Set the delay time (ms) for the requirement of
86 realtek,btndet-delay = <16>;
H A Ddmic-codec.yaml33 modeswitch-delay-ms:
36 wakeup-delay-ms:
52 wakeup-delay-ms = <50>;
53 modeswitch-delay-ms = <35>;
/linux/arch/arm64/boot/dts/sprd/
H A Dums512-1h10.dts45 sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x73 0x72 0x72>;
46 sprd,phy-delay-sd-uhs-sdr50 = <0x6e 0x7f 0x01 0x01>;
47 sprd,phy-delay-sd-highspeed = <0x7f 0x1a 0x9a 0x9a>;
48 sprd,phy-delay-legacy = <0x7f 0x1a 0x9a 0x9a>;
/linux/drivers/clk/sunxi/
H A Dclk-mod0.c177 u8 delay; in mmc_get_phase() local
180 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
182 if (!delay) in mmc_get_phase()
209 return delay * step; in mmc_get_phase()
219 u8 delay; in mmc_set_phase() local
261 delay = DIV_ROUND_CLOSEST(degrees, step); in mmc_set_phase()
263 delay = 0; in mmc_set_phase()
269 value |= delay << phase->offset; in mmc_set_phase()
/linux/drivers/staging/most/i2c/
H A Di2c.c42 unsigned int delay; member
72 unsigned int delay, pr; in configure_channel() local
101 delay = msecs_to_jiffies(MSEC_PER_SEC / polling_rate); in configure_channel()
102 dev->rx.delay = delay ? delay : 1; in configure_channel()
103 pr = MSEC_PER_SEC / jiffies_to_msecs(dev->rx.delay); in configure_channel()
245 schedule_delayed_work(&dev->rx.dwork, dev->rx.delay); in pending_rx_work()
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-starfive-visionfive-2-v1.3b.dts33 rx-internal-delay-ps = <1500>;
34 tx-internal-delay-ps = <1500>;
42 rx-internal-delay-ps = <300>;
43 tx-internal-delay-ps = <0>;
/linux/drivers/input/
H A Dinput-poller.c28 unsigned long delay; in input_dev_poller_queue_work() local
30 delay = msecs_to_jiffies(poller->poll_interval); in input_dev_poller_queue_work()
31 if (delay >= HZ) in input_dev_poller_queue_work()
32 delay = round_jiffies_relative(delay); in input_dev_poller_queue_work()
34 queue_delayed_work(system_freezable_wq, &poller->work, delay); in input_dev_poller_queue_work()
/linux/Documentation/devicetree/bindings/regulator/
H A Danatop-regulator.yaml45 anatop-delay-reg-offset:
49 anatop-delay-bit-shift:
53 anatop-delay-bit-width:
87 anatop-delay-reg-offset = <0x170>;
88 anatop-delay-bit-shift = <24>;
89 anatop-delay-bit-width = <2>;
/linux/arch/powerpc/include/asm/
H A Ddelay.h53 #define spin_event_timeout(condition, timeout, delay) \ argument
59 if (delay) { \
62 udelay(delay); \
/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c412 u32 delay; in periodic_compensation_handler() local
415 delay *= 1000; in periodic_compensation_handler()
416 delay = 2 + (delay / last->rate); in periodic_compensation_handler()
470 udelay(delay); in periodic_compensation_handler()
540 delay *= 1000; in tegra210_emc_r21021_periodic_compensation()
542 udelay(delay); in tegra210_emc_r21021_periodic_compensation()
1319 delay = 30; in tegra210_emc_r21021_set_clock()
1348 delay = value * delay + 20; in tegra210_emc_r21021_set_clock()
1350 delay = 0; in tegra210_emc_r21021_set_clock()
1456 delay); in tegra210_emc_r21021_set_clock()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dti,dp83822.yaml51 rx-internal-delay-ps:
54 Setting this property to a non-zero number sets the RX internal delay
55 for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
58 tx-internal-delay-ps:
61 Setting this property to a non-zero number sets the TX internal delay
62 for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
111 rx-internal-delay-ps = <1>;
112 tx-internal-delay-ps = <1>;

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