| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveDebugVariables.h | 45 LiveIntervals &LIS);
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| H A D | RegAllocBase.h | 67 LiveIntervals *LIS = nullptr; variable
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| H A D | LiveInterval.cpp | 1336 const MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def); in Classify()
1340 if (const VNInfo *PVNI = LR.getVNInfoBefore(LIS.getMBBEndIdx(Pred))) in Classify()
1370 SlotIndex Idx = LIS.getSlotIndexes()->getIndexBefore(*MI); in Distribute()
1373 SlotIndex Idx = LIS.getInstructionIndex(*MI); in Distribute()
1390 BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator(); in Distribute()
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| H A D | TargetInstrInfo.cpp | 562 LiveIntervals *LIS, in foldMemoryOperand() argument
609 NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, FI, LIS, VRM); in foldMemoryOperand()
655 LiveIntervals *LIS) const { in foldMemoryOperand()
679 NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, LoadMI, LIS); in foldMemoryOperand()
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| H A D | ScheduleDAGInstrs.cpp | 733 LiveIntervals *LIS, in buildSchedGraph() argument
827 SlotIndex SlotIdx = LIS->getInstructionIndex(MI); in buildSchedGraph()
828 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx); in buildSchedGraph()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 285 LiveIntervals &LIS) const { in shouldCoalesce()
290 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS); in shouldCoalesce()
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| H A D | AVRRegisterInfo.h | 60 LiveIntervals &LIS) const override;
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.h | 280 LiveIntervals *LIS = nullptr,
285 LiveIntervals *LIS = nullptr) const override;
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| H A D | SystemZRegisterInfo.h | 163 LiveIntervals &LIS) const override;
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| H A D | SystemZInstrInfo.cpp | 997 LiveIntervals *LIS, VirtRegMap *VRM) const { in foldMemoryOperandImpl() argument
1009 if (LIS) { in foldMemoryOperandImpl()
1010 MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot(); in foldMemoryOperandImpl()
1011 CCLiveRange = &LIS->getRegUnit(*CCUnit); in foldMemoryOperandImpl()
1027 CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator()); in foldMemoryOperandImpl()
1302 CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator()); in foldMemoryOperandImpl()
1329 LiveIntervals *LIS) const { in foldMemoryOperandImpl()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 61 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 250 LiveIntervals &LIS) const override;
300 LiveIntervals *LIS) const;
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| H A D | SIMachineScheduler.h | 446 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false); in initRPTracker()
452 LiveIntervals *getLIS() { return LIS; } in getLIS()
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| H A D | SIRegisterInfo.cpp | 2263 LiveIntervals &LIS) const { in shouldCoalesce()
2385 LiveIntervals *LIS) const { in findReachingDef()
2386 auto &MDT = LIS->getAnalysis<MachineDominatorTree>(); in findReachingDef()
2387 SlotIndex UseIdx = LIS->getInstructionIndex(Use); in findReachingDef()
2391 if (!LIS->hasInterval(Reg)) in findReachingDef()
2393 LiveInterval &LI = LIS->getInterval(Reg); in findReachingDef()
2414 LiveRange &LR = LIS->getRegUnit(*Units); in findReachingDef()
2417 MDT.dominates(LIS->getInstructionFromIndex(DefIdx), in findReachingDef()
2418 LIS->getInstructionFromIndex(V->def))) in findReachingDef()
2426 MachineInstr *Def = LIS->getInstructionFromIndex(DefIdx); in findReachingDef()
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| H A D | SIMachineScheduler.cpp | 292 const LiveIntervals *LIS) { in isDefBetween() argument
299 SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot(); in isDefBetween()
310 LiveIntervals *LIS = DAG->getLIS(); in initRegPressure() local
361 isDefBetween(Reg, LIS->getInstructionIndex(*BeginBlock).getRegSlot(), in initRegPressure()
362 LIS->getInstructionIndex(*EndBlock).getRegSlot(), MRI, in initRegPressure()
363 LIS)) { in initRegPressure()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | LiveRegMatrix.h | 42 LiveIntervals *LIS; variable
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| H A D | TargetInstrInfo.h | 1087 LiveIntervals *LIS = nullptr,
1094 LiveIntervals *LIS = nullptr) const;
1197 LiveIntervals *LIS = nullptr,
1210 LiveIntervals *LIS = nullptr) const {
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| H A D | MachinePipeliner.h | 115 LiveIntervals &LIS; variable
196 : ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), Loop(L), LIS(lis), in SwingSchedulerDAG()
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| H A D | ScheduleDAGInstrs.h | 318 LiveIntervals *LIS = nullptr,
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| H A D | LiveInterval.h | 993 LiveIntervals &LIS; variable
997 explicit ConnectedVNInfoEqClasses(LiveIntervals &lis) : LIS(lis) {} in ConnectedVNInfoEqClasses()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 136 LiveIntervals &LIS) const override;
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| H A D | AArch64InstrInfo.h | 188 LiveIntervals *LIS = nullptr,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 383 LiveIntervals *LIS = nullptr,
392 LiveIntervals *LIS = nullptr) const override;
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 211 LiveIntervals &LIS) const override;
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCPreEmitPeephole.cpp | 128 if (Opc != PPC::LI && Opc != PPC::LI8 && Opc != PPC::LIS && in removeRedundantLIs()
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