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Searched refs:MO (Results 101 – 125 of 497) sorted by relevance

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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/
H A DDbgEntityHistoryCalculator.cpp345 if (MO.isReg() && MO.getReg() && MO.getReg() != RegNo) in clobberRegEntries()
346 MaybeRemovedRegisters.insert(MO.getReg()); in clobberRegEntries()
349 if (MO.isReg() && MO.getReg()) in clobberRegEntries()
350 KeepRegisters.insert(MO.getReg()); in clobberRegEntries()
491 for (const MachineOperand &MO : MI.operands()) { in calculateDbgEntityHistory() local
492 if (MO.isReg() && MO.isDef() && MO.getReg()) { in calculateDbgEntityHistory()
495 if (MI.isCall() && MO.getReg() == SP) in calculateDbgEntityHistory()
499 if (Register::isVirtualRegister(MO.getReg())) in calculateDbgEntityHistory()
506 else if (MO.getReg() != FrameReg || in calculateDbgEntityHistory()
513 } else if (MO.isRegMask()) { in calculateDbgEntityHistory()
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H A DAsmPrinterInlineAsm.cpp518 if (!MO.isImm()) in emitInlineAsm()
520 unsigned Flags = MO.getImm(); in emitInlineAsm()
591 printOffset(MO.getOffset(), OS); in PrintSymbolOperand()
610 if (MO.isReg()) { in PrintAsmOperand()
616 if (MO.isImm()) { in PrintAsmOperand()
617 O << MO.getImm(); in PrintAsmOperand()
620 if (MO.isGlobal()) { in PrintAsmOperand()
621 PrintSymbolOperand(MO, O); in PrintAsmOperand()
626 if (!MO.isImm()) in PrintAsmOperand()
628 O << -MO.getImm(); in PrintAsmOperand()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp61 MachineOperand &MO, WebAssemblyFunctionInfo &MFI, in maybeRewriteToDrop() argument
67 MO.setReg(NewReg); in maybeRewriteToDrop()
68 MO.setIsDead(); in maybeRewriteToDrop()
91 for (auto &MO : MI.explicit_operands()) { in maybeRewriteToFallthrough() local
94 Register Reg = MO.getReg(); in maybeRewriteToFallthrough()
126 MO.setReg(NewReg); in maybeRewriteToFallthrough()
168 MachineOperand &MO = MI.getOperand(0); in runOnMachineFunction() local
169 Register OldReg = MO.getReg(); in runOnMachineFunction()
175 Changed |= maybeRewriteToDrop(OldReg, NewReg, MO, MFI, MRI); in runOnMachineFunction()
H A DWebAssemblyExplicitLocals.cpp187 Register Reg = MO.getReg(); in findStartOfTree()
341 if (!MO.isReg()) in runOnMachineFunction()
344 Register OldReg = MO.getReg(); in runOnMachineFunction()
349 if (MO.isDef()) { in runOnMachineFunction()
354 MI.untieRegOperand(MI.getOperandNo(&MO)); in runOnMachineFunction()
355 MO.ChangeToImmediate(LocalId); in runOnMachineFunction()
362 InsertPt = findStartOfTree(MO, MRI, MFI); in runOnMachineFunction()
372 MO.ChangeToImmediate(LocalId); in runOnMachineFunction()
384 MO.setReg(NewReg); in runOnMachineFunction()
421 (!MO.isReg() || MRI.use_empty(MO.getReg()) || in runOnMachineFunction()
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H A DWebAssemblyRegStackify.cpp141 if (MO.isGlobal()) { in queryCallee()
365 if (!MO.isReg() || MO.isUndef()) in isSafeToMove()
367 Register Reg = MO.getReg(); in isSafeToMove()
422 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) in isSafeToMove()
467 if (!MO.isReg()) in oneUseDominatesOtherUses()
469 Register DefReg = MO.getReg(); in oneUseDominatesOtherUses()
741 if (MO.isReg() && MO.getReg() == Reg) in isOnStack()
956 if (!MO.isReg()) in runOnMachineFunction()
958 Register Reg = MO.getReg(); in runOnMachineFunction()
964 if (!MO.isReg()) in runOnMachineFunction()
[all …]
H A DWebAssemblyDebugValueManager.cpp66 for (auto &MO : DBI->getDebugOperandsForReg(CurrentReg)) in updateReg() local
67 MO.setReg(Reg); in updateReg()
77 for (auto &MO : Clone->getDebugOperandsForReg(CurrentReg)) in clone() local
78 MO.setReg(NewReg); in clone()
88 for (auto &MO : DBI->getDebugOperandsForReg(CurrentReg)) in replaceWithLocal() local
89 MO.ChangeToTargetIndex(IndexType, LocalId); in replaceWithLocal()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/ExecutionEngine/Orc/
H A DIRCompileLayer.h34 IRCompiler(IRSymbolMapper::ManglingOptions MO) : MO(std::move(MO)) {} in IRCompiler() argument
37 return MO; in getManglingOptions()
42 IRSymbolMapper::ManglingOptions &manglingOptions() { return MO; } in manglingOptions()
45 IRSymbolMapper::ManglingOptions MO;
H A DLayer.h38 const IRSymbolMapper::ManglingOptions &MO,
70 IRLayer(ExecutionSession &ES, const IRSymbolMapper::ManglingOptions *&MO) in IRLayer() argument
71 : ES(ES), MO(MO) {} in IRLayer()
80 return MO; in getManglingOptions()
116 const IRSymbolMapper::ManglingOptions *&MO; variable
124 const IRSymbolMapper::ManglingOptions &MO,
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp85 const MachineOperand &MO = MI.getOperand(i); in clobbersCTR() local
86 if (MO.isReg()) { in clobbersCTR()
87 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8)) in clobbersCTR()
89 } else if (MO.isRegMask()) { in clobbersCTR()
90 if (MO.clobbersPhysReg(PPC::CTR) || MO.clobbersPhysReg(PPC::CTR8)) in clobbersCTR()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFAsmPrinter.cpp74 const MachineOperand &MO = MI->getOperand(OpNum); in printOperand() local
76 switch (MO.getType()) { in printOperand()
78 O << BPFInstPrinter::getRegisterName(MO.getReg()); in printOperand()
82 O << MO.getImm(); in printOperand()
86 O << *MO.getMBB()->getSymbol(); in printOperand()
90 O << *getSymbol(MO.getGlobal()); in printOperand()
94 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress()); in printOperand()
100 O << *GetExternalSymbolSymbol(MO.getSymbolName()); in printOperand()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp128 MachineOperand &MO = MI.getOperand(0); in getCallTargetRegOpnd() local
130 if (!MO.isReg() || !MO.isUse() || !Register::isVirtualRegister(MO.getReg())) in getCallTargetRegOpnd()
133 return &MO; in getCallTargetRegOpnd()
171 MachineOperand &MO = MI.getOperand(I); in eraseGPOpnd() local
172 if (MO.isReg() && MO.getReg() == Reg) { in eraseGPOpnd()
270 MachineOperand *MO = getCallTargetRegOpnd(MI); in isCallViaRegister() local
273 if (!MO) in isCallViaRegister()
277 Reg = MO->getReg(); in isCallViaRegister()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DImplicitNullChecks.cpp242 auto IsRegMask = [](const MachineOperand &MO) { return MO.isRegMask(); }; in canHandle() argument
736 for (auto &MO : MI->uses()) { in insertFaultingInstr() local
737 if (MO.isReg()) { in insertFaultingInstr()
738 MachineOperand NewMO = MO; in insertFaultingInstr()
739 if (MO.isUse()) { in insertFaultingInstr()
742 assert(MO.isDef() && "Expected def or use"); in insertFaultingInstr()
747 MIB.add(MO); in insertFaultingInstr()
784 if (!MO.isReg() || !MO.isDef()) in rewriteNullChecks()
786 Register Reg = MO.getReg(); in rewriteNullChecks()
793 for (auto &MO : DepMI->operands()) { in rewriteNullChecks() local
[all …]
H A DMachineLoopUtils.cpp50 for (MachineOperand &MO : NewMI->defs()) { in PeelSingleBlockLoop()
51 Register OrigR = MO.getReg(); in PeelSingleBlockLoop()
56 MO.setReg(R); in PeelSingleBlockLoop()
75 for (MachineOperand &MO : I->uses()) in PeelSingleBlockLoop()
76 if (MO.isReg() && Remaps.count(MO.getReg())) in PeelSingleBlockLoop()
77 MO.setReg(Remaps[MO.getReg()]); in PeelSingleBlockLoop()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonHazardRecognizer.cpp50 MachineOperand &MO = MI->getOperand(MI->getNumOperands() - 1); in getHazardType() local
51 if (!MO.isReg() || RegDefs.count(MO.getReg()) == 0) in getHazardType()
115 for (const MachineOperand &MO : MI->operands()) in EmitInstruction() local
116 if (MO.isReg() && MO.isDef() && !MO.isImplicit()) in EmitInstruction()
117 RegDefs.insert(MO.getReg()); in EmitInstruction()
H A DHexagonSubtarget.cpp309 const MachineOperand &MO = MI->getOperand(i); in apply() local
310 if (!MO.isReg()) in apply()
312 if (MO.isUse() && !MI->isCopy() && in apply()
313 VRegHoldingReg.count(MO.getReg())) { in apply()
316 } else if (MO.isDef() && Register::isPhysicalRegister(MO.getReg())) { in apply()
422 const MachineOperand &MO = DDst->getOperand(OpNum); in adjustSchedDependency() local
423 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { in adjustSchedDependency()
499 if (MO.isReg()) { in restoreLatency()
500 Register MOReg = MO.getReg(); in restoreLatency()
506 if (MO.isDef() && IsSameOrSubReg) in restoreLatency()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp204 const MachineOperand &MO = MI->getOperand(I); in delayHasHazard() local
207 if (!MO.isReg() || !(Reg = MO.getReg())) in delayHasHazard()
210 if (MO.isDef()) { in delayHasHazard()
215 if (MO.isUse()) { in delayHasHazard()
233 const MachineOperand &MO = MI->getOperand(I); in insertDefsUses() local
236 if (!MO.isReg() || !(Reg = MO.getReg())) in insertDefsUses()
239 if (MO.isDef()) in insertDefsUses()
241 else if (MO.isUse()) in insertDefsUses()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp175 const MachineOperand &MO = MI->getOperand(0); in LowerGETPCXAndEmitMCInsts() local
176 assert(MO.getReg() != SP::O7 && in LowerGETPCXAndEmitMCInsts()
179 MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); in LowerGETPCXAndEmitMCInsts()
293 const MachineOperand &MO = MI->getOperand (opNum); in printOperand() local
298 if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) { in printOperand()
349 switch (MO.getType()) { in printOperand()
355 O << MO.getImm(); in printOperand()
358 MO.getMBB()->getSymbol()->print(O, MAI); in printOperand()
361 PrintSymbolOperand(MO, O); in printOperand()
367 O << MO.getSymbolName(); in printOperand()
[all …]
H A DDelaySlotFiller.cpp253 if (!MO.isReg()) in delayHasHazard()
256 Register Reg = MO.getReg(); in delayHasHazard()
258 if (MO.isDef()) { in delayHasHazard()
263 if (MO.isUse()) { in delayHasHazard()
323 const MachineOperand &MO = MI->getOperand(i); in insertDefsUses() local
324 if (!MO.isReg()) in insertDefsUses()
327 Register Reg = MO.getReg(); in insertDefsUses()
330 if (MO.isDef()) in insertDefsUses()
332 if (MO.isUse()) { in insertDefsUses()
368 if (!MO.isImm()) in needsUnimp()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp215 return MI.getOperandNo(&MO) == 1 && in isCandidateStore()
308 } else if (isCandidateStore(MI, MO)) { in handleUse()
501 for (const MachineOperand &MO : MI.operands()) { in handleNormalInst() local
502 if (MO.isRegMask()) { in handleNormalInst()
503 const uint32_t *RegMask = MO.getRegMask(); in handleNormalInst()
510 if (!MO.isReg() || !MO.isDef()) in handleNormalInst()
512 int Idx = mapRegToGPRIndex(MO.getReg()); in handleNormalInst()
520 for (const MachineOperand &MO : MI.uses()) { in handleNormalInst() local
521 if (!MO.isReg() || !MO.readsReg()) in handleNormalInst()
523 int Idx = mapRegToGPRIndex(MO.getReg()); in handleNormalInst()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp87 for (auto &MO : MI->operands()) { in INITIALIZE_PASS() local
88 if (!MO.isReg()) in INITIALIZE_PASS()
90 Register Reg = MO.getReg(); in INITIALIZE_PASS()
93 if (MO.isUse()) in INITIALIZE_PASS()
114 for (MachineOperand &MO : MI->operands()) { in ClearKillFlags()
115 if (!MO.isReg() || MO.isDef() || !MO.isKill()) in ClearKillFlags()
117 if (!Uses.count(MO.getReg())) in ClearKillFlags()
119 MO.setIsKill(false); in ClearKillFlags()
H A DA15SDOptimizer.cpp134 if (!MO.isReg()) in usesRegClass()
136 Register Reg = MO.getReg(); in usesRegClass()
160 if (!MO) return ARM::ssub_0; in getPrefSPRLane()
190 for (MachineOperand &MO : MI->operands()) { in eraseInstrWithNoUses()
191 if ((!MO.isReg()) || (!MO.isUse())) in eraseInstrWithNoUses()
193 Register Reg = MO.getReg(); in eraseInstrWithNoUses()
401 for (MachineOperand &MO : MI->operands()) { in getReadDPRs()
402 if (!MO.isReg() || !MO.isUse()) in getReadDPRs()
404 if (!usesRegClass(MO, &ARM::DPRRegClass) && in getReadDPRs()
405 !usesRegClass(MO, &ARM::QPRRegClass) && in getReadDPRs()
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp386 const MachineOperand &MO) const { in addNodeIDMachineOperand()
387 if (MO.isReg()) { in addNodeIDMachineOperand()
388 Register Reg = MO.getReg(); in addNodeIDMachineOperand()
389 if (!MO.isDef()) in addNodeIDMachineOperand()
395 } else if (MO.isImm()) in addNodeIDMachineOperand()
396 ID.AddInteger(MO.getImm()); in addNodeIDMachineOperand()
397 else if (MO.isCImm()) in addNodeIDMachineOperand()
398 ID.AddPointer(MO.getCImm()); in addNodeIDMachineOperand()
399 else if (MO.isFPImm()) in addNodeIDMachineOperand()
400 ID.AddPointer(MO.getFPImm()); in addNodeIDMachineOperand()
[all …]
/netbsd/share/misc/
H A Dzipcodes28131 63379:Troy, MO
28258 63674:Tiff, MO
28264 63733:Arab, MO
28294 63771:Oran, MO
28367 63940:Fisk, MO
28374 63950:Lodi, MO
28379 63955:Oxly, MO
28391 64001:Alma, MO
28411 64048:Holt, MO
28590 64480:Rea, MO
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp27 static const TargetRegisterClass *getRC32(MachineOperand &MO, in getRC32() argument
33 MO.getSubReg() == SystemZ::subreg_l32 || in getRC32()
34 MO.getSubReg() == SystemZ::subreg_hl32) in getRC32()
37 MO.getSubReg() == SystemZ::subreg_h32 || in getRC32()
38 MO.getSubReg() == SystemZ::subreg_hh32) in getRC32()
41 if (VRM && VRM->hasPhys(MO.getReg())) { in getRC32()
42 Register PhysReg = VRM->getPhys(MO.getReg()); in getRC32()
109 Register Reg = MO->getReg(); in getRegAllocationHints()
114 if (MO->getSubReg()) in getRegAllocationHints()
428 for (const MachineOperand &MO : MII->operands()) in shouldCoalesce() local
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrBuilder.h65 void getFullAddress(SmallVectorImpl<MachineOperand> &MO) { in getFullAddress()
69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, in getFullAddress()
73 MO.push_back(MachineOperand::CreateFI(Base.FrameIndex)); in getFullAddress()
76 MO.push_back(MachineOperand::CreateImm(Scale)); in getFullAddress()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
81 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags)); in getFullAddress()
83 MO.push_back(MachineOperand::CreateImm(Disp)); in getFullAddress()
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false, in getFullAddress()

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