/openbsd/gnu/llvm/llvm/include/llvm/Support/ |
H A D | MachineValueType.h | 58 f64 = 13, // This is a 64 bit floating point value enumerator 717 case nxv8f64: return f64; in getVectorElementType() 984 case f64 : in getSizeInBits() 1232 return MVT::f64; in getFloatingPointVT() 1398 case MVT::f64: in getVectorVT() 1484 case MVT::f64: in getScalableVectorVT()
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsCallLowering.cpp | 174 VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 && in assignCustomValue() 266 VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 && in assignCustomValue()
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H A D | MipsISelLowering.cpp | 322 setTruncStoreAction(MVT::f64, MVT::f16, Expand); in MipsTargetLowering() 324 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in MipsTargetLowering() 2490 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); in lowerFABS64() 2942 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { in CC_MipsO32() 3299 (ValVT == MVT::f64 && LocVT == MVT::i64) || in LowerCall() 3300 (ValVT == MVT::i64 && LocVT == MVT::f64)) in LowerCall() 3302 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { in LowerCall() 3696 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments() 3697 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments() 3700 ValVT == MVT::f64) { in LowerFormalArguments() [all …]
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H A D | MipsSEISelDAGToDAG.cpp | 771 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { in trySelect() 776 CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero)); in trySelect() 781 MVT::f64, Zero, Zero)); in trySelect() 786 MVT::f64, Zero, Zero)); in trySelect() 961 assert((ResTy == MVT::f64 || ResTy == MVT::f32) && in trySelect() 964 if (ResTy == MVT::f64) in trySelect()
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H A D | MipsSEISelLowering.cpp | 216 setOperationAction(ISD::LOAD, MVT::f64, Custom); in MipsSETargetLowering() 217 setOperationAction(ISD::STORE, MVT::f64, Custom); in MipsSETargetLowering() 249 setOperationAction(ISD::SETCC, MVT::f64, Legal); in MipsSETargetLowering() 250 setOperationAction(ISD::SELECT, MVT::f64, Custom); in MipsSETargetLowering() 261 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in MipsSETargetLowering() 262 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand); in MipsSETargetLowering() 263 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in MipsSETargetLowering() 264 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in MipsSETargetLowering() 1170 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) in lowerLOAD() 1232 if (Src == MVT::i64 && Dest == MVT::f64) { in lowerBITCAST() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/VE/ |
H A D | VECallingConv.td | 43 CCIfType<[i64, f64], 91 CCIfType<[i64, f64],
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H A D | VVPInstrPatternsVec.td | 389 f64, v256f64, "VFADDD", 392 f64, v256f64, "VFMULD", 395 f64, v256f64, "VFSUBD", 398 f64, v256f64, "VFDIVD", 534 f64, v256f64, "VFMADD", f32, v256f32, "VFMADS">;
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/openbsd/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86InstrFPStack.td | 59 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 70 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 182 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 224 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 226 (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 506 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 800 // Required for RET of f32 / f64 / f80 values. 808 // Required for CALL which return f32 / f64 / f80 values. 819 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 820 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; [all …]
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H A D | X86InstrFMA.td | 380 defm : scalar_fma_patterns<any_fma, "VFMADD", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; 381 defm : scalar_fma_patterns<X86any_Fmsub, "VFMSUB", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; 382 defm : scalar_fma_patterns<X86any_Fnmadd, "VFNMADD", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; 383 defm : scalar_fma_patterns<X86any_Fnmsub, "VFNMSUB", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; 570 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, any_fma, loadf64, 573 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86any_Fmsub, loadf64, 576 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64, 579 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64,
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H A D | X86FastISel.cpp | 150 return (VT == MVT::f64 && Subtarget->hasSSE2()) || in isScalarFPTypeInSSEReg() 299 if (VT == MVT::f64 && !Subtarget->hasSSE2()) in isTypeLegal() 355 case MVT::f64: in X86FastEmitLoad() 522 case MVT::f64: in X86FastEmitStore() 1368 case MVT::f64: in X86ChooseCmpOpcode() 2257 case MVT::f64: Opc = &OpcTable[1][0]; break; in X86FastEmitSSESelect() 2286 case MVT::f64: in X86FastEmitPseudoSelect() 3083 case MVT::f64: in fastLowerArguments() 3742 case MVT::f64: in X86MaterializeFP() 3850 case MVT::f64: in fastMaterializeConstant() [all …]
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H A D | X86InstrVecCompiler.td | 19 // A vector extract of the first f32/f64 position is a subregister copy 24 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))), 29 // A vector extract of the first f32/f64 position is a subregister copy 34 def : Pat<(f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonOperands.td | 12 def f64Imm : Operand<f64> { let ParserMatchClass = f64ImmOperand; }
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H A D | HexagonISelLowering.cpp | 1602 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in HexagonTargetLowering() 1755 setOperationAction(ISD::FMA, MVT::f64, Expand); in HexagonTargetLowering() 1756 setOperationAction(ISD::FADD, MVT::f64, Expand); in HexagonTargetLowering() 1757 setOperationAction(ISD::FSUB, MVT::f64, Expand); in HexagonTargetLowering() 1758 setOperationAction(ISD::FMUL, MVT::f64, Expand); in HexagonTargetLowering() 1786 setTruncStoreAction(MVT::f64, MVT::f16, Expand); in HexagonTargetLowering() 1805 setOperationAction(ISD::FADD, MVT::f64, Legal); in HexagonTargetLowering() 1806 setOperationAction(ISD::FSUB, MVT::f64, Legal); in HexagonTargetLowering() 1809 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in HexagonTargetLowering() 1810 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in HexagonTargetLowering() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 392 if (VT == MVT::f64) return 0; in ARMMoveToFPReg() 416 bool is64bit = VT == MVT::f64; in ARMMaterializeFP() 821 case MVT::f64: in ARMSimplifyAddress() 969 case MVT::f64: in ARMEmitLoad() 1112 case MVT::f64: in ARMEmitStore() 1373 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) in ARMEmitCmp() 1388 case MVT::f64: in ARMEmitCmp() 1903 if (VA.getLocVT() != MVT::f64 || in ProcessCallArgs() 1920 case MVT::f64: in ProcessCallArgs() 1985 assert(VA.getLocVT() == MVT::f64 && in ProcessCallArgs() [all …]
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H A D | ARMISelLowering.cpp | 169 if (ElemTy != MVT::f64) in addTypeForNEON() 219 addTypeForNEON(VT, MVT::f64); in addDRTypeForNEON() 5391 if (VT == MVT::f64) in isUnsupportedFloatingType() 6024 if (VT == MVT::f64) in LowerFCOPYSIGN() 6032 if (VT == MVT::f64) in LowerFCOPYSIGN() 6064 if (SrcVT == MVT::f64) in LowerFCOPYSIGN() 7088 case MVT::f64: { in LowerConstantFP() 13747 case MVT::f64: in shouldConvertFpToSat() 18961 return MVT::f64; in getOptimalMemOpType() 19253 case MVT::f64: in isFMAFasterThanFMulAndFAdd() [all …]
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H A D | ARMInstrNEON.td | 2461 // Use vld1/vst1 for unaligned f64 load / store 2463 def : Pat<(f64 (hword_alignedload addrmode6:$addr)), 2467 def : Pat<(f64 (byte_alignedload addrmode6:$addr)), 7504 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>; 7532 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>; 7533 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>; 7534 def : Pat<(f64 (bitconvert (v4f16 DPR:$src))), (f64 DPR:$src)>; 7535 def : Pat<(f64 (bitconvert (v4bf16 DPR:$src))), (f64 DPR:$src)>; 7536 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>; 7537 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>; [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrHFP.td | 179 // Extending multiplication (f32 x f32 -> f64). 187 // Extending multiplication (f64 x f64 -> f128).
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | SISchedule.td | 41 // Slow quarter rate f64 instruction. 44 // half rate f64 instruction (same as v_add_f64) 47 // Conversion to or from f64 instruction
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H A D | SIInstrInfo.td | 315 !eq(SrcVT.Value, f64.Value), 866 def InlineImmFP64 : FPImmLeaf<f64, [{ 1772 !eq(SrcVT.Value, f64.Value), 2670 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>; 2672 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>; 2673 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>; 2685 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>; 2686 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>; 2701 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>; 2724 def VOP_V4F64_F64_F64_V4F64 : VOPProfile <[v4f64, f64, f64, v4f64]>; [all …]
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H A D | VOPCInstructions.td | 1075 defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>; 1076 defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>; 1077 defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>; 1078 defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>; 1079 defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>; 1080 defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>; 1089 defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>; 1090 defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>; 1091 defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>; 1092 defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>; [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyInstrInfo.td | 168 def f64imm_op : FPOperand<f64>; 278 defm "": ARGUMENT<F64, f64>; 381 "f64.const\t$res, $imm", "f64.const\t$imm", 0x44>;
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 331 case MVT::f64: in getImplicitScaleFactor() 393 if (VT != MVT::f32 && VT != MVT::f64) in materializeFP() 397 bool Is64Bit = (VT == MVT::f64); in materializeFP() 565 if (VT != MVT::f32 && VT != MVT::f64) in fastMaterializeFloatZero() 568 bool Is64Bit = (VT == MVT::f64); in fastMaterializeFloatZero() 1489 case MVT::f64: in emitCmp() 1861 case MVT::f64: in emitLoad() 2700 case MVT::f64: in selectSelect() 2841 if (SrcVT == MVT::f64) { in selectFPToInt() 3606 case MVT::f64: in fastLowerIntrinsicCall() [all …]
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/openbsd/gnu/llvm/llvm/include/llvm/IR/ |
H A D | IntrinsicsVEVL.gen.td | 85 …l_lvsd_svs : ClangBuiltin<"__builtin_ve_vl_lvsd_svs">, Intrinsic<[LLVMType<f64>], [LLVMType<v256f6… 91 …tin<"__builtin_ve_vl_vbrdd_vsl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<f64>, LLVMType<i32>], [… 92 …in<"__builtin_ve_vl_vbrdd_vsvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<f64>, LLVMType<v256f64>… 93 …n<"__builtin_ve_vl_vbrdd_vsmvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<f64>, LLVMType<v256i1>,… 531 …n<"__builtin_ve_vl_vfaddd_vsvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<f64>, LLVMType<v256f64>… 549 …n<"__builtin_ve_vl_vfsubd_vsvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<f64>, LLVMType<v256f64>… 567 …n<"__builtin_ve_vl_vfmuld_vsvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<f64>, LLVMType<v256f64>… 585 …n<"__builtin_ve_vl_vfdivd_vsvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<f64>, LLVMType<v256f64>… 601 …n<"__builtin_ve_vl_vfcmpd_vsvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<f64>, LLVMType<v256f64>… 619 …n<"__builtin_ve_vl_vfmaxd_vsvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<f64>, LLVMType<v256f64>… [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/Sparc/ |
H A D | SparcInstr64Bit.td | 346 [(set f64:$rd, 347 (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>; 413 [(set f64:$rd, (SPselectreg f64:$rs2, f64:$f, imm:$rcond, i64:$rs1))]>;
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/openbsd/gnu/llvm/llvm/lib/Target/CSKY/ |
H A D | CSKYRegisterInfo.td | 196 def FPR64 : RegisterClass<"CSKY", [f64], 32, 198 def sFPR64 : RegisterClass<"CSKY", [f64], 32,
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