/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/MCTargetDesc/ |
H A D | LoongArchMCCodeEmitter.cpp | 87 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 3675 MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 || in processInstruction() 3676 MRI->getEncodingValue(Inst.getOperand(1).getReg()) < 8) in processInstruction() 3704 MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 || in processInstruction() 3705 MRI->getEncodingValue(Inst.getOperand(2).getReg()) < 8) in processInstruction() 3866 unsigned Src2Enc = MRI->getEncodingValue(Src2); in validateInstruction() 3883 unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction() 3884 unsigned Index = MRI->getEncodingValue( in validateInstruction() 3890 unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction() 3891 unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction() 3892 unsigned Index = MRI->getEncodingValue( in validateInstruction() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 4500 EReg = MRI->getEncodingValue(Reg); in parseRegisterList() 4518 EReg = MRI->getEncodingValue(Reg); in parseRegisterList() 4547 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) in parseRegisterList() 4553 EReg = MRI->getEncodingValue(Reg); in parseRegisterList() 4589 EReg = MRI->getEncodingValue(Reg); in parseRegisterList() 4606 MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { in parseRegisterList() 4617 EReg = MRI->getEncodingValue(Reg); in parseRegisterList() 4623 EReg = MRI->getEncodingValue(++Reg); in parseRegisterList() 7453 unsigned Rt = MRI->getEncodingValue(Reg1); in ParseInstruction() 7454 unsigned Rt2 = MRI->getEncodingValue(Reg2); in ParseInstruction() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | SIRegisterInfo.h | 169 return getEncodingValue(Reg) & 0xff; in getHWRegIndex()
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H A D | SIInsertWaitcnts.cpp | 503 unsigned Reg = TRI->getEncodingValue(AMDGPU::getMCReg(Op.getReg(), *ST)); in getRegInterval() 656 TRI->getEncodingValue(AMDGPU::getMCReg(DefMO.getReg(), *ST)), in updateByEvent() 1794 Encoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0); in runOnMachineFunction() 1796 Encoding.SGPR0 = TRI->getEncodingValue(AMDGPU::SGPR0); in runOnMachineFunction()
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H A D | R600InstrInfo.cpp | 327 int Index = RI.getEncodingValue(Reg) & 0xff; in ExtractSrcs() 419 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(R600::OQAP))) { in isLegalUpTo() 599 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff; in fitsConstReadLimitations()
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/openbsd/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMELFStreamer.cpp | 1299 UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg)); in FlushUnwindOpcodes() 1390 UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg)); in emitMovSP() 1412 Reg = MRI.getEncodingValue(Reg); in collectHWRegs()
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H A D | ARMInstPrinter.cpp | 811 return MRI.getEncodingValue(LHS.getReg()) < in printRegisterList() 812 MRI.getEncodingValue(RHS.getReg()); in printRegisterList()
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/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/ |
H A D | SystemZAsmPrinter.cpp | 990 unsigned V = TRI->getEncodingValue((Register)I); in emitPPA1() 997 unsigned I = TRI->getEncodingValue(Reg); in emitPPA1() 1020 uint8_t FrameReg = TRI->getEncodingValue(TRI->getFrameRegister(*MF)); in emitPPA1()
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/openbsd/gnu/llvm/llvm/lib/Target/Xtensa/MCTargetDesc/ |
H A D | XtensaMCCodeEmitter.cpp | 149 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVMCCodeEmitter.cpp | 231 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
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/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 176 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
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/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 986 .addImm(getEncodingValue(SrcReg) * 4) in lowerCRSpilling() 1028 unsigned ShiftBits = getEncodingValue(DestReg)*4; in lowerCRRestore() 1145 .addImm(getEncodingValue(SrcReg)) in lowerCRBitSpilling() 1190 unsigned ShiftBits = getEncodingValue(DestReg); in lowerCRBitRestore()
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H A D | PPCFrameLowering.cpp | 2166 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; in processFunctionBeforeFrameFinalized() 2226 std::min<unsigned>(TRI->getEncodingValue(MinGPR), in processFunctionBeforeFrameFinalized() 2227 TRI->getEncodingValue(MinG8R)); in processFunctionBeforeFrameFinalized()
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/openbsd/gnu/llvm/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 553 uint16_t getEncodingValue(MCRegister RegNo) const { in getEncodingValue() function
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 1123 FrameReg = RegInfo->getEncodingValue(StackReg); in emitFrame() 1125 ReturnReg = RegInfo->getEncodingValue(ReturnReg_); in emitFrame()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64A57FPLoadBalancing.cpp | 714 if ((TRI->getEncodingValue(Reg) % 2) == 0) in getColor()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 1706 RI->getEncodingValue(getReg())); in addGPR32as64Operands() 1718 RI->getEncodingValue(getReg())); in addGPR64as32Operands() 2078 .getRegister(RI->getEncodingValue(getReg())); in addSyspXzrPairOperand() 4415 if (RI->getEncodingValue(Reg) <= (RI->getEncodingValue(PrevReg))) in tryParseMatrixTileList() 4433 RegMask |= 0x1 << (RI->getEncodingValue(Reg) - in tryParseMatrixTileList() 4434 RI->getEncodingValue(AArch64::ZAD0)); in tryParseMatrixTileList() 4537 unsigned RegVal = getContext().getRegisterInfo()->getEncodingValue(Reg); in tryParseVectorList() 4539 getContext().getRegisterInfo()->getEncodingValue(PrevReg); in tryParseVectorList() 7735 unsigned FirstEncoding = RI->getEncodingValue(FirstReg); in tryParseGPRSeqPair() 7759 if (RI->getEncodingValue(SecondReg) != FirstEncoding + 1 || in tryParseGPRSeqPair()
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/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCInstPrinter.cpp | 647 RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg)); in printOperand()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 213 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; in getX86RegNum() 218 return Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(OpNum).getReg()); in getX86RegEncoding()
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/openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 1571 return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first); in emitPushInst() 1668 return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS); in emitPopInst()
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H A D | ARMBaseRegisterInfo.cpp | 380 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) in getRegAllocationHints()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 81 return getEncodingValue(i); in getSEHRegNum()
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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 474 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); in getSingleInstruction()
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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCCodeEmitter.cpp | 782 return MCT.getRegisterInfo()->getEncodingValue(Reg); in getMachineOpValue()
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