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/qemu/docs/devel/
H A Dqapi-code-gen.rst569 - It does not access guest RAM that may block when userfaultfd is
575 The restrictions on locking limit access to shared state. Such access
H A Dtesting.rst754 access, so they SHOULD NOT be exposed to external interfaces if you are
879 * Have access to a library of guest OS images (by means of the
/qemu/tcg/riscv/
H A Dtcg-target.c.inc1274 * alignment bits within the address. For unaligned access, we
1276 * byte of the access.
/qemu/tcg/ppc/
H A Dtcg-target.c.inc2453 * Before 3.0, "An access that is not atomic is performed as a set of
2457 * As of 3.0, "the non-atomic access is performed as described in
2544 * If the access is unaligned, we need to make sure we fail if we
2545 * cross a page boundary. The trick is to add the access size-1
/qemu/target/arm/tcg/
H A Da64.decode326 # so we ignore hints about data access patterns, and handle these like
/qemu/tests/qtest/
H A Dlibqtest.c964 if (!access("/dev/kvm", R_OK | W_OK)) { in qtest_has_accel()
/qemu/tcg/s390x/
H A Dtcg-target.c.inc1882 * alignment bits within the address. For unaligned access, we
1884 * byte of the access.
3460 * interlocked-access-1, and load/store-on-condition-1
/qemu/target/hexagon/idef-parser/
H A DREADME.rst38 not access any global variable, because all the accessed data structures will be
/qemu/tcg/i386/
H A Dtcg-target.c.inc2151 * If the required alignment is at least as large as the access,
2153 * check that we don't cross pages for the complete access.
2980 access to the high-byte registers. */
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc1796 * the alignment bits within the address. For unaligned access,
1798 * last byte of the access.
/qemu/linux-user/
H A Dstrace.list13 { TARGET_NR_access, "access" , NULL, print_access, NULL },
/qemu/hw/net/
H A Dtrace-events258 e1000e_wrn_io_addr_flash(uint64_t addr) "IO flash access (0x%"PRIx64") not implemented"
/qemu/qga/
H A Dqapi-schema.json273 # file access, the number of bytes to read is limited to 48 MB.
/qemu/
H A Dhmp-commands.hx571 .help = "print expression value (use $reg for CPU register access)",
H A DMAINTAINERS2912 F: block/snapshot-access.c
/qemu/tcg/mips/
H A Dtcg-target.c.inc1272 * For unaligned accesses, compare against the end of the access to
/qemu/tests/data/qobject/
H A Dqdict.txt247 access.c: 10521
/qemu/target/i386/tcg/
H A Ddecode-new.c.inc1851 case X86_SIZE_y_d64: /* Full (not 16-bit) register access */
2776 * Write back flags after last memory access. Some older ALU instructions, as
/qemu/tests/tcg/i386/
H A Dx86.csv128 # address size prefix byte to access the instruction.
135 # operand size prefix byte to access the instruction.

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