| /qemu/hw/block/ |
| H A D | nand.c | 258 if (!s->blk_load(s, s->addr, offset)) { in nand_load_block()
280 s->ioaddr = s->io; in nand_command()
299 s->iolen = nand_load_block(s, s->addr & ((1 << s->addr_shift) - 1)); in nand_command()
307 s->ioaddr = s->io; in nand_command()
331 s->ioaddr = s->io; in nand_command()
345 s->ioaddr_vmstate = s->ioaddr - s->io; in nand_pre_save()
357 s->ioaddr = s->io + s->ioaddr_vmstate; in nand_post_load()
433 (s->pages << s->page_shift) + (s->pages << s->oob_shift)) { in nand_realize()
445 s->ioaddr = s->io; in nand_realize()
603 s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] = in nand_setio()
[all …]
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| /qemu/hw/char/ |
| H A D | serial.c | 139 s->iir = tmp_iir | (s->iir & 0xF0); in serial_update_irq()
175 speed = (s->divider == 0) ? 3500 : (float) s->baudbase / s->divider; in serial_update_parameters()
200 s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; in serial_update_msl()
201 s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; in serial_update_msl()
202 s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; in serial_update_msl()
203 s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; in serial_update_msl()
207 s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); in serial_update_msl()
246 s->tsr = s->thr; in serial_xmit()
257 serial_receive1(s, &s->tsr, 1); in serial_xmit()
634 s->fcr_vmstate = s->fcr; in serial_pre_save()
[all …]
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| H A D | escc.c | 202 return s->bit_swap ? s->it_shift + 1 : s->it_shift; in reg_shift()
207 return s->bit_swap ? s->it_shift : s->it_shift + 1; in chn_shift()
286 s->rx = s->tx = 0; in escc_reset_chn()
287 s->rxint = s->txint = 0; in escc_reset_chn()
289 s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0; in escc_reset_chn()
580 s->wregs[s->reg] = val; in escc_mem_write()
589 s->wregs[s->reg] = val; in escc_mem_write()
592 s->wregs[s->reg] = val; in escc_mem_write()
607 s->wregs[s->reg] = val; in escc_mem_write()
691 trace_escc_mem_readb_ctrl(CHN_C(s), s->reg, s->rregs[s->reg]); in escc_mem_read()
[all …]
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| H A D | sh_serial.c | 88 s->rx_cnt = 0; in OBJECT_DEFINE_TYPE()
114 if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) { in sh_serial_write()
268 ret = s->rx_fifo[s->rx_tail++]; in sh_serial_read()
273 if (s->rx_cnt < s->rtrg) { in sh_serial_read()
344 if (s->scr & (1 << 6) && s->rxi) { in sh_serial_timeout_int()
357 s->rx_fifo[s->rx_head++] = buf[i]; in sh_serial_receive1()
362 if (s->rx_cnt >= s->rtrg) { in sh_serial_receive1()
364 if (s->scr & (1 << 6) && s->rxi) { in sh_serial_receive1()
398 s->rtrg = 1; in sh_serial_reset()
400 s->smr = 0; in sh_serial_reset()
[all …]
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| H A D | pl011.c | 128 flags = s->int_level & s->int_enabled; in pl011_update()
166 c = s->read_fifo[s->read_pos]; in pl011_read()
169 s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1); in pl011_read()
174 if (s->read_count == s->read_trigger - 1) in pl011_read()
213 r = s->int_level & s->int_enabled; in pl011_read()
240 s->read_trigger = (s->ifl >> 1) & 0x1c; in pl011_set_read_trigger()
432 r = s->read_count < pl011_get_fifo_depth(s); in pl011_can_receive()
453 if (s->read_count == s->read_trigger) { in pl011_put_fifo()
523 if (!pl011_is_fifo_enabled(s) && s->read_count > 0 && s->read_pos > 0) { in pl011_post_load()
530 s->read_fifo[0] = s->read_fifo[s->read_pos]; in pl011_post_load()
[all …]
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| /qemu/hw/misc/ |
| H A D | cbus.c | 61 if (s->slave[s->addr]) in cbus_io()
62 s->slave[s->addr]->io(s->slave[s->addr]->opaque, in cbus_io()
63 s->rw, s->reg, &s->val); in cbus_io()
78 s->dir = !s->rw; in cbus_cycle()
103 s->val |= s->dat << (s->bit --); in cbus_clk()
105 qemu_set_irq(s->dat_out, (s->val >> (s->bit --)) & 1); in cbus_clk()
179 qemu_set_irq(s->irq, s->irqst & ~s->irqen); in retu_interrupt_update()
265 return (s->channel << 10) | s->result[s->channel]; in retu_read()
412 s->cbus.opaque = s; in retu_init()
485 qemu_set_irq(s->irq, s->irqst & ~s->irqen); in tahvo_interrupt_update()
[all …]
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| /qemu/hw/core/ |
| H A D | ptimer.c | 48 s->callback(s->callback_opaque); in ptimer_trigger()
83 delta = s->delta = s->limit; in ptimer_reload()
147 s->last_event = s->next_event; in ptimer_reload()
152 timer_mod(s->timer, s->next_event); in ptimer_reload()
189 s->delta = s->limit; in ptimer_tick()
205 if (s->enabled && s->delta != 0) { in ptimer_get_count()
333 s->delta = ptimer_get_count(s); in ptimer_stop()
343 s->delta = ptimer_get_count(s); in ptimer_set_period()
365 s->delta = ptimer_get_count(s); in ptimer_set_period_from_clock()
388 s->delta = ptimer_get_count(s); in ptimer_set_freq()
[all …]
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| /qemu/hw/ide/ |
| H A D | atapi.c | 59 return !s->tray_open && s->nb_sectors > 0; in media_present()
142 cd_data_to_raw(s->io_buffer, s->lba); in cd_read_sector_cb()
161 buf = (s->cd_sector_size == 2352) ? s->io_buffer + 16 : s->io_buffer; in cd_read_sector()
169 ide_buffered_readv(s, (int64_t)s->lba << 2, &s->qiov, 4, in cd_read_sector()
213 bcl = s->lcyl | (s->hcyl << 8); in atapi_byte_count_limit()
230 if (s->lba != -1 && s->io_buffer_index >= s->cd_sector_size) { in ide_atapi_cmd_reply_end()
407 s->bus->dma->aiocb = ide_buffered_readv(s, (int64_t)s->lba << 2, in ide_atapi_cmd_read_dma_cb()
433 block_acct_start(blk_get_stats(s->blk), &s->acct, s->packet_transfer_size, in ide_atapi_cmd_read_dma()
460 s->unit = s->bus->retry_unit; in ide_atapi_dma_restart()
1318 trace_ide_atapi_cmd_packet(s, s->lcyl | (s->hcyl << 8), ppacket); in ide_atapi_cmd()
[all …]
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| /qemu/hw/rtc/ |
| H A D | mc146818rtc.c | 91 guest_clock - s->last_update + s->offset; in get_guest_rtc_ns()
232 periodic_timer_update(s, s->next_periodic_time, s->period, false); in rtc_periodic_timer()
448 s->cmos_data[s->cmos_index] = data; in cmos_ioport_write()
462 s->cmos_data[s->cmos_index] = data; in cmos_ioport_write()
589 rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year + in rtc_get_time()
696 ret = s->cmos_data[s->cmos_index]; in cmos_ioport_read()
699 ret = s->cmos_data[s->cmos_index]; in cmos_ioport_read()
705 ret = s->cmos_data[s->cmos_index]; in cmos_ioport_read()
726 ret = s->cmos_data[s->cmos_index]; in cmos_ioport_read()
780 s->period = rtc_periodic_clock_ticks(s); in rtc_post_load()
[all …]
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| H A D | twl92230.c | 79 qemu_set_irq(s->out[3], s->status & ~s->mask); in menelaus_update()
85 timer_mod(s->rtc.hz_tm, s->rtc.next); in menelaus_rtc_start()
98 qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset); in menelaus_rtc_update()
104 s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset; in menelaus_alm_update()
114 timer_mod(s->rtc.hz_tm, s->rtc.next); in menelaus_rtc_hz()
117 if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec) in menelaus_rtc_hz()
141 s->reg = 0x00; in menelaus_reset()
318 return s->inputs | (~s->dir & s->outputs); in menelaus_read()
723 menelaus_write(s, s->reg ++, data); in menelaus_tx()
732 return menelaus_read(s, s->reg ++); in menelaus_rx()
[all …]
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| /qemu/hw/arm/ |
| H A D | pxa2xx.c | 637 return s->sssr | s->ssitr; in pxa2xx_ssp_read()
771 s->sscr[0] = s->sscr[1] = 0; in pxa2xx_ssp_reset()
779 s->rx_start = s->rx_level = 0; in pxa2xx_ssp_reset()
1528 s->slave->host = s; in pxa2xx_i2c_init()
1750 if (s->enable && s->tx_len) in pxa2xx_i2s_data_req()
1752 if (s->enable && s->rx_len) in pxa2xx_i2s_data_req()
1757 s->tx_len = tx - s->fifo_len; in pxa2xx_i2s_data_req()
1761 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) in pxa2xx_i2s_data_req()
1985 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); in pxa2xx_fir_rx()
2134 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); in pxa270_init()
[all …]
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| H A D | strongarm.c | 111 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); in strongarm_pic_update()
112 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); in strongarm_pic_update()
135 return s->pending & ~s->is_fiq & s->enabled; in strongarm_pic_mem_read()
143 return s->pending & s->is_fiq & s->enabled; in strongarm_pic_mem_read()
523 s->ilevel & ~s->dir; in strongarm_gpio_set()
537 level = s->olevel & s->dir; in strongarm_gpio_handler_update()
754 level = s->olevel & s->dir; in strongarm_ppc_handler_update()
1071 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; in strongarm_uart_rx_push()
1126 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); in strongarm_uart_tx()
1221 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; in strongarm_uart_write()
[all …]
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| /qemu/hw/net/ |
| H A D | pcnet.c | 635 (s->csr[8] | s->csr[9] | s->csr[10] | s->csr[11]) != 0) { in ladr_match()
776 trace_pcnet_init(s, PHYSADDR(s, CSR_IADR(s))); in pcnet_init()
780 s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)), in pcnet_init()
796 s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)), in pcnet_init()
827 s->rdra = PHYSADDR(s, rdra); in pcnet_init()
828 s->tdra = PHYSADDR(s, tdra); in pcnet_init()
834 s->rdra, CSR_RCVRL(s), s->tdra, CSR_XMTRL(s)); in pcnet_init()
927 PHYSADDR(s,CSR_CRDA(s)), CSR_CRST(s), CSR_RCVRC(s), in pcnet_rdte_poll()
994 if (CSR_DRX(s) || CSR_STOP(s) || CSR_SPND(s) || !size || in pcnet_receive()
1297 if (CSR_TDMD(s) || (CSR_TXON(s) && !CSR_DPOLL(s) && pcnet_tdte_poll(s))) { in pcnet_poll()
[all …]
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| H A D | tulip.c | 108 uint32_t ie = s->csr[5] & s->csr[7]; in tulip_update_int()
155 s->current_rx_desc = s->csr[3]; in tulip_next_rx_descriptor()
566 tulip_receive(s, s->tx_frame, s->tx_frame_len); in tulip_tx()
626 s->filter[n][3], s->filter[n][2], s->filter[n][1], s->filter[n][0]); in tulip_setup_filter_addr()
657 s->current_tx_desc = s->csr[4]; in tulip_next_tx_descriptor()
774 s->current_rx_desc = s->csr[3]; in tulip_write()
780 s->current_tx_desc = s->csr[4]; in tulip_write()
826 s->old_csr9 = s->csr[9]; in tulip_write()
973 memory_region_init_io(&s->io, OBJECT(&s->dev), &tulip_ops, s, in pci_tulip_realize()
976 memory_region_init_io(&s->memory, OBJECT(&s->dev), &tulip_ops, s, in pci_tulip_realize()
[all …]
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| H A D | smc91c111.c | 131 level = (s->int_level & s->int_mask) != 0; in smc91c111_update()
174 s->tx_alloc = smc91c111_allocate_packet(s); in smc91c111_tx_alloc()
189 s->rx_fifo[i] = s->rx_fifo[i + 1]; in smc91c111_pop_rx_fifo()
207 s->tx_fifo_done[i] = s->tx_fifo_done[i + 1]; in smc91c111_pop_tx_fifo_done()
284 s->tx_fifo[s->tx_fifo_len++] = packet; in smc91c111_queue_tx()
420 smc91c111_queue_tx(s, s->packet_num); in smc91c111_writeb()
454 s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x7ff); in smc91c111_writeb()
602 s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x07ff); in smc91c111_readb()
706 s->rx_fifo[s->rx_fifo_len++] = packetnum; in smc91c111_receive()
780 memory_region_init_io(&s->mmio, OBJECT(s), &smc91c111_mem_ops, s, in smc91c111_realize()
[all …]
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| /qemu/hw/gpio/ |
| H A D | omap_gpio.c | 65 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) & in omap_gpio_set()
84 return s->inputs & s->pins; in omap_gpio_read()
129 diff = (s->outputs ^ value) & ~s->dir; in omap_gpio_write()
139 diff = s->outputs & (s->dir ^ value); in omap_gpio_write()
142 value = s->outputs & ~s->dir; in omap_gpio_write()
231 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]); in omap2_gpio_module_int_update()
261 s->ints[line] |= s->dir & in omap2_gpio_module_level_update()
262 ((s->inputs & s->level[1]) | (~s->inputs & s->level[0])); in omap2_gpio_module_level_update()
282 if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) in omap2_gpio_set()
286 if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) in omap2_gpio_set()
[all …]
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| H A D | pl061.c | 129 floating = ~(s->pur | s->pdr); in pl061_floating()
166 trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data, in pl061_update()
175 out = (s->data & s->dir) | pullups | (s->old_out_data & floating); in pl061_update()
190 changed = (s->old_in_data ^ s->data) & ~s->dir; in pl061_update()
192 s->old_in_data = s->data; in pl061_update()
206 s->istate |= ~(s->data ^ s->iev) & mask; in pl061_update()
214 s->istate |= ~(s->data ^ s->iev) & s->isense; in pl061_update()
217 s->istate, s->im, (s->istate & s->im) != 0); in pl061_update()
219 qemu_set_irq(s->irq, (s->istate & s->im) != 0); in pl061_update()
251 r = s->istate & s->im; in pl061_read()
[all …]
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| /qemu/hw/display/ |
| H A D | ati.c | 54 s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN)); in ati_vga_switch_mode()
148 if ((s->regs.cur_offset & BIT(31)) || s->cursor_guest_mode) { in ati_cursor_define()
163 cursor_set_mono(s->cursor, s->regs.cur_color1, s->regs.cur_color0, in ati_cursor_define()
165 dpy_cursor_define(s->vga.con, s->cursor); in ati_cursor_define()
180 s->cursor_offset != s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - in ati_cursor_invalidate()
186 s->cursor_offset = s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - in ati_cursor_invalidate()
255 pci_set_irq(&s->dev, !!(s->regs.gen_int_status & s->regs.gen_int_cntl)); in ati_vga_update_irq()
646 s->regs.gpio_dvi_ddc = ati_i2c(&s->bbi2c, in ati_mm_write()
660 s->regs.gpio_monid = ati_i2c(&s->bbi2c, s->regs.gpio_monid, 1); in ati_mm_write()
1008 memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s, in ati_vga_realize()
[all …]
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| H A D | xlnx_dp.c | 354 s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i]) in xlnx_dp_audio_mix_buffer()
357 s->byte_left = s->audio_data_available[0]; in xlnx_dp_audio_mix_buffer()
359 memset(s->temp_buffer, 0, s->audio_data_available[1] / 2); in xlnx_dp_audio_mix_buffer()
366 s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i]) in xlnx_dp_audio_mix_buffer()
369 s->byte_left = s->audio_data_available[1]; in xlnx_dp_audio_mix_buffer()
405 &s->out_buffer[s->data_ptr], s->byte_left); in xlnx_dp_audio_callback()
803 xlnx_dp_aux_set_command(s, s->core_registers[offset]); in xlnx_dp_write()
1311 qdev_realize(DEVICE(s->dpcd), BUS(s->aux_bus), &error_fatal); in xlnx_dp_realize()
1327 s->amixer_output_stream = AUD_open_out(&s->aud_card, in xlnx_dp_realize()
1345 memset(s->core_registers, 0, sizeof(s->core_registers)); in xlnx_dp_reset()
[all …]
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| /qemu/hw/net/can/ |
| H A D | ctucan_core.c | 187 s->status.s.txnf = txnf; in ctucan_update_txnf()
204 s->status.s.idle = 1; in ctucan_hardware_reset()
272 s->status.s.idle = 0; in ctucan_send_ready_buffers()
273 s->status.s.txs = 1; in ctucan_send_ready_buffers()
275 s->status.s.idle = 1; in ctucan_send_ready_buffers()
276 s->status.s.txs = 0; in ctucan_send_ready_buffers()
456 s->rx_pointers.s.rx_rpp = s->rx_tail_pos; in ctucan_mem_read()
552 s->status.s.dor = 1; in ctucan_receive()
559 s->status.s.idle = 0; in ctucan_receive()
560 s->status.s.rxs = 1; in ctucan_receive()
[all …]
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| /qemu/hw/sensor/ |
| H A D | tmp105.c | 32 qemu_set_irq(s->pin, s->alarm ^ ((~s->config >> 2) & 1)); /* POL */ in tmp105_interrupt_update()
128 s->buf[s->len ++] = (((uint16_t) s->temperature) >> 8); in tmp105_read()
129 s->buf[s->len ++] = (((uint16_t) s->temperature) >> 0) & in tmp105_read()
134 s->buf[s->len ++] = s->config; in tmp105_read()
138 s->buf[s->len ++] = ((uint16_t) s->limit[0]) >> 8; in tmp105_read()
139 s->buf[s->len ++] = ((uint16_t) s->limit[0]) >> 0; in tmp105_read()
143 s->buf[s->len ++] = ((uint16_t) s->limit[1]) >> 8; in tmp105_read()
144 s->buf[s->len ++] = ((uint16_t) s->limit[1]) >> 0; in tmp105_read()
158 s->config = s->buf[0]; in tmp105_write()
178 return s->buf[s->len ++]; in tmp105_rx()
[all …]
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| /qemu/hw/sd/ |
| H A D | pl181.c | 139 qemu_set_irq(s->irq[i], (s->status & s->mask[i]) != 0); in pl181_update()
151 n = (s->fifo_pos + s->fifo_len) & (PL181_FIFO_LEN - 1); in pl181_fifo_push()
152 s->fifo_len++; in pl181_fifo_push()
165 value = s->fifo[s->fifo_pos]; in pl181_fifo_pop()
166 s->fifo_len--; in pl181_fifo_pop()
167 s->fifo_pos = (s->fifo_pos + 1) & (PL181_FIFO_LEN - 1); in pl181_fifo_pop()
191 s->response[1] = s->response[2] = s->response[3] = 0; in pl181_do_command()
226 while (s->datacnt && s->fifo_len < PL181_FIFO_LEN) { in pl181_fifo_run()
260 if (s->datacnt == 0 && s->fifo_len == 0) { in pl181_fifo_run()
417 s->datacnt = s->datalength; in pl181_write()
[all …]
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| H A D | pxa2xx_mmci.c | 75 return s->tx_start < ARRAY_SIZE(s->tx_fifo) in pxa2xx_mmci_vmstate_validate()
76 && s->rx_start < ARRAY_SIZE(s->rx_fifo) in pxa2xx_mmci_vmstate_validate()
77 && s->tx_len <= ARRAY_SIZE(s->tx_fifo) in pxa2xx_mmci_vmstate_validate()
78 && s->rx_len <= ARRAY_SIZE(s->rx_fifo) in pxa2xx_mmci_vmstate_validate()
186 while (s->bytesleft && s->tx_len) { in pxa2xx_mmci_fifo_update()
187 sdbus_write_byte(&s->sdbus, s->tx_fifo[s->tx_start++]); in pxa2xx_mmci_fifo_update()
196 s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] = in pxa2xx_mmci_fifo_update()
266 s->bytesleft = s->numblk * s->blklen; in pxa2xx_mmci_wakequeues()
330 ret = (s->resp_len < 9) ? s->resp_fifo[s->resp_len++] : 0; in pxa2xx_mmci_read()
454 s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] = in pxa2xx_mmci_write()
[all …]
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| H A D | bcm2835_sdhost.c | 134 s->rsp[1] = s->rsp[2] = s->rsp[3] = 0; in bcm2835_sdhost_send_command()
176 value = s->fifo[s->fifo_pos]; in bcm2835_sdhost_fifo_pop()
239 if (s->hbct && s->datacnt % s->hbct == 0 && in bcm2835_sdhost_fifo_run()
254 s->edm |= ((s->fifo_len & 0x1f) << 4); in bcm2835_sdhost_fifo_run()
363 s->datacnt = s->hblc * s->hbct; in bcm2835_sdhost_write()
406 qbus_init(&s->sdbus, sizeof(s->sdbus), in bcm2835_sdhost_init()
411 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); in bcm2835_sdhost_init()
412 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); in bcm2835_sdhost_init()
419 s->cmd = 0; in bcm2835_sdhost_reset()
424 s->hbct = 0; in bcm2835_sdhost_reset()
[all …]
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| /qemu/hw/timer/ |
| H A D | imx_gpt.c | 145 s->freq = imx_ccm_get_clock_frequency(s->ccm, in imx_gpt_set_freq()
151 ptimer_set_freq(s->timer, s->freq); in imx_gpt_set_freq()
157 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { in imx_gpt_update_int()
166 s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer); in imx_gpt_update_count()
205 count = s->cnt = s->next_timeout = 0; in imx_gpt_compute_next_timeout()
208 count = s->cnt = s->next_timeout = 0; in imx_gpt_compute_next_timeout()
249 s->sr |= s->next_int; in imx_gpt_compute_next_timeout()
363 if (s->freq && (s->cr & GPT_CR_EN)) { in imx_gpt_reset_common()
490 s->sr |= s->next_int; in imx_gpt_timeout()
497 if (s->freq && (s->cr & GPT_CR_EN)) { in imx_gpt_timeout()
[all …]
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