/qemu/hw/nvram/ |
H A D | ds1225y.c | 45 uint32_t val; in nvram_read() local 47 val = s->contents[addr]; in nvram_read() 48 trace_nvram_read(addr, val); in nvram_read() 49 return val; in nvram_read() 52 static void nvram_write(void *opaque, hwaddr addr, uint64_t val, in nvram_write() argument 57 val &= 0xff; in nvram_write() 58 trace_nvram_write(addr, s->contents[addr], val); in nvram_write() 60 s->contents[addr] = val; in nvram_write() 63 fputc(val, s->file); in nvram_write()
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/qemu/tests/qtest/libqos/ |
H A D | pci.c | 273 uint16_t val; in qpci_msix_enable() local 304 uint16_t val; in qpci_msix_disable() local 339 uint16_t val; in qpci_msix_masked() local 406 uint8_t val; in qpci_io_readb() local 408 bus->memread(dev->bus, token.addr + off, &val, sizeof(val)); in qpci_io_readb() 409 return val; in qpci_io_readb() 420 uint16_t val; in qpci_io_readw() local 422 bus->memread(bus, token.addr + off, &val, sizeof(val)); in qpci_io_readw() 434 uint32_t val; in qpci_io_readl() local 436 bus->memread(dev->bus, token.addr + off, &val, sizeof(val)); in qpci_io_readl() [all …]
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/qemu/hw/input/ |
H A D | pl050.c | 84 uint8_t val; in pl050_read() local 87 val = s->last; in pl050_read() 88 val = val ^ (val >> 4); in pl050_read() 89 val = val ^ (val >> 2); in pl050_read() 90 val = (val ^ (val >> 1)) & 1; in pl050_read() 93 if (val) { in pl050_read()
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/qemu/tests/tcg/hexagon/ |
H A D | v68_scalar.c | 117 static inline void storew_rl_at(int *p, int val) in storew_rl_at() argument 120 : : "r"(p), "r"(val) : "memory"); in storew_rl_at() 131 static inline void stored_rl_at(long long *p, long long val) in stored_rl_at() argument 134 : : "r"(p), "r"(val) : "memory"); in stored_rl_at() 145 static inline void storew_rl_st(int *p, int val) in storew_rl_st() argument 148 : : "r"(p), "r"(val) : "memory"); in storew_rl_st() 159 static inline void stored_rl_st(long long *p, long long val) in stored_rl_st() argument 162 : : "r"(p), "r"(val) : "memory"); in stored_rl_st()
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/qemu/hw/ide/ |
H A D | ahci-allwinner.c | 52 uint64_t val = a->regs[addr / 4]; in allwinner_ahci_mem_read() local 56 val |= 0x2 << 28; in allwinner_ahci_mem_read() 59 val &= ~(0x1 << 24); in allwinner_ahci_mem_read() 62 trace_allwinner_ahci_mem_read(s, a, addr, val, size); in allwinner_ahci_mem_read() 63 return val; in allwinner_ahci_mem_read() 67 uint64_t val, unsigned size) in allwinner_ahci_mem_write() argument 72 trace_allwinner_ahci_mem_write(s, a, addr, val, size); in allwinner_ahci_mem_write() 73 a->regs[addr / 4] = val; in allwinner_ahci_mem_write()
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/qemu/monitor/ |
H A D | hmp.c | 427 int64_t val, val2; in expr_prod() local 441 val *= val2; in expr_prod() 456 return val; in expr_prod() 461 int64_t val, val2; in expr_logic() local 475 val &= val2; in expr_logic() 478 val |= val2; in expr_logic() 481 val ^= val2; in expr_logic() 485 return val; in expr_logic() 490 int64_t val, val2; in expr_sum() local 502 val += val2; in expr_sum() [all …]
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H A D | hmp-cmds.c | 328 hwaddr val = qdict_get_int(qdict, "val"); in hmp_print() local 345 monitor_printc(mon, val); in hmp_print() 364 sum += val; in hmp_sum() 374 uint32_t val; in hmp_ioport_read() local 387 val = cpu_inb(addr); in hmp_ioport_read() 391 val = cpu_inw(addr); in hmp_ioport_read() 395 val = cpu_inl(addr); in hmp_ioport_read() 407 int val = qdict_get_int(qdict, "val"); in hmp_ioport_write() local 414 cpu_outb(addr, val); in hmp_ioport_write() 417 cpu_outw(addr, val); in hmp_ioport_write() [all …]
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/qemu/linux-user/arm/nwfpe/ |
H A D | fpa11_cpdt.c | 110 float32 val; in storeSingle() local 111 register unsigned int *p = (unsigned int*)&val; in storeSingle() 116 val = float64_to_float32(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status); in storeSingle() 123 default: val = fpa11->fpreg[Fn].fSingle; in storeSingle() 134 float64 val; in storeDouble() local 135 register unsigned int *p = (unsigned int*)&val; in storeDouble() 140 val = float32_to_float64(fpa11->fpreg[Fn].fSingle, &fpa11->fp_status); in storeDouble() 147 default: val = fpa11->fpreg[Fn].fDouble; in storeDouble() 163 floatx80 val; in storeExtended() local 164 register unsigned int *p = (unsigned int*)&val; in storeExtended() [all …]
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/qemu/hw/net/ |
H A D | trace-events | 20 lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" 25 mipsnet_read(uint64_t addr, uint32_t val) "read addr=0x%" PRIx64 " val=0x%x" 26 mipsnet_write(uint64_t addr, uint64_t val) "write addr=0x%" PRIx64 " val=0x%" PRIx64 30 ne2000_read(uint64_t addr, uint64_t val) "read addr=0x%" PRIx64 " val=0x%" PRIx64 31 ne2000_write(uint64_t addr, uint64_t val) "write addr=0x%" PRIx64 " val=0x%" PRIx64 32 ne2000_ioport_read(uint64_t addr, uint64_t val) "io read addr=0x%02" PRIx64 " val=0x%02" PRIx64 33 ne2000_ioport_write(uint64_t addr, uint64_t val) "io write addr=0x%02" PRIx64 " val=0x%02" PRIx64 58 pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x" 59 pcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x" 422 lasi_82596_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64" val=0x%04x" [all …]
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H A D | opencores_eth.c | 313 uint32_t val) in open_eth_int_source_write() argument 317 s->regs[INT_SOURCE] = val; in open_eth_int_source_write() 587 s->regs[MODER] = val; 603 s->regs[INT_SOURCE] &= ~val; 612 s->regs[INT_MASK] = val; 619 if (val < 0x80) { 622 s->regs[TX_BD_NUM] = val; 634 if (val & MIICOMMAND_WCTRLDATA) { 640 if (val & MIICOMMAND_RSTAT) { 678 reg_write[idx](s, val); [all …]
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/qemu/hw/usb/ |
H A D | hcd-ohci.c | 109 #define OHCI_BM(val, field) \ argument 1302 val &= OHCI_FMI_FI; in ohci_set_frame_interval() 1304 if (val != ohci->fi) { in ohci_set_frame_interval() 1308 ohci->fi = val; in ohci_set_frame_interval() 1328 ohci->ctl = val; in ohci_set_ctl() 1441 if (val == 0) { in ohci_port_set_if_connected() 1665 val = (val & ~OHCI_STATUS_SOC); in ohci_mem_write() 1681 ohci->intr |= val; in ohci_mem_write() 1686 ohci->intr &= ~val; in ohci_mem_write() 1756 ohci->hmask = val; in ohci_mem_write() [all …]
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/qemu/hw/pci-host/ |
H A D | pnv_phb4_pec.c | 49 pec->nest_regs[reg] = val & PPC_BITMASK(0, 25); in pnv_pec_nest_xscom_write() 52 pec->nest_regs[reg] = val & PPC_BITMASK(0, 11); in pnv_pec_nest_xscom_write() 55 pec->nest_regs[reg] = val & PPC_BITMASK(0, 16); in pnv_pec_nest_xscom_write() 58 pec->nest_regs[reg] = val & PPC_BITMASK(0, 37); in pnv_pec_nest_xscom_write() 61 pec->nest_regs[reg] = val & PPC_BITMASK(0, 6); in pnv_pec_nest_xscom_write() 64 pec->nest_regs[reg] = val & PPC_BITMASK(0, 15); in pnv_pec_nest_xscom_write() 67 pec->nest_regs[reg] = val & PPC_BITMASK(0, 48); in pnv_pec_nest_xscom_write() 71 pec->nest_regs[reg] = val & PPC_BITMASK(0, 24); in pnv_pec_nest_xscom_write() 78 pec->nest_regs[reg] = val; in pnv_pec_nest_xscom_write() 82 addr, val); in pnv_pec_nest_xscom_write() [all …]
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H A D | pnv_phb3_pbcq.c | 137 pbcq->nest_regs[reg] = val & 0xffffffffc0000000ull; in pnv_pbcq_nest_xscom_write() 143 pbcq->nest_regs[reg] = val & 0xfffffffffc000000ull; in pnv_pbcq_nest_xscom_write() 152 pbcq->nest_regs[reg] = val & PBCQ_NEST_IRSN_COMP; in pnv_pbcq_nest_xscom_write() 156 pbcq->nest_regs[reg] = val & PBCQ_NEST_LSI_SRC; in pnv_pbcq_nest_xscom_write() 161 addr, val); in pnv_pbcq_nest_xscom_write() 173 pbcq->pci_regs[reg] = val & 0xfffffffffc000000ull; in pnv_pbcq_pci_xscom_write() 178 addr, val); in pnv_pbcq_pci_xscom_write() 190 pbcq->spci_regs[reg] = val & 0xfff; in pnv_pbcq_spci_xscom_write() 193 pbcq->spci_regs[reg] &= ~val; in pnv_pbcq_spci_xscom_write() 197 val, 8); in pnv_pbcq_spci_xscom_write() [all …]
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/qemu/hw/intc/ |
H A D | slavio_intctl.c | 117 trace_slavio_intctl_mem_writel(s->cpu, addr, val); in slavio_intctl_mem_writel() 120 val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN; in slavio_intctl_mem_writel() 121 s->intreg_pending &= ~val; in slavio_intctl_mem_writel() 126 val &= CPU_SOFTIRQ_MASK; in slavio_intctl_mem_writel() 127 s->intreg_pending |= val; in slavio_intctl_mem_writel() 180 trace_slavio_intctlm_mem_writel(addr, val); in slavio_intctlm_mem_writel() 184 val &= MASTER_IRQ_MASK; in slavio_intctlm_mem_writel() 185 s->intregm_disabled &= ~val; in slavio_intctlm_mem_writel() 191 val &= MASTER_IRQ_MASK; in slavio_intctlm_mem_writel() 192 s->intregm_disabled |= val; in slavio_intctlm_mem_writel() [all …]
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H A D | bcm2836_control.c | 223 s->local_timer_control = val; in bcm2836_control_local_timer_control() 224 if (val & LOCALTIMER_ENABLE) { in bcm2836_control_local_timer_control() 235 if (val & LOCALTIMER_INTFLAG) { in bcm2836_control_local_timer_ack() 238 if ((val & LOCALTIMER_RELOAD) && in bcm2836_control_local_timer_ack() 281 s->route_gpu_irq = val & 0x3; in bcm2836_control_write() 282 s->route_gpu_fiq = (val >> 2) & 0x3; in bcm2836_control_write() 284 s->route_localtimer = val & 7; in bcm2836_control_write() 286 bcm2836_control_local_timer_control(s, val); in bcm2836_control_write() 288 bcm2836_control_local_timer_ack(s, val); in bcm2836_control_write() 294 s->mailboxes[(offset - REG_MBOX0_WR) >> 2] |= val; in bcm2836_control_write() [all …]
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H A D | ioapic.c | 300 uint32_t val = 0; in ioapic_mem_read() local 306 val = s->ioregsel; in ioapic_mem_read() 315 val = s->id << IOAPIC_ID_SHIFT; in ioapic_mem_read() 318 val = s->version | in ioapic_mem_read() 325 val = s->ioredtbl[index] >> 32; in ioapic_mem_read() 334 trace_ioapic_mem_read(addr, s->ioregsel, size, val); in ioapic_mem_read() 336 return val; in ioapic_mem_read() 368 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, in ioapic_mem_write() argument 379 s->ioregsel = val; in ioapic_mem_write() 401 s->ioredtbl[index] |= val; in ioapic_mem_write() [all …]
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/qemu/hw/misc/ |
H A D | allwinner-sid.c | 49 uint64_t val = 0; in allwinner_sid_read() local 53 val = s->control; in allwinner_sid_read() 56 val = s->rdkey; in allwinner_sid_read() 64 trace_allwinner_sid_read(offset, val, size); in allwinner_sid_read() 66 return val; in allwinner_sid_read() 70 uint64_t val, unsigned size) in allwinner_sid_write() argument 74 trace_allwinner_sid_write(offset, val, size); in allwinner_sid_write() 78 s->control = val; in allwinner_sid_write()
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/qemu/scripts/ |
H A D | minikconf.py | 120 self.value = val 279 def do_assignment(self, var, val): argument 283 val = self.value_mangler(val) 431 val = self.val 440 val = self.val 466 val = self.parse_expr() 471 val = self.parse_var() 474 return val 562 val = self.val 564 self.do_include(val) [all …]
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/qemu/hw/remote/ |
H A D | message.c | 100 if ((conf->addr + sizeof(conf->val)) > pci_config_size(dev)) { in process_config_write() 105 pci_default_write_config(dev, conf->addr, conf->val, conf->len); in process_config_write() 124 if ((conf->addr + sizeof(conf->val)) > pci_config_size(dev)) { in process_config_read() 149 uint64_t val; in process_bar_write() local 157 val = cpu_to_le64(bar_access->val); in process_bar_write() 160 (void *)&val, bar_access->size, true); in process_bar_write() 185 uint64_t val = 0; in process_bar_read() local 191 val = UINT64_MAX; in process_bar_read() 196 (void *)&val, bar_access->size, false); in process_bar_read() 201 val = UINT64_MAX; in process_bar_read() [all …]
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/qemu/hw/timer/ |
H A D | armv7m_systick.c | 70 uint32_t val; in systick_read() local 79 val = s->control; in systick_read() 83 val = ptimer_get_limit(s->ptimer); in systick_read() 86 val = ptimer_get_count(s->ptimer); in systick_read() 102 val = SYSCALIB_NOREF; in systick_read() 105 val = clock_ns_to_ticks(s->refclk, 10 * SCALE_MS) - 1; in systick_read() 106 val &= SYSCALIB_TENMS; in systick_read() 109 val |= SYSCALIB_SKEW; in systick_read() 113 val = 0; in systick_read() 119 trace_systick_read(addr, val, size); in systick_read() [all …]
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/qemu/hw/pci/ |
H A D | pcie_aer.c | 833 uint32_t val; member 844 .val = PCI_ERR_UNC_DLP, 848 .val = PCI_ERR_UNC_SDN, 856 .val = PCI_ERR_UNC_FCP, 880 .val = PCI_ERR_UNC_ECRC, 884 .val = PCI_ERR_UNC_UNSUP, 888 .val = PCI_ERR_UNC_ACSV, 892 .val = PCI_ERR_UNC_INTN, 896 .val = PCI_ERR_UNC_MCBTLP, 908 .val = PCI_ERR_COR_RCVR, [all …]
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/qemu/tests/qtest/ |
H A D | pvpanic-test.c | 16 uint8_t val; in test_panic_nopause() local 22 val = qtest_inb(qts, 0x505); in test_panic_nopause() 23 g_assert_cmpuint(val, ==, 3); in test_panic_nopause() 39 uint8_t val; in test_panic() local 45 val = qtest_inb(qts, 0x505); in test_panic() 46 g_assert_cmpuint(val, ==, 3); in test_panic()
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/qemu/disas/ |
H A D | m68k.c | 687 int val = 0; in fetch_arg() local 1093 int val = 0; in print_insn_arg() local 1188 val = 8; in print_insn_arg() 1196 val = -1; in print_insn_arg() 1211 val = val - 0x100; in print_insn_arg() 1407 val = ((val & 7) << 3) + ((val >> 3) & 7); in print_insn_arg() 1529 if (val) in print_insn_arg() 1556 val = newval; in print_insn_arg() 1594 val = newval; in print_insn_arg() 1876 int val; in print_insn_m68k() local [all …]
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/qemu/include/exec/ |
H A D | memory_ldst.h.inc | 30 hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); 32 hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result); 34 hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); 36 hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); 53 hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result); 55 hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result); 57 hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result); 59 hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); 61 hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); 63 hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); [all …]
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/qemu/hw/ipmi/ |
H A D | ipmi_bt.c | 238 if (IPMI_BT_GET_CLR_WR(val)) { in ipmi_bt_ioport_write() 241 if (IPMI_BT_GET_CLR_RD(val)) { in ipmi_bt_ioport_write() 244 if (IPMI_BT_GET_B2H_ATN(val)) { in ipmi_bt_ioport_write() 247 if (IPMI_BT_GET_SMS_ATN(val)) { in ipmi_bt_ioport_write() 250 if (IPMI_BT_GET_HBUSY(val)) { in ipmi_bt_ioport_write() 255 if (IPMI_BT_GET_H2B_ATN(val)) { in ipmi_bt_ioport_write() 263 ib->inmsg[ib->inlen] = val; in ipmi_bt_ioport_write() 269 if (IPMI_BT_GET_B2H_IRQ_EN(val) != in ipmi_bt_ioport_write() 271 if (IPMI_BT_GET_B2H_IRQ_EN(val)) { in ipmi_bt_ioport_write() 317 if (val) { in ipmi_bt_set_atn() [all …]
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