1module S6CLK2PIN
2(
3    input I,
4    output O
5);
6
7    ODDR2 #(
8           .DDR_ALIGNMENT("NONE"), // to "NONE", "C0" or "C1"
9           .INIT(1'b0),            // output to 1'b0 or 1'b1
10           .SRTYPE("ASYNC"))        // set/reset "SYNC" or "ASYNC"
11
12         ODDR2_S6CLK2PIN
13           (
14        .Q(O),  // 1-bit DDR output data
15        .C0(I), // 1-bit clock input
16        .C1(~I), // 1-bit clock input
17        .CE(1'b1), // 1-bit clock enable input
18        .D0(1'b1), // 1-bit data input (associated with C0)
19        .D1(1'b0), // 1-bit data input (associated with C1)
20        .R(1'b0),  // 1-bit reset input
21        .S(1'b0) );// 1-bit set input
22
23endmodule //S6CLK2PIN
24