1 ///////////////////////////////////////////////////////////////////////// 2 // $Id: instr.h 14086 2021-01-30 08:35:35Z sshwarts $ 3 ///////////////////////////////////////////////////////////////////////// 4 // 5 // Copyright (c) 2016-2017 Stanislav Shwartsman 6 // Written by Stanislav Shwartsman [sshwarts at sourceforge net] 7 // 8 // This library is free software; you can redistribute it and/or 9 // modify it under the terms of the GNU Lesser General Public 10 // License as published by the Free Software Foundation; either 11 // version 2 of the License, or (at your option) any later version. 12 // 13 // This library is distributed in the hope that it will be useful, 14 // but WITHOUT ANY WARRANTY; without even the implied warranty of 15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 // Lesser General Public License for more details. 17 // 18 // You should have received a copy of the GNU Lesser General Public 19 // License along with this library; if not, write to the Free Software 20 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA 21 // 22 ///////////////////////////////////////////////////////////////////////// 23 24 #ifndef BX_INSTR_H 25 #define BX_INSTR_H 26 27 extern bx_address bx_asize_mask[]; 28 29 const char *get_bx_opcode_name(Bit16u ia_opcode); 30 const char *get_intel_disasm_opcode_name(Bit16u ia_opcode); 31 const char *get_gas_disasm_opcode_name(Bit16u ia_opcode); 32 33 class BX_CPU_C; 34 class bxInstruction_c; 35 36 #ifndef BX_STANDALONE_DECODER 37 38 // <TAG-TYPE-EXECUTEPTR-START> 39 #if BX_USE_CPU_SMF 40 typedef void (BX_CPP_AttrRegparmN(1) *BxExecutePtr_tR)(bxInstruction_c *); 41 #else 42 typedef void (BX_CPU_C::*BxExecutePtr_tR)(bxInstruction_c *) BX_CPP_AttrRegparmN(1); 43 #endif 44 // <TAG-TYPE-EXECUTEPTR-END> 45 46 #endif 47 48 // <TAG-CLASS-INSTRUCTION-START> 49 class bxInstruction_c { 50 public: 51 52 #ifndef BX_STANDALONE_DECODER 53 // Function pointers; a function to resolve the modRM address 54 // given the current state of the CPU and the instruction data, 55 // and a function to execute the instruction after resolving 56 // the memory address (if any). 57 BxExecutePtr_tR execute1; 58 59 union { 60 BxExecutePtr_tR execute2; 61 bxInstruction_c *next; 62 } handlers; 63 #endif 64 65 struct { 66 // 15...0 opcode 67 Bit16u ia_opcode; 68 69 // 7...4 (unused) 70 // 3...0 ilen (0..15) 71 Bit8u ilen; 72 73 #define BX_LOCK_PREFIX_USED 1 74 // 7...6 lockUsed, repUsed (0=none, 1=0xF0, 2=0xF2, 3=0xF3) 75 // 5...5 extend8bit 76 // 4...4 mod==c0 (modrm) 77 // 3...3 os64 78 // 2...2 os32 79 // 1...1 as64 80 // 0...0 as32 81 Bit8u metaInfo1; 82 } metaInfo; 83 84 enum { 85 BX_INSTR_METADATA_DST = 0, 86 BX_INSTR_METADATA_SRC1 = 1, 87 BX_INSTR_METADATA_SRC2 = 2, 88 BX_INSTR_METADATA_SRC3 = 3, 89 BX_INSTR_METADATA_CET_SEGOVERRIDE = 3, // share src3 90 BX_INSTR_METADATA_SEG = 4, 91 BX_INSTR_METADATA_BASE = 5, 92 BX_INSTR_METADATA_INDEX = 6, 93 BX_INSTR_METADATA_SCALE = 7 94 }; 95 96 // using 5-bit field for registers (16 regs in 64-bit, RIP, NIL) 97 Bit8u metaData[8]; 98 99 union { 100 // Form (longest case): [opcode+modrm+sib/displacement32/immediate32] 101 struct { 102 union { 103 Bit32u Id; 104 Bit16u Iw[2]; 105 // use Ib[3] as EVEX mask register 106 // use Ib[2] as AVX attributes 107 // 7..5 (unused) 108 // 4..4 VEX.W 109 // 3..3 Broadcast/RC/SAE control (EVEX.b) 110 // 2..2 Zeroing/Merging mask (EVEX.z) 111 // 1..0 Round control 112 // use Ib[1] as AVX VL 113 Bit8u Ib[4]; 114 }; 115 union { 116 Bit16u displ16u; // for 16-bit modrm forms 117 Bit32u displ32u; // for 32-bit modrm forms 118 119 Bit32u Id2; 120 Bit16u Iw2[2]; 121 Bit8u Ib2[4]; 122 }; 123 } modRMForm; 124 125 #if BX_SUPPORT_X86_64 126 struct { 127 Bit64u Iq; // for MOV Rx,imm64 128 } IqForm; 129 #endif 130 }; 131 132 #ifdef BX_INSTR_STORE_OPCODE_BYTES 133 Bit8u opcode_bytes[16]; 134 get_opcode_bytes(void)135 BX_CPP_INLINE const Bit8u* get_opcode_bytes(void) const { 136 return opcode_bytes; 137 } 138 set_opcode_bytes(const Bit8u * opcode)139 BX_CPP_INLINE void set_opcode_bytes(const Bit8u *opcode) { 140 memcpy(opcode_bytes, opcode, ilen()); 141 } 142 #endif 143 144 #ifndef BX_STANDALONE_DECODER execute2(void)145 BX_CPP_INLINE BxExecutePtr_tR execute2(void) const { 146 return handlers.execute2; 147 } 148 #endif 149 seg(void)150 BX_CPP_INLINE unsigned seg(void) const { 151 return metaData[BX_INSTR_METADATA_SEG]; 152 } setSeg(unsigned val)153 BX_CPP_INLINE void setSeg(unsigned val) { 154 metaData[BX_INSTR_METADATA_SEG] = val; 155 } 156 157 #if BX_SUPPORT_CET segOverrideCet(void)158 BX_CPP_INLINE unsigned segOverrideCet(void) const { 159 return metaData[BX_INSTR_METADATA_CET_SEGOVERRIDE]; 160 } setCetSegOverride(unsigned val)161 BX_CPP_INLINE void setCetSegOverride(unsigned val) { 162 metaData[BX_INSTR_METADATA_CET_SEGOVERRIDE] = val; 163 } 164 #endif 165 setFoo(unsigned foo)166 BX_CPP_INLINE void setFoo(unsigned foo) { 167 // none of x87 instructions has immediate 168 modRMForm.Iw[0] = foo; 169 } foo()170 BX_CPP_INLINE unsigned foo() const { 171 return modRMForm.Iw[0]; 172 } b1()173 BX_CPP_INLINE unsigned b1() const { 174 return modRMForm.Iw[0] >> 8; 175 } 176 setSibScale(unsigned scale)177 BX_CPP_INLINE void setSibScale(unsigned scale) { 178 metaData[BX_INSTR_METADATA_SCALE] = scale; 179 } sibScale()180 BX_CPP_INLINE unsigned sibScale() const { 181 return metaData[BX_INSTR_METADATA_SCALE]; 182 } setSibIndex(unsigned index)183 BX_CPP_INLINE void setSibIndex(unsigned index) { 184 metaData[BX_INSTR_METADATA_INDEX] = index; 185 } sibIndex()186 BX_CPP_INLINE unsigned sibIndex() const { 187 return metaData[BX_INSTR_METADATA_INDEX]; 188 } setSibBase(unsigned base)189 BX_CPP_INLINE void setSibBase(unsigned base) { 190 metaData[BX_INSTR_METADATA_BASE] = base; 191 } sibBase()192 BX_CPP_INLINE unsigned sibBase() const { 193 return metaData[BX_INSTR_METADATA_BASE]; 194 } displ32s()195 BX_CPP_INLINE Bit32s displ32s() const { return (Bit32s) modRMForm.displ32u; } displ16s()196 BX_CPP_INLINE Bit16s displ16s() const { return (Bit16s) modRMForm.displ16u; } Id()197 BX_CPP_INLINE Bit32u Id() const { return modRMForm.Id; } Iw()198 BX_CPP_INLINE Bit16u Iw() const { return modRMForm.Iw[0]; } Ib()199 BX_CPP_INLINE Bit8u Ib() const { return modRMForm.Ib[0]; } Id2()200 BX_CPP_INLINE Bit16u Id2() const { return modRMForm.Id2; } Iw2()201 BX_CPP_INLINE Bit16u Iw2() const { return modRMForm.Iw2[0]; } Ib2()202 BX_CPP_INLINE Bit8u Ib2() const { return modRMForm.Ib2[0]; } 203 #if BX_SUPPORT_X86_64 Iq()204 BX_CPP_INLINE Bit64u Iq() const { return IqForm.Iq; } 205 #endif 206 207 // Info in the metaInfo field. 208 // Note: the 'L' at the end of certain flags, means the value returned 209 // is for Logical comparisons, eg if (i->os32L() && i->as32L()). If you 210 // want a bool value, use os32B() etc. This makes for smaller 211 // code, when a strict 0 or 1 is not necessary. init(unsigned os32,unsigned as32,unsigned os64,unsigned as64)212 BX_CPP_INLINE void init(unsigned os32, unsigned as32, unsigned os64, unsigned as64) 213 { 214 metaInfo.metaInfo1 = (os32<<2) | (os64<<3) | (as32<<0) | (as64<<1); 215 } 216 os32L(void)217 BX_CPP_INLINE unsigned os32L(void) const { 218 return metaInfo.metaInfo1 & (1<<2); 219 } setOs32B(unsigned bit)220 BX_CPP_INLINE void setOs32B(unsigned bit) { 221 metaInfo.metaInfo1 = (metaInfo.metaInfo1 & ~(1<<2)) | (bit<<2); 222 } assertOs32(void)223 BX_CPP_INLINE void assertOs32(void) { 224 metaInfo.metaInfo1 |= (1<<2); 225 } 226 227 #if BX_SUPPORT_X86_64 os64L(void)228 BX_CPP_INLINE unsigned os64L(void) const { 229 return metaInfo.metaInfo1 & (1<<3); 230 } assertOs64(void)231 BX_CPP_INLINE void assertOs64(void) { 232 metaInfo.metaInfo1 |= (1<<3); 233 } 234 #else os64L(void)235 BX_CPP_INLINE unsigned os64L(void) const { return 0; } 236 #endif osize(void)237 BX_CPP_INLINE unsigned osize(void) const { 238 return (metaInfo.metaInfo1 >> 2) & 0x3; 239 } 240 as32L(void)241 BX_CPP_INLINE unsigned as32L(void) const { 242 return metaInfo.metaInfo1 & 0x1; 243 } setAs32B(unsigned bit)244 BX_CPP_INLINE void setAs32B(unsigned bit) { 245 metaInfo.metaInfo1 = (metaInfo.metaInfo1 & ~0x1) | (bit); 246 } 247 248 #if BX_SUPPORT_X86_64 as64L(void)249 BX_CPP_INLINE unsigned as64L(void) const { 250 return metaInfo.metaInfo1 & (1<<1); 251 } clearAs64(void)252 BX_CPP_INLINE void clearAs64(void) { 253 metaInfo.metaInfo1 &= ~(1<<1); 254 } 255 #else as64L(void)256 BX_CPP_INLINE unsigned as64L(void) const { return 0; } 257 #endif 258 asize(void)259 BX_CPP_INLINE unsigned asize(void) const { 260 return metaInfo.metaInfo1 & 0x3; 261 } asize_mask(void)262 BX_CPP_INLINE bx_address asize_mask(void) const { 263 return bx_asize_mask[asize()]; 264 } 265 266 #if BX_SUPPORT_X86_64 extend8bitL(void)267 BX_CPP_INLINE unsigned extend8bitL(void) const { 268 return metaInfo.metaInfo1 & (1<<5); 269 } assertExtend8bit(void)270 BX_CPP_INLINE void assertExtend8bit(void) { 271 metaInfo.metaInfo1 |= (1<<5); 272 } 273 #endif 274 ilen(void)275 BX_CPP_INLINE unsigned ilen(void) const { 276 return metaInfo.ilen; 277 } setILen(unsigned ilen)278 BX_CPP_INLINE void setILen(unsigned ilen) { 279 metaInfo.ilen = ilen; 280 } 281 getIaOpcode(void)282 BX_CPP_INLINE unsigned getIaOpcode(void) const { 283 return metaInfo.ia_opcode; 284 } setIaOpcode(Bit16u op)285 BX_CPP_INLINE void setIaOpcode(Bit16u op) { 286 metaInfo.ia_opcode = op; 287 } getIaOpcodeName(void)288 BX_CPP_INLINE const char* getIaOpcodeName(void) const { 289 return get_bx_opcode_name(getIaOpcode()); 290 } getIaOpcodeNameShort(void)291 BX_CPP_INLINE const char* getIaOpcodeNameShort(void) const { 292 return get_bx_opcode_name(getIaOpcode()) + /*"BX_IA_"*/ 6; 293 } 294 repUsedL(void)295 BX_CPP_INLINE unsigned repUsedL(void) const { 296 return metaInfo.metaInfo1 >> 7; 297 } lockRepUsedValue(void)298 BX_CPP_INLINE unsigned lockRepUsedValue(void) const { 299 return metaInfo.metaInfo1 >> 6; 300 } setLockRepUsed(unsigned value)301 BX_CPP_INLINE void setLockRepUsed(unsigned value) { 302 metaInfo.metaInfo1 = (metaInfo.metaInfo1 & 0x3f) | (value << 6); 303 } 304 setLock(void)305 BX_CPP_INLINE void setLock(void) { 306 setLockRepUsed(BX_LOCK_PREFIX_USED); 307 } getLock(void)308 BX_CPP_INLINE bool getLock(void) const { 309 return lockRepUsedValue() == BX_LOCK_PREFIX_USED; 310 } 311 getVL(void)312 BX_CPP_INLINE unsigned getVL(void) const { 313 #if BX_SUPPORT_AVX 314 return modRMForm.Ib[1]; 315 #else 316 return 0; 317 #endif 318 } setVL(unsigned value)319 BX_CPP_INLINE void setVL(unsigned value) { 320 modRMForm.Ib[1] = value; 321 } 322 323 #if BX_SUPPORT_AVX setVexW(unsigned bit)324 BX_CPP_INLINE void setVexW(unsigned bit) { 325 modRMForm.Ib[2] = (modRMForm.Ib[2] & ~(1<<4)) | (bit<<4); 326 } getVexW(void)327 BX_CPP_INLINE unsigned getVexW(void) const { 328 return modRMForm.Ib[2] & (1 << 4); 329 } 330 #else getVexW(void)331 BX_CPP_INLINE unsigned getVexW(void) const { return 0; } 332 #endif 333 334 #if BX_SUPPORT_EVEX setOpmask(unsigned reg)335 BX_CPP_INLINE void setOpmask(unsigned reg) { 336 modRMForm.Ib[3] = reg; 337 } opmask(void)338 BX_CPP_INLINE unsigned opmask(void) const { 339 return modRMForm.Ib[3]; 340 } 341 setEvexb(unsigned bit)342 BX_CPP_INLINE void setEvexb(unsigned bit) { 343 modRMForm.Ib[2] = (modRMForm.Ib[2] & ~(1<<3)) | (bit<<3); 344 } getEvexb(void)345 BX_CPP_INLINE unsigned getEvexb(void) const { 346 return modRMForm.Ib[2] & (1 << 3); 347 } 348 setZeroMasking(unsigned bit)349 BX_CPP_INLINE void setZeroMasking(unsigned bit) { 350 modRMForm.Ib[2] = (modRMForm.Ib[2] & ~(1<<2)) | (bit<<2); 351 } isZeroMasking(void)352 BX_CPP_INLINE unsigned isZeroMasking(void) const { 353 return modRMForm.Ib[2] & (1 << 2); 354 } 355 setRC(unsigned rc)356 BX_CPP_INLINE void setRC(unsigned rc) { 357 modRMForm.Ib[2] = (modRMForm.Ib[2] & ~0x3) | rc; 358 } getRC(void)359 BX_CPP_INLINE unsigned getRC(void) const { 360 return modRMForm.Ib[2] & 0x3; 361 } 362 #endif 363 setSrcReg(unsigned src,unsigned reg)364 BX_CPP_INLINE void setSrcReg(unsigned src, unsigned reg) { 365 metaData[src] = reg; 366 } getSrcReg(unsigned src)367 BX_CPP_INLINE unsigned getSrcReg(unsigned src) const { 368 return metaData[src]; 369 } 370 dst()371 BX_CPP_INLINE unsigned dst() const { 372 return metaData[BX_INSTR_METADATA_DST]; 373 } 374 src1()375 BX_CPP_INLINE unsigned src1() const { 376 return metaData[BX_INSTR_METADATA_SRC1]; 377 } src2()378 BX_CPP_INLINE unsigned src2() const { 379 return metaData[BX_INSTR_METADATA_SRC2]; 380 } src3()381 BX_CPP_INLINE unsigned src3() const { 382 return metaData[BX_INSTR_METADATA_SRC3]; 383 } 384 src()385 BX_CPP_INLINE unsigned src() const { return src1(); } 386 modC0()387 BX_CPP_INLINE unsigned modC0() const 388 { 389 // This is a cheaper way to test for modRM instructions where 390 // the mod field is 0xc0. FetchDecode flags this condition since 391 // it is quite common to be tested for. 392 return metaInfo.metaInfo1 & (1<<4); 393 } assertModC0()394 BX_CPP_INLINE void assertModC0() 395 { 396 metaInfo.metaInfo1 |= (1<<4); 397 } 398 399 #if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS && BX_ENABLE_TRACE_LINKING && !defined(BX_STANDALONE_DECODER) getNextTrace(Bit32u currTraceLinkTimeStamp)400 BX_CPP_INLINE bxInstruction_c* getNextTrace(Bit32u currTraceLinkTimeStamp) { 401 if (currTraceLinkTimeStamp > modRMForm.Id2) handlers.next = NULL; 402 return handlers.next; 403 } setNextTrace(bxInstruction_c * iptr,Bit32u traceLinkTimeStamp)404 BX_CPP_INLINE void setNextTrace(bxInstruction_c* iptr, Bit32u traceLinkTimeStamp) { 405 handlers.next = iptr; 406 modRMForm.Id2 = traceLinkTimeStamp; 407 } 408 #endif 409 410 }; 411 // <TAG-CLASS-INSTRUCTION-END> 412 413 enum BxDisasmStyle { 414 BX_DISASM_INTEL, 415 BX_DISASM_GAS 416 }; 417 418 extern char* disasm(const Bit8u *opcode, bool is_32, bool is_64, char *disbufptr, bxInstruction_c *i, bx_address cs_base, bx_address rip, BxDisasmStyle style = BX_DISASM_INTEL); 419 420 #endif 421