1/* $NetBSD: tsarm_start.S,v 1.7 2011/01/31 06:28:05 matt Exp $ */ 2 3/* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro@ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <machine/asm.h> 31#include <arm/armreg.h> 32#include "assym.h" 33 34#include <arm/ep93xx/ep93xxreg.h> 35 36RCSID("$NetBSD: tsarm_start.S,v 1.7 2011/01/31 06:28:05 matt Exp $") 37 38 .section .start,"ax",%progbits 39 40 .global _C_LABEL(ts7xxx_start) 41_C_LABEL(ts7xxx_start): 42 43 /* 44 * We will go ahead and disable the MMU here so that we don't 45 * have to worry about flushing caches, etc. 46 * 47 * Note that we may not currently be running VA==PA, which means 48 * we'll need to leap to the next insn after disabing the MMU. 49 */ 50 adr r8, Lunmapped 51 bic r8, r8, #0xff000000 /* clear upper 8 bits */ 52 53 /* 54 * Setup coprocessor 15. 55 */ 56 mrc p15, 0, r2, c1, c0, 0 57 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 58 mcr p15, 0, r2, c1, c0, 0 59 60 nop 61 nop 62 nop 63 64 mov pc, r8 /* Heave-ho! */ 65 66Lunmapped: 67 /* 68 * We want to construct a memory map that maps us 69 * VA==PA (SDRAM at 0x00000000). We create these 70 * mappings uncached and unbuffered to be safe. 71 */ 72 /* 73 * Step 1: Map the entire address space VA==PA. 74 */ 75 adr r4, Ltable 76 ldr r0, [r4] /* r0 = &l1table */ 77 78 mov r1, #(L1_TABLE_SIZE / 4) /* 4096 entry */ 79 mov r2, #(L1_S_SIZE) /* 1MB / section */ 80 mov r3, #(L1_S_AP_KRW) /* kernel read/write */ 81 orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 821: 83 str r3, [r0], #0x04 84 add r3, r3, r2 85 subs r1, r1, #1 86 bgt 1b 87 88 89 /* 90 * Step 2: Map VA 0xc0000000->0xc07fffff to PA 0x00000000->0x007fffff. 91 */ 92 ldr r0, [r4] 93 add r0, r0, #(0xc00 * 4) /* offset to 0xc00xxxxx */ 94 95 mov r1, #0x8 /* 8MB */ 96 mov r3, #(L1_S_AP_KRW) 97 orr r3, r3, #(L1_TYPE_S) 981: 99 str r3, [r0], #0x04 100 add r3, r3, r2 101 subs r1, r1, #1 102 bgt 1b 103 104 /* 105 * Step 3: Map VA 0xf0000000->0xf0100000 to PA 0x80000000->0x80100000. 106 */ 107 ldr r0, [r4] 108 109 add r0, r0, #(0xf00 * 4) /* offset to 0xf0000000 */ 110 mov r3, #0x80000000 111 orr r3, r3, #(L1_S_AP_KRW) 112 orr r3, r3, #(L1_TYPE_S) 113 str r3, [r0], #4 114 115 /* 116 * Step 4: Map VA 0xf0100000->0xf0300000 to PA 0x80800000->0x80a00000. 117 */ 118 mov r3, #0x80000000 119 add r3, r3, #0x00800000 120 orr r3, r3, #(L1_S_AP_KRW) 121 orr r3, r3, #(L1_TYPE_S) 122 str r3, [r0], #0x4 123 add r3, r3, r2 124 str r3, [r0], #0x4 125 126 /* 127 * Step 5: Map VA 0xf0300000->0xf4300000 to PA 0x10000000->0x14000000. 128 */ 129 mov r1, #0x40 /* 64MB */ 130 mov r3, #(L1_S_AP_KRW) 131 orr r3, r3, #(L1_TYPE_S) 132 orr r3, r3, #0x10000000 1331: 134 str r3, [r0], #0x04 135 add r3, r3, r2 136 subs r1, r1, #1 137 bgt 1b 138 139 /* 140 * Step 6: Map VA 0xf4300000->0xf8300000 to PA 0x20000000->0x24000000. 141 */ 142 mov r1, #0x40 /* 64MB */ 143 mov r3, #(L1_S_AP_KRW) 144 orr r3, r3, #(L1_TYPE_S) 145 orr r3, r3, #0x20000000 1461: 147 str r3, [r0], #0x04 148 add r3, r3, r2 149 subs r1, r1, #1 150 bgt 1b 151 152 153 /* OK! Page table is set up. Give it to the CPU. */ 154 adr r0, Ltable 155 ldr r0, [r0] 156 mcr p15, 0, r0, c2, c0, 0 157 158 /* Flush the old TLBs, just in case. */ 159 mcr p15, 0, r0, c8, c7, 0 160 161 /* Set the Domain Access register. Very important! */ 162 mov r0, #1 163 mcr p15, 0, r0, c3, c0, 0 164 165 /* Get ready to jump to the "real" kernel entry point... */ 166 ldr r1, Lstart 167 mov r1, r1 /* Make sure the load completes! */ 168 169 /* OK, let's enable the MMU. */ 170 mrc p15, 0, r2, c1, c0, 0 171 orr r2, r2, #CPU_CONTROL_MMU_ENABLE 172 mcr p15, 0, r2, c1, c0, 0 173 174 nop 175 nop 176 nop 177 178 /* CPWAIT sequence to make sure the MMU is on... */ 179 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 180 mov r2, r2 /* force it to complete */ 181 mov pc, r1 /* leap to kernel entry point! */ 182 183Ltable: 184 .word 0x4000 185 186Lstart: 187 .word start 188