1module myDFF (output reg Q, input CLK, D);
2	parameter [0:0] INIT = 1'b0;
3	initial Q = INIT;
4	always @(posedge CLK)
5		Q <= D;
6endmodule
7
8module myDFFE (output reg Q, input D, CLK, CE);
9	parameter [0:0] INIT = 1'b0;
10	initial Q = INIT;
11	always @(posedge CLK) begin
12		if (CE)
13			Q <= D;
14	end
15endmodule // DFFE (positive clock edge; clock enable)
16
17
18module myDFFS (output reg Q, input D, CLK, SET);
19	parameter [0:0] INIT = 1'b1;
20	initial Q = INIT;
21	always @(posedge CLK) begin
22		if (SET)
23			Q <= 1'b1;
24		else
25			Q <= D;
26	end
27endmodule // DFFS (positive clock edge; synchronous set)
28
29
30module myDFFSE (output reg Q, input D, CLK, CE, SET);
31	parameter [0:0] INIT = 1'b1;
32	initial Q = INIT;
33	always @(posedge CLK) begin
34		if (SET)
35			Q <= 1'b1;
36		else if (CE)
37			Q <= D;
38end
39endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
40
41
42module myDFFR (output reg Q, input D, CLK, RESET);
43	parameter [0:0] INIT = 1'b0;
44	initial Q = INIT;
45	always @(posedge CLK) begin
46		if (RESET)
47			Q <= 1'b0;
48		else
49			Q <= D;
50	end
51endmodule // DFFR (positive clock edge; synchronous reset)
52
53
54module myDFFRE (output reg Q, input D, CLK, CE, RESET);
55	parameter [0:0] INIT = 1'b0;
56	initial Q = INIT;
57	always @(posedge CLK) begin
58		if (RESET)
59			Q <= 1'b0;
60		else if (CE)
61			Q <= D;
62	end
63endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
64
65
66module myDFFP (output reg Q, input D, CLK, PRESET);
67	parameter [0:0] INIT = 1'b1;
68	initial Q = INIT;
69	always @(posedge CLK or posedge PRESET) begin
70		if(PRESET)
71			Q <= 1'b1;
72		else
73			Q <= D;
74	end
75endmodule // DFFP (positive clock edge; asynchronous preset)
76
77
78module myDFFPE (output reg Q, input D, CLK, CE, PRESET);
79	parameter [0:0] INIT = 1'b1;
80	initial Q = INIT;
81	always @(posedge CLK or posedge PRESET) begin
82		if(PRESET)
83			Q <= 1'b1;
84		else if (CE)
85			Q <= D;
86	end
87endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
88
89
90module myDFFC (output reg Q, input D, CLK, CLEAR);
91	parameter [0:0] INIT = 1'b0;
92	initial Q = INIT;
93	always @(posedge CLK or posedge CLEAR) begin
94		if(CLEAR)
95			Q <= 1'b0;
96		else
97			Q <= D;
98	end
99endmodule // DFFC (positive clock edge; asynchronous clear)
100
101
102module myDFFCE (output reg Q, input D, CLK, CE, CLEAR);
103	parameter [0:0] INIT = 1'b0;
104	initial Q = INIT;
105	always @(posedge CLK or posedge CLEAR) begin
106		if(CLEAR)
107			Q <= 1'b0;
108		else if (CE)
109			Q <= D;
110	end
111endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
112
113
114module myDFFN (output reg Q, input CLK, D);
115	parameter [0:0] INIT = 1'b0;
116	initial Q = INIT;
117	always @(negedge CLK)
118		Q <= D;
119endmodule
120
121module myDFFNE (output reg Q, input D, CLK, CE);
122	parameter [0:0] INIT = 1'b0;
123	initial Q = INIT;
124	always @(negedge CLK) begin
125		if (CE)
126			Q <= D;
127	end
128endmodule // DFFNE (negative clock edge; clock enable)
129
130
131module myDFFNS (output reg Q, input D, CLK, SET);
132	parameter [0:0] INIT = 1'b1;
133	initial Q = INIT;
134	always @(negedge CLK) begin
135		if (SET)
136			Q <= 1'b1;
137		else
138			Q <= D;
139	end
140endmodule // DFFNS (negative clock edge; synchronous set)
141
142
143module myDFFNSE (output reg Q, input D, CLK, CE, SET);
144	parameter [0:0] INIT = 1'b1;
145	initial Q = INIT;
146	always @(negedge CLK) begin
147		if (SET)
148			Q <= 1'b1;
149		else if (CE)
150			Q <= D;
151end
152endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
153
154
155module myDFFNR (output reg Q, input D, CLK, RESET);
156	parameter [0:0] INIT = 1'b0;
157	initial Q = INIT;
158	always @(negedge CLK) begin
159		if (RESET)
160			Q <= 1'b0;
161		else
162			Q <= D;
163	end
164endmodule // DFFNR (negative clock edge; synchronous reset)
165
166
167module myDFFNRE (output reg Q, input D, CLK, CE, RESET);
168	parameter [0:0] INIT = 1'b0;
169	initial Q = INIT;
170	always @(negedge CLK) begin
171		if (RESET)
172			Q <= 1'b0;
173		else if (CE)
174			Q <= D;
175	end
176endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
177
178
179module myDFFNP (output reg Q, input D, CLK, PRESET);
180	parameter [0:0] INIT = 1'b1;
181	initial Q = INIT;
182	always @(negedge CLK or posedge PRESET) begin
183		if(PRESET)
184			Q <= 1'b1;
185		else
186			Q <= D;
187	end
188endmodule // DFFNP (negative clock edge; asynchronous preset)
189
190
191module myDFFNPE (output reg Q, input D, CLK, CE, PRESET);
192	parameter [0:0] INIT = 1'b1;
193	initial Q = INIT;
194	always @(negedge CLK or posedge PRESET) begin
195		if(PRESET)
196			Q <= 1'b1;
197		else if (CE)
198			Q <= D;
199	end
200endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
201
202
203module myDFFNC (output reg Q, input D, CLK, CLEAR);
204	parameter [0:0] INIT = 1'b0;
205	initial Q = INIT;
206	always @(negedge CLK or posedge CLEAR) begin
207		if(CLEAR)
208			Q <= 1'b0;
209		else
210			Q <= D;
211	end
212endmodule // DFFNC (negative clock edge; asynchronous clear)
213
214
215module myDFFNCE (output reg Q, input D, CLK, CE, CLEAR);
216	parameter [0:0] INIT = 1'b0;
217	initial Q = INIT;
218	always @(negedge CLK or posedge CLEAR) begin
219		if(CLEAR)
220			Q <= 1'b0;
221		else if (CE)
222			Q <= D;
223	end
224endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
225