1//===- TableGen'erated file -------------------------------------*- C++ -*-===// 2// 3// Subtarget Enumeration Source Fragment 4// 5// Automatically generated file, do not edit! 6// 7//===----------------------------------------------------------------------===// 8 9#include "llvm/Support/Debug.h" 10#include "llvm/Support/raw_ostream.h" 11#include "llvm/Target/SubtargetFeature.h" 12#include "llvm/Target/TargetInstrItineraries.h" 13 14enum { 15 Feature3DNow = 1 << 0, 16 Feature3DNowA = 1 << 1, 17 Feature64Bit = 1 << 2, 18 FeatureAES = 1 << 3, 19 FeatureAVX = 1 << 4, 20 FeatureCLMUL = 1 << 5, 21 FeatureCMOV = 1 << 6, 22 FeatureFMA3 = 1 << 7, 23 FeatureFMA4 = 1 << 8, 24 FeatureFastUAMem = 1 << 9, 25 FeatureMMX = 1 << 10, 26 FeatureSSE1 = 1 << 11, 27 FeatureSSE2 = 1 << 12, 28 FeatureSSE3 = 1 << 13, 29 FeatureSSE41 = 1 << 14, 30 FeatureSSE42 = 1 << 15, 31 FeatureSSE4A = 1 << 16, 32 FeatureSSSE3 = 1 << 17, 33 FeatureSlowBTMem = 1 << 18, 34 FeatureVectorUAMem = 1 << 19 35}; 36 37// Sorted (by key) array of values for CPU features. 38static const llvm::SubtargetFeatureKV FeatureKV[] = { 39 { "3dnow", "Enable 3DNow! instructions", Feature3DNow, 0 }, 40 { "3dnowa", "Enable 3DNow! Athlon instructions", Feature3DNowA, Feature3DNow }, 41 { "64bit", "Support 64-bit instructions", Feature64Bit, FeatureCMOV }, 42 { "aes", "Enable AES instructions", FeatureAES, 0 }, 43 { "avx", "Enable AVX instructions", FeatureAVX, 0 }, 44 { "clmul", "Enable carry-less multiplication instructions", FeatureCLMUL, 0 }, 45 { "cmov", "Enable conditional move instructions", FeatureCMOV, 0 }, 46 { "fast-unaligned-mem", "Fast unaligned memory access", FeatureFastUAMem, 0 }, 47 { "fma3", "Enable three-operand fused multiple-add", FeatureFMA3, 0 }, 48 { "fma4", "Enable four-operand fused multiple-add", FeatureFMA4, 0 }, 49 { "mmx", "Enable MMX instructions", FeatureMMX, 0 }, 50 { "slow-bt-mem", "Bit testing of memory is slow", FeatureSlowBTMem, 0 }, 51 { "sse", "Enable SSE instructions", FeatureSSE1, FeatureMMX | FeatureCMOV }, 52 { "sse2", "Enable SSE2 instructions", FeatureSSE2, FeatureSSE1 }, 53 { "sse3", "Enable SSE3 instructions", FeatureSSE3, FeatureSSE2 }, 54 { "sse41", "Enable SSE 4.1 instructions", FeatureSSE41, FeatureSSSE3 }, 55 { "sse42", "Enable SSE 4.2 instructions", FeatureSSE42, FeatureSSE41 }, 56 { "sse4a", "Support SSE 4a instructions", FeatureSSE4A, 0 }, 57 { "ssse3", "Enable SSSE3 instructions", FeatureSSSE3, FeatureSSE3 }, 58 { "vector-unaligned-mem", "Allow unaligned memory operands on vector/SIMD instructions", FeatureVectorUAMem, 0 } 59}; 60 61enum { 62 FeatureKVSize = sizeof(FeatureKV)/sizeof(llvm::SubtargetFeatureKV) 63}; 64 65// Sorted (by key) array of values for CPU subtype. 66static const llvm::SubtargetFeatureKV SubTypeKV[] = { 67 { "amdfam10", "Select the amdfam10 processor", FeatureSSE3 | FeatureSSE4A | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 }, 68 { "athlon", "Select the athlon processor", FeatureMMX | Feature3DNowA | FeatureSlowBTMem, 0 }, 69 { "athlon-4", "Select the athlon-4 processor", FeatureSSE1 | Feature3DNowA | FeatureSlowBTMem, 0 }, 70 { "athlon-fx", "Select the athlon-fx processor", FeatureSSE2 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 }, 71 { "athlon-mp", "Select the athlon-mp processor", FeatureSSE1 | Feature3DNowA | FeatureSlowBTMem, 0 }, 72 { "athlon-tbird", "Select the athlon-tbird processor", FeatureMMX | Feature3DNowA | FeatureSlowBTMem, 0 }, 73 { "athlon-xp", "Select the athlon-xp processor", FeatureSSE1 | Feature3DNowA | FeatureSlowBTMem, 0 }, 74 { "athlon64", "Select the athlon64 processor", FeatureSSE2 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 }, 75 { "athlon64-sse3", "Select the athlon64-sse3 processor", FeatureSSE3 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 }, 76 { "atom", "Select the atom processor", FeatureSSE3 | Feature64Bit | FeatureSlowBTMem, 0 }, 77 { "barcelona", "Select the barcelona processor", FeatureSSE3 | FeatureSSE4A | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 }, 78 { "c3", "Select the c3 processor", FeatureMMX | Feature3DNow, 0 }, 79 { "c3-2", "Select the c3-2 processor", FeatureSSE1, 0 }, 80 { "core2", "Select the core2 processor", FeatureSSSE3 | Feature64Bit | FeatureSlowBTMem, 0 }, 81 { "corei7", "Select the corei7 processor", FeatureSSE42 | Feature64Bit | FeatureSlowBTMem | FeatureFastUAMem | FeatureAES, 0 }, 82 { "generic", "Select the generic processor", 0, 0 }, 83 { "i386", "Select the i386 processor", 0, 0 }, 84 { "i486", "Select the i486 processor", 0, 0 }, 85 { "i586", "Select the i586 processor", 0, 0 }, 86 { "i686", "Select the i686 processor", 0, 0 }, 87 { "istanbul", "Select the istanbul processor", Feature3DNowA | Feature64Bit | FeatureSSE4A | Feature3DNowA, 0 }, 88 { "k6", "Select the k6 processor", FeatureMMX, 0 }, 89 { "k6-2", "Select the k6-2 processor", FeatureMMX | Feature3DNow, 0 }, 90 { "k6-3", "Select the k6-3 processor", FeatureMMX | Feature3DNow, 0 }, 91 { "k8", "Select the k8 processor", FeatureSSE2 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 }, 92 { "k8-sse3", "Select the k8-sse3 processor", FeatureSSE3 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 }, 93 { "nehalem", "Select the nehalem processor", FeatureSSE42 | Feature64Bit | FeatureSlowBTMem | FeatureFastUAMem, 0 }, 94 { "nocona", "Select the nocona processor", FeatureSSE3 | Feature64Bit | FeatureSlowBTMem, 0 }, 95 { "opteron", "Select the opteron processor", FeatureSSE2 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 }, 96 { "opteron-sse3", "Select the opteron-sse3 processor", FeatureSSE3 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 }, 97 { "penryn", "Select the penryn processor", FeatureSSE41 | Feature64Bit | FeatureSlowBTMem, 0 }, 98 { "pentium", "Select the pentium processor", 0, 0 }, 99 { "pentium-m", "Select the pentium-m processor", FeatureSSE2 | FeatureSlowBTMem, 0 }, 100 { "pentium-mmx", "Select the pentium-mmx processor", FeatureMMX, 0 }, 101 { "pentium2", "Select the pentium2 processor", FeatureMMX | FeatureCMOV, 0 }, 102 { "pentium3", "Select the pentium3 processor", FeatureSSE1, 0 }, 103 { "pentium4", "Select the pentium4 processor", FeatureSSE2, 0 }, 104 { "pentiumpro", "Select the pentiumpro processor", FeatureCMOV, 0 }, 105 { "prescott", "Select the prescott processor", FeatureSSE3 | FeatureSlowBTMem, 0 }, 106 { "sandybridge", "Select the sandybridge processor", FeatureSSE42 | FeatureAVX | Feature64Bit, 0 }, 107 { "shanghai", "Select the shanghai processor", Feature3DNowA | Feature64Bit | FeatureSSE4A | Feature3DNowA, 0 }, 108 { "westmere", "Select the westmere processor", FeatureSSE42 | Feature64Bit | FeatureSlowBTMem | FeatureFastUAMem | FeatureAES, 0 }, 109 { "winchip-c6", "Select the winchip-c6 processor", FeatureMMX, 0 }, 110 { "winchip2", "Select the winchip2 processor", FeatureMMX | Feature3DNow, 0 }, 111 { "x86-64", "Select the x86-64 processor", FeatureSSE2 | Feature64Bit | FeatureSlowBTMem, 0 }, 112 { "yonah", "Select the yonah processor", FeatureSSE3 | FeatureSlowBTMem, 0 } 113}; 114 115enum { 116 SubTypeKVSize = sizeof(SubTypeKV)/sizeof(llvm::SubtargetFeatureKV) 117}; 118 119 120enum { 121 ItinClassesSize = 1 122}; 123 124// ParseSubtargetFeatures - Parses features string setting specified 125// subtarget options. 126std::string llvm::X86Subtarget::ParseSubtargetFeatures(const std::string &FS, 127 const std::string &CPU) { 128 DEBUG(dbgs() << "\nFeatures:" << FS); 129 DEBUG(dbgs() << "\nCPU:" << CPU); 130 SubtargetFeatures Features(FS); 131 Features.setCPUIfNone(CPU); 132 uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize, 133 FeatureKV, FeatureKVSize); 134 if ((Bits & Feature3DNow) != 0 && X863DNowLevel < ThreeDNow) X863DNowLevel = ThreeDNow; 135 if ((Bits & Feature3DNowA) != 0 && X863DNowLevel < ThreeDNowA) X863DNowLevel = ThreeDNowA; 136 if ((Bits & Feature64Bit) != 0) HasX86_64 = true; 137 if ((Bits & FeatureAES) != 0) HasAES = true; 138 if ((Bits & FeatureAVX) != 0) HasAVX = true; 139 if ((Bits & FeatureCLMUL) != 0) HasCLMUL = true; 140 if ((Bits & FeatureCMOV) != 0) HasCMov = true; 141 if ((Bits & FeatureFMA3) != 0) HasFMA3 = true; 142 if ((Bits & FeatureFMA4) != 0) HasFMA4 = true; 143 if ((Bits & FeatureFastUAMem) != 0) IsUAMemFast = true; 144 if ((Bits & FeatureMMX) != 0 && X86SSELevel < MMX) X86SSELevel = MMX; 145 if ((Bits & FeatureSSE1) != 0 && X86SSELevel < SSE1) X86SSELevel = SSE1; 146 if ((Bits & FeatureSSE2) != 0 && X86SSELevel < SSE2) X86SSELevel = SSE2; 147 if ((Bits & FeatureSSE3) != 0 && X86SSELevel < SSE3) X86SSELevel = SSE3; 148 if ((Bits & FeatureSSE41) != 0 && X86SSELevel < SSE41) X86SSELevel = SSE41; 149 if ((Bits & FeatureSSE42) != 0 && X86SSELevel < SSE42) X86SSELevel = SSE42; 150 if ((Bits & FeatureSSE4A) != 0) HasSSE4A = true; 151 if ((Bits & FeatureSSSE3) != 0 && X86SSELevel < SSSE3) X86SSELevel = SSSE3; 152 if ((Bits & FeatureSlowBTMem) != 0) IsBTMemSlow = true; 153 if ((Bits & FeatureVectorUAMem) != 0) HasVectorUAMem = true; 154 return Features.getCPU(); 155} 156