1//===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This describes the available hardware counters for various subtargets.
10//
11//===----------------------------------------------------------------------===//
12
13def UnhaltedCoreCyclesPfmCounter : PfmCounter<"unhalted_core_cycles">;
14def UopsIssuedPfmCounter : PfmCounter<"uops_issued:any">;
15
16// No default counters on X86.
17def DefaultPfmCounters : ProcPfmCounters {}
18def : PfmCountersDefaultBinding<DefaultPfmCounters>;
19
20// Intel X86 Counters.
21defvar DefaultIntelPfmValidationCounters = [
22  PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">,
23  PfmValidationCounter<L1DCacheLoadMiss, "MEM_LOAD_UOPS_RETIRED:L1_MISS">,
24  PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,
25  PfmValidationCounter<DataTLBLoadMiss, "DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK">,
26  PfmValidationCounter<DataTLBStoreMiss, "DTLB_STORE_MISSES:MISS_CAUSES_A_WALK">,
27  PfmValidationCounter<InstructionTLBLoadMiss, "ITLB_MISSES:MISS_CAUSES_A_WALK">
28];
29
30def PentiumPfmCounters : ProcPfmCounters {
31  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
32  let UopsCounter = PfmCounter<"uops_retired">;
33}
34def : PfmCountersBinding<"pentiumpro", PentiumPfmCounters>;
35def : PfmCountersBinding<"pentium2", PentiumPfmCounters>;
36def : PfmCountersBinding<"pentium3", PentiumPfmCounters>;
37def : PfmCountersBinding<"pentium3m", PentiumPfmCounters>;
38def : PfmCountersBinding<"pentium-m", PentiumPfmCounters>;
39
40def CorePfmCounters : ProcPfmCounters {
41  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
42  let UopsCounter = PfmCounter<"uops_retired:any">;
43}
44def : PfmCountersBinding<"yonah", CorePfmCounters>;
45def : PfmCountersBinding<"prescott", CorePfmCounters>;
46
47def AtomPfmCounters : ProcPfmCounters {
48  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
49  let UopsCounter = PfmCounter<"uops_retired:any">;
50}
51def : PfmCountersBinding<"bonnell", AtomPfmCounters>;
52def : PfmCountersBinding<"atom", AtomPfmCounters>;
53
54def SLMPfmCounters : ProcPfmCounters {
55  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
56  let UopsCounter = PfmCounter<"uops_retired:any">;
57  let IssueCounters = [
58    PfmIssueCounter<"SLM_MEC_RSV", "mem_uop_retired:any_ld + mem_uop_retired:any_st">
59  ];
60}
61def : PfmCountersBinding<"silvermont", SLMPfmCounters>;
62def : PfmCountersBinding<"goldmont", SLMPfmCounters>;
63def : PfmCountersBinding<"goldmont-plus", SLMPfmCounters>;
64def : PfmCountersBinding<"tremont", SLMPfmCounters>;
65
66def KnightPfmCounters : ProcPfmCounters {
67  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
68  let UopsCounter = PfmCounter<"uops_retired:all">;
69}
70def : PfmCountersBinding<"knl", KnightPfmCounters>;
71def : PfmCountersBinding<"knm", KnightPfmCounters>;
72
73def Core2PfmCounters : ProcPfmCounters {
74  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
75  let UopsCounter = PfmCounter<"uops_retired:any">;
76  let IssueCounters = [
77    PfmIssueCounter<"SBPort0",  "rs_uops_dispatched_cycles:port_0">,
78    PfmIssueCounter<"SBPort1",  "rs_uops_dispatched_cycles:port_1">,
79    PfmIssueCounter<"SBPort23", "rs_uops_dispatched_cycles:port_2 + rs_uops_dispatched_cycles:port_3">,
80    PfmIssueCounter<"SBPort4",  "rs_uops_dispatched_cycles:port_4">,
81    PfmIssueCounter<"SBPort5",  "rs_uops_dispatched_cycles:port_5">
82  ];
83}
84def : PfmCountersBinding<"core2", Core2PfmCounters>;
85def : PfmCountersBinding<"penryn", Core2PfmCounters>;
86
87def NehalemPfmCounters : ProcPfmCounters {
88  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
89  let UopsCounter = PfmCounter<"uops_retired:any">;
90  let IssueCounters = [
91    PfmIssueCounter<"SBPort0",  "uops_executed:port0">,
92    PfmIssueCounter<"SBPort1",  "uops_executed:port1">,
93    PfmIssueCounter<"SBPort23", "uops_executed:port2_core + uops_executed:port3_core">,
94    PfmIssueCounter<"SBPort4",  "uops_executed:port4_core">,
95    PfmIssueCounter<"SBPort5",  "uops_executed:port5">
96  ];
97}
98def : PfmCountersBinding<"nehalem", NehalemPfmCounters>;
99def : PfmCountersBinding<"corei7", NehalemPfmCounters>;
100def : PfmCountersBinding<"westmere", NehalemPfmCounters>;
101
102def SandyBridgePfmCounters : ProcPfmCounters {
103  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
104  let UopsCounter = UopsIssuedPfmCounter;
105  let IssueCounters = [
106    PfmIssueCounter<"SBPort0",  "uops_dispatched_port:port_0">,
107    PfmIssueCounter<"SBPort1",  "uops_dispatched_port:port_1">,
108    PfmIssueCounter<"SBPort23", "uops_dispatched_port:port_2 + uops_dispatched_port:port_3">,
109    PfmIssueCounter<"SBPort4",  "uops_dispatched_port:port_4">,
110    PfmIssueCounter<"SBPort5",  "uops_dispatched_port:port_5">
111  ];
112  let ValidationCounters = DefaultIntelPfmValidationCounters;
113}
114def : PfmCountersBinding<"sandybridge", SandyBridgePfmCounters>;
115def : PfmCountersBinding<"ivybridge", SandyBridgePfmCounters>;
116
117def HaswellPfmCounters : ProcPfmCounters {
118  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
119  let UopsCounter = UopsIssuedPfmCounter;
120  let IssueCounters = [
121    PfmIssueCounter<"HWPort0", "uops_executed_port:port_0">,
122    PfmIssueCounter<"HWPort1", "uops_executed_port:port_1">,
123    PfmIssueCounter<"HWPort2", "uops_executed_port:port_2">,
124    PfmIssueCounter<"HWPort3", "uops_executed_port:port_3">,
125    PfmIssueCounter<"HWPort4", "uops_executed_port:port_4">,
126    PfmIssueCounter<"HWPort5", "uops_executed_port:port_5">,
127    PfmIssueCounter<"HWPort6", "uops_executed_port:port_6">,
128    PfmIssueCounter<"HWPort7", "uops_executed_port:port_7">
129  ];
130  let ValidationCounters = DefaultIntelPfmValidationCounters;
131}
132def : PfmCountersBinding<"haswell", HaswellPfmCounters>;
133
134def BroadwellPfmCounters : ProcPfmCounters {
135  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
136  let UopsCounter = UopsIssuedPfmCounter;
137  let IssueCounters = [
138    PfmIssueCounter<"BWPort0", "uops_executed_port:port_0">,
139    PfmIssueCounter<"BWPort1", "uops_executed_port:port_1">,
140    PfmIssueCounter<"BWPort2", "uops_executed_port:port_2">,
141    PfmIssueCounter<"BWPort3", "uops_executed_port:port_3">,
142    PfmIssueCounter<"BWPort4", "uops_executed_port:port_4">,
143    PfmIssueCounter<"BWPort5", "uops_executed_port:port_5">,
144    PfmIssueCounter<"BWPort6", "uops_executed_port:port_6">,
145    PfmIssueCounter<"BWPort7", "uops_executed_port:port_7">
146  ];
147  let ValidationCounters = DefaultIntelPfmValidationCounters;
148}
149def : PfmCountersBinding<"broadwell", BroadwellPfmCounters>;
150
151def SkylakeClientPfmCounters : ProcPfmCounters {
152  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
153  let UopsCounter = UopsIssuedPfmCounter;
154  let IssueCounters = [
155    PfmIssueCounter<"SKLPort0", "uops_dispatched_port:port_0">,
156    PfmIssueCounter<"SKLPort1", "uops_dispatched_port:port_1">,
157    PfmIssueCounter<"SKLPort2", "uops_dispatched_port:port_2">,
158    PfmIssueCounter<"SKLPort3", "uops_dispatched_port:port_3">,
159    PfmIssueCounter<"SKLPort4", "uops_dispatched_port:port_4">,
160    PfmIssueCounter<"SKLPort5", "uops_dispatched_port:port_5">,
161    PfmIssueCounter<"SKLPort6", "uops_dispatched_port:port_6">,
162    PfmIssueCounter<"SKLPort7", "uops_dispatched_port:port_7">
163  ];
164  let ValidationCounters = DefaultIntelPfmValidationCounters;
165}
166def : PfmCountersBinding<"skylake", SkylakeClientPfmCounters>;
167
168def SkylakeServerPfmCounters : ProcPfmCounters {
169  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
170  let UopsCounter = UopsIssuedPfmCounter;
171  let IssueCounters = [
172    PfmIssueCounter<"SKXPort0", "uops_dispatched_port:port_0">,
173    PfmIssueCounter<"SKXPort1", "uops_dispatched_port:port_1">,
174    PfmIssueCounter<"SKXPort2", "uops_dispatched_port:port_2">,
175    PfmIssueCounter<"SKXPort3", "uops_dispatched_port:port_3">,
176    PfmIssueCounter<"SKXPort4", "uops_dispatched_port:port_4">,
177    PfmIssueCounter<"SKXPort5", "uops_dispatched_port:port_5">,
178    PfmIssueCounter<"SKXPort6", "uops_dispatched_port:port_6">,
179    PfmIssueCounter<"SKXPort7", "uops_dispatched_port:port_7">
180  ];
181  let ValidationCounters = DefaultIntelPfmValidationCounters;
182}
183def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>;
184def : PfmCountersBinding<"cascadelake", SkylakeServerPfmCounters>;
185def : PfmCountersBinding<"cannonlake", SkylakeServerPfmCounters>;
186
187def IceLakePfmCounters : ProcPfmCounters {
188  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
189  let UopsCounter = UopsIssuedPfmCounter;
190  let IssueCounters = [
191    PfmIssueCounter<"ICXPort0",  "uops_dispatched_port:port_0">,
192    PfmIssueCounter<"ICXPort1",  "uops_dispatched_port:port_1">,
193    PfmIssueCounter<"ICXPort23", "uops_dispatched_port:port_2_3">,
194    PfmIssueCounter<"ICXPort49", "uops_dispatched_port:port_4_9">,
195    PfmIssueCounter<"ICXPort5",  "uops_dispatched_port:port_5">,
196    PfmIssueCounter<"ICXPort6",  "uops_dispatched_port:port_6">,
197    PfmIssueCounter<"ICXPort78", "uops_dispatched_port:port_7_8">
198  ];
199  let ValidationCounters = DefaultIntelPfmValidationCounters;
200}
201def : PfmCountersBinding<"icelake-client", IceLakePfmCounters>;
202def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>;
203def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>;
204def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>;
205
206// AMD X86 Counters.
207defvar DefaultAMDPfmValidationCounters = [
208  PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">,
209  PfmValidationCounter<L1DCacheLoadMiss, "L1-DCACHE-LOAD-MISSES">,
210  PfmValidationCounter<L1DCacheStoreMiss, "L1-DCACHE-STORE-MISSES">,
211  PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,
212  PfmValidationCounter<DataTLBLoadMiss, "DTLB-LOAD-MISSES">,
213  PfmValidationCounter<InstructionTLBLoadMiss, "ITLB-LOAD-MISSES">
214];
215
216// Set basic counters for AMD cpus that we know libpfm4 supports.
217def DefaultAMDPfmCounters : ProcPfmCounters {
218  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
219  let UopsCounter = PfmCounter<"retired_uops">;
220}
221def : PfmCountersBinding<"athlon", DefaultAMDPfmCounters>;
222def : PfmCountersBinding<"athlon-tbird", DefaultAMDPfmCounters>;
223def : PfmCountersBinding<"athlon-4", DefaultAMDPfmCounters>;
224def : PfmCountersBinding<"athlon-xp", DefaultAMDPfmCounters>;
225def : PfmCountersBinding<"athlon-mp", DefaultAMDPfmCounters>;
226def : PfmCountersBinding<"k8", DefaultAMDPfmCounters>;
227def : PfmCountersBinding<"opteron", DefaultAMDPfmCounters>;
228def : PfmCountersBinding<"athlon64", DefaultAMDPfmCounters>;
229def : PfmCountersBinding<"athlon-fx", DefaultAMDPfmCounters>;
230def : PfmCountersBinding<"k8-sse3", DefaultAMDPfmCounters>;
231def : PfmCountersBinding<"opteron-sse3", DefaultAMDPfmCounters>;
232def : PfmCountersBinding<"athlon64-sse3", DefaultAMDPfmCounters>;
233def : PfmCountersBinding<"amdfam10", DefaultAMDPfmCounters>;
234def : PfmCountersBinding<"barcelona", DefaultAMDPfmCounters>;
235
236def BdVer2PfmCounters : ProcPfmCounters {
237  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
238  let UopsCounter = PfmCounter<"retired_uops">;
239  let IssueCounters = [
240    PfmIssueCounter<"PdFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">,
241    PfmIssueCounter<"PdFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">,
242    PfmIssueCounter<"PdFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">,
243    PfmIssueCounter<"PdFPU3", "dispatched_fpu_ops:ops_pipe3 + dispatched_fpu_ops:ops_dual_pipe3">
244  ];
245}
246def : PfmCountersBinding<"bdver1", BdVer2PfmCounters>;
247def : PfmCountersBinding<"bdver2", BdVer2PfmCounters>;
248
249def BdVer3PfmCounters : ProcPfmCounters {
250  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
251  let UopsCounter = PfmCounter<"retired_uops">;
252  let IssueCounters = [
253    PfmIssueCounter<"SrFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">,
254    PfmIssueCounter<"SrFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">,
255    PfmIssueCounter<"SrFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">
256  ];
257}
258def : PfmCountersBinding<"bdver3", BdVer3PfmCounters>;
259def : PfmCountersBinding<"bdver4", BdVer3PfmCounters>;
260
261def BtVer1PfmCounters : ProcPfmCounters {
262  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
263  let UopsCounter = PfmCounter<"retired_uops">;
264  let IssueCounters = [
265    PfmIssueCounter<"BtFPU0", "dispatched_fpu:pipe0">,
266    PfmIssueCounter<"BtFPU1", "dispatched_fpu:pipe1">
267  ];
268}
269def : PfmCountersBinding<"btver1", BtVer1PfmCounters>;
270
271def BtVer2PfmCounters : ProcPfmCounters {
272  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
273  let UopsCounter = PfmCounter<"retired_uops">;
274  let IssueCounters = [
275    PfmIssueCounter<"JFPU0", "dispatched_fpu:pipe0">,
276    PfmIssueCounter<"JFPU1", "dispatched_fpu:pipe1">
277  ];
278}
279def : PfmCountersBinding<"btver2", BtVer2PfmCounters>;
280
281def ZnVer1PfmCounters : ProcPfmCounters {
282  let CycleCounter = PfmCounter<"cycles_not_in_halt">;
283  let UopsCounter = PfmCounter<"retired_uops">;
284  let IssueCounters = [
285    PfmIssueCounter<"ZnFPU0", "fpu_pipe_assignment:total0">,
286    PfmIssueCounter<"ZnFPU1", "fpu_pipe_assignment:total1">,
287    PfmIssueCounter<"ZnFPU2", "fpu_pipe_assignment:total2">,
288    PfmIssueCounter<"ZnFPU3", "fpu_pipe_assignment:total3">,
289    PfmIssueCounter<"ZnAGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">,
290    PfmIssueCounter<"ZnDivider", "div_op_count">
291  ];
292  let ValidationCounters = DefaultAMDPfmValidationCounters;
293}
294def : PfmCountersBinding<"znver1", ZnVer1PfmCounters>;
295
296def ZnVer2PfmCounters : ProcPfmCounters {
297  let CycleCounter = PfmCounter<"cycles_not_in_halt">;
298  let UopsCounter = PfmCounter<"retired_uops">;
299  let IssueCounters = [
300    PfmIssueCounter<"Zn2AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">,
301    PfmIssueCounter<"Zn2Divider", "div_op_count">
302  ];
303  let ValidationCounters = DefaultAMDPfmValidationCounters;
304}
305def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>;
306
307def ZnVer3PfmCounters : ProcPfmCounters {
308  let CycleCounter = PfmCounter<"cycles_not_in_halt">;
309  let UopsCounter = PfmCounter<"retired_ops">;
310  let IssueCounters = [
311    PfmIssueCounter<"Zn3Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">,
312    PfmIssueCounter<"Zn3FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">,
313    PfmIssueCounter<"Zn3Load", "ls_dispatch:ld_dispatch">,
314    PfmIssueCounter<"Zn3Store", "ls_dispatch:store_dispatch">,
315    PfmIssueCounter<"Zn3Divider", "div_op_count">
316  ];
317  let ValidationCounters = DefaultAMDPfmValidationCounters;
318}
319def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>;
320
321def ZnVer4PfmCounters : ProcPfmCounters {
322  let CycleCounter = PfmCounter<"cycles_not_in_halt">;
323  let UopsCounter = PfmCounter<"retired_ops">;
324  let IssueCounters = [
325    PfmIssueCounter<"Zn4Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">,
326    PfmIssueCounter<"Zn4FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">,
327    PfmIssueCounter<"Zn4Load", "ls_dispatch:ld_dispatch">,
328    PfmIssueCounter<"Zn4Store", "ls_dispatch:store_dispatch">,
329    PfmIssueCounter<"Zn4Divider", "div_op_count">,
330    PfmIssueCounter<"Zn4AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">
331  ];
332  let ValidationCounters = DefaultAMDPfmValidationCounters;
333}
334def : PfmCountersBinding<"znver4", ZnVer4PfmCounters>;
335