xref: /netbsd/sys/arch/amiga/dev/scivar.h (revision 5e3d155b)
1 /*	$NetBSD: scivar.h,v 1.19 2022/04/07 20:23:44 andvar Exp $	*/
2 
3 /*
4  * Copyright (c) 1990 The Regents of the University of California.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to Berkeley by
8  * Van Jacobson of Lawrence Berkeley Laboratory.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. Neither the name of the University nor the names of its contributors
19  *    may be used to endorse or promote products derived from this software
20  *    without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32  * SUCH DAMAGE.
33  *
34  *	@(#)scivar.h	7.1 (Berkeley) 5/8/90
35  */
36 #ifndef _SCIVAR_H_
37 #define _SCIVAR_H_
38 
39 struct sci_softc;
40 
41 struct	sci_softc {
42 	device_t sc_dev;
43 	struct	isr sc_isr;
44 	struct	scsipi_adapter sc_adapter;
45 	struct	scsipi_channel sc_channel;
46 	struct	scsipi_xfer *sc_xs;	/* transfer from high level code */
47 
48 	volatile u_char	*sci_data;	/* r: Current data */
49 	volatile u_char	*sci_odata;	/* w: Out data */
50 	volatile u_char	*sci_icmd;	/* rw: Initiator command */
51 	volatile u_char	*sci_mode;	/* rw: Mode */
52 	volatile u_char	*sci_tcmd;	/* rw: Target command */
53 	volatile u_char	*sci_bus_csr;	/* r: Bus Status */
54 	volatile u_char	*sci_sel_enb;	/* w: Select enable */
55 	volatile u_char	*sci_csr;	/* r: Status */
56 	volatile u_char	*sci_dma_send;	/* w: Start DMA send data */
57 	volatile u_char	*sci_idata;	/* r: Input data */
58 	volatile u_char	*sci_trecv;	/* w: Start DMA receive, target */
59 	volatile u_char	*sci_iack;	/* r: Interrupt Acknowledge */
60 	volatile u_char	*sci_irecv;	/* w: Start DMA receive, initiator */
61 
62 	/* pseudo DMA transfer */
63 	int	(*dma_xfer_in)(struct sci_softc *, int, u_char *, int);
64 	/* pseudo DMA transfer */
65 	int	(*dma_xfer_out)(struct sci_softc *, int, u_char *, int);
66 	u_char	sc_flags;
67 	u_char	sc_lun;
68 	/* one for each target */
69 	struct syncpar {
70 	  u_char state;
71 	  u_char period, offset;
72 	} sc_sync[8];
73 	u_char	sc_slave;
74 	u_char	sc_scsi_addr;
75 	u_char	sc_stat[2];
76 	u_char	sc_msg[8];
77 };
78 
79 /* sc_flags */
80 #define	SCI_IO		0x80	/* DMA I/O in progress */
81 #define	SCI_ALIVE	0x01	/* controller initialized */
82 #define SCI_SELECTED	0x04	/* bus is in selected state. Needed for
83 				   correct abort procedure. */
84 
85 /* sync states */
86 #define SYNC_START	0	/* no sync handshake started */
87 #define SYNC_SENT	1	/* we sent sync request, no answer yet */
88 #define SYNC_DONE	2	/* target accepted our (or inferior) settings,
89 				   or it rejected the request and we stay async */
90 
91 #define	PHASE		0x07		/* mask for psns/pctl phase */
92 #define	DATA_OUT_PHASE	0x00
93 #define	DATA_IN_PHASE	0x01
94 #define	CMD_PHASE	0x02
95 #define	STATUS_PHASE	0x03
96 #define	BUS_FREE_PHASE	0x04
97 #define	ARB_SEL_PHASE	0x05	/* Fuji chip combines arbitration with sel. */
98 #define	MESG_OUT_PHASE	0x06
99 #define	MESG_IN_PHASE	0x07
100 
101 #define	MSG_CMD_COMPLETE	0x00
102 #define MSG_EXT_MESSAGE		0x01
103 #define	MSG_SAVE_DATA_PTR	0x02
104 #define	MSG_RESTORE_PTR		0x03
105 #define	MSG_DISCONNECT		0x04
106 #define	MSG_INIT_DETECT_ERROR	0x05
107 #define	MSG_ABORT		0x06
108 #define	MSG_REJECT		0x07
109 #define	MSG_NOOP		0x08
110 #define	MSG_PARITY_ERROR	0x09
111 #define	MSG_BUS_DEVICE_RESET	0x0C
112 #define	MSG_IDENTIFY		0x80
113 #define	MSG_IDENTIFY_DR		0xc0	/* (disconnect/reconnect allowed) */
114 #define	MSG_SYNC_REQ 		0x01
115 
116 
117 #define	STS_CHECKCOND	0x02	/* Check Condition (ie., read sense) */
118 #define	STS_CONDMET	0x04	/* Condition Met (ie., search worked) */
119 #define	STS_BUSY	0x08
120 #define	STS_INTERMED	0x10	/* Intermediate status sent */
121 #define	STS_EXT		0x80	/* Extended status valid */
122 
123 /*
124  * XXXX
125  */
126 struct scsi_fmt_cdb {
127 	int len;		/* cdb length (in bytes) */
128 	u_char cdb[28];		/* cdb to use on next read/write */
129 };
130 
131 struct buf;
132 struct scsipi_xfer;
133 
134 void sci_minphys(struct buf *);
135 void sci_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, void *);
136 void scireset(struct sci_softc *);
137 
138 #endif /* _SCIVAR_H_ */
139