1 /* $OpenBSD: dec_2100_a50.c,v 1.22 2014/05/08 20:46:49 miod Exp $ */
2 /* $NetBSD: dec_2100_a50.c,v 1.43 2000/05/22 20:13:31 thorpej Exp $ */
3
4 /*
5 * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
6 * All rights reserved.
7 *
8 * Author: Chris G. Demetriou
9 *
10 * Permission to use, copy, modify and distribute this software and
11 * its documentation is hereby granted, provided that both the copyright
12 * notice and this permission notice appear in all copies of the
13 * software, derivative works or modified versions, and any portions
14 * thereof, and that both notices appear in supporting documentation.
15 *
16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19 *
20 * Carnegie Mellon requests users of this software to return to
21 *
22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23 * School of Computer Science
24 * Carnegie Mellon University
25 * Pittsburgh PA 15213-3890
26 *
27 * any improvements or extensions that they make and grant Carnegie the
28 * rights to redistribute these changes.
29 */
30 /*
31 * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
32 */
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/device.h>
37 #include <sys/termios.h>
38 #include <dev/cons.h>
39 #include <sys/conf.h>
40
41 #include <machine/rpb.h>
42 #include <machine/autoconf.h>
43 #include <machine/bus.h>
44 #include <machine/cpuconf.h>
45 #include <machine/logout.h>
46
47 #include <dev/ic/comreg.h>
48 #include <dev/ic/comvar.h>
49
50 #include <dev/isa/isareg.h>
51 #include <dev/isa/isavar.h>
52 #include <dev/ic/i8042reg.h>
53 #include <dev/ic/pckbcvar.h>
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
56
57 #include <alpha/pci/apecsreg.h>
58 #include <alpha/pci/apecsvar.h>
59
60 #include <scsi/scsi_all.h>
61 #include <scsi/scsiconf.h>
62
63 #include "pckbd.h"
64
65 #ifndef CONSPEED
66 #define CONSPEED TTYDEF_SPEED
67 #endif
68 static int comcnrate = CONSPEED;
69
70 void dec_2100_a50_init(void);
71 static void dec_2100_a50_cons_init(void);
72 static void dec_2100_a50_device_register(struct device *, void *);
73
74 #ifndef SMALL_KERNEL
75 static void dec_2100_a50_mcheck_handler(unsigned long, struct trapframe *,
76 unsigned long, unsigned long);
77 static void dec_2100_a50_mcheck(unsigned long, unsigned long, unsigned long,
78 struct trapframe *);
79 #endif
80
81 const struct alpha_variation_table dec_2100_a50_variations[] = {
82 { SV_ST_AVANTI, "AlphaStation 400 4/233 (\"Avanti\")" },
83 { SV_ST_MUSTANG2_4_166, "AlphaStation 200 4/166 (\"Mustang II\")" },
84 { SV_ST_MUSTANG2_4_233, "AlphaStation 200 4/233 (\"Mustang II\")" },
85 { SV_ST_AVANTI_4_266, "AlphaStation 250 4/266" },
86 { SV_ST_MUSTANG2_4_100, "AlphaStation 200 4/100 (\"Mustang II\")" },
87 { SV_ST_AVANTI_4_233, "AlphaStation 255/233" },
88 { 0, NULL },
89 };
90
91 void
dec_2100_a50_init()92 dec_2100_a50_init()
93 {
94 u_int64_t variation;
95
96 platform.family = "AlphaStation 200/400 (\"Avanti\")";
97
98 if ((platform.model = alpha_dsr_sysname()) == NULL) {
99 variation = hwrpb->rpb_variation & SV_ST_MASK;
100 if (variation == SV_ST_AVANTI_XXX) {
101 /* XXX apparently the same? */
102 variation = SV_ST_AVANTI;
103 }
104 if ((platform.model = alpha_variation_name(variation,
105 dec_2100_a50_variations)) == NULL)
106 platform.model = alpha_unknown_sysname();
107 }
108
109 platform.iobus = "apecs";
110 platform.cons_init = dec_2100_a50_cons_init;
111 platform.device_register = dec_2100_a50_device_register;
112 #ifndef SMALL_KERNEL
113 platform.mcheck_handler = dec_2100_a50_mcheck_handler;
114 #endif
115 }
116
117 static void
dec_2100_a50_cons_init()118 dec_2100_a50_cons_init()
119 {
120 struct ctb *ctb;
121 struct apecs_config *acp;
122 extern struct apecs_config apecs_configuration;
123
124 acp = &apecs_configuration;
125 apecs_init(acp, 0);
126
127 ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
128
129 switch (ctb->ctb_term_type) {
130 case CTB_PRINTERPORT:
131 /* serial console ... */
132 /* XXX */
133 {
134 /*
135 * Delay to allow PROM putchars to complete.
136 * FIFO depth * character time,
137 * character time = (1000000 / (defaultrate / 10))
138 */
139 DELAY(160000000 / comcnrate);
140
141 if(comcnattach(&acp->ac_iot, 0x3f8, comcnrate,
142 COM_FREQ,
143 (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8))
144 panic("can't init serial console");
145
146 break;
147 }
148
149 case CTB_GRAPHICS:
150 #if NPCKBD > 0
151 /* display console ... */
152 /* XXX */
153 (void) pckbc_cnattach(&acp->ac_iot, IO_KBD, KBCMDP, 0);
154
155 if (CTB_TURBOSLOT_TYPE(ctb->ctb_turboslot) ==
156 CTB_TURBOSLOT_TYPE_ISA)
157 isa_display_console(&acp->ac_iot, &acp->ac_memt);
158 else
159 pci_display_console(&acp->ac_iot, &acp->ac_memt,
160 &acp->ac_pc, CTB_TURBOSLOT_BUS(ctb->ctb_turboslot),
161 CTB_TURBOSLOT_SLOT(ctb->ctb_turboslot), 0);
162 #else
163 panic("not configured to use display && keyboard console");
164 #endif
165 break;
166
167 default:
168 printf("ctb->ctb_term_type = 0x%lx\n",
169 (unsigned long)ctb->ctb_term_type);
170 printf("ctb->ctb_turboslot = 0x%lx\n",
171 (unsigned long)ctb->ctb_turboslot);
172
173 panic("consinit: unknown console type %lu",
174 (unsigned long)ctb->ctb_term_type);
175 }
176 }
177
178 static void
dec_2100_a50_device_register(dev,aux)179 dec_2100_a50_device_register(dev, aux)
180 struct device *dev;
181 void *aux;
182 {
183 static int found, initted, diskboot, netboot;
184 static struct device *pcidev, *ctrlrdev;
185 struct bootdev_data *b = bootdev_data;
186 struct device *parent = dev->dv_parent;
187 struct cfdata *cf = dev->dv_cfdata;
188 struct cfdriver *cd = cf->cf_driver;
189
190 if (found)
191 return;
192
193 if (!initted) {
194 diskboot = (strncasecmp(b->protocol, "SCSI", 4) == 0);
195 netboot = (strncasecmp(b->protocol, "BOOTP", 5) == 0) ||
196 (strncasecmp(b->protocol, "MOP", 3) == 0);
197 #if 0
198 printf("diskboot = %d, netboot = %d\n", diskboot, netboot);
199 #endif
200 initted =1;
201 }
202
203 if (pcidev == NULL) {
204 if (strcmp(cd->cd_name, "pci"))
205 return;
206 else {
207 struct pcibus_attach_args *pba = aux;
208
209 if ((b->slot / 1000) != pba->pba_bus)
210 return;
211
212 pcidev = dev;
213 #if 0
214 printf("\npcidev = %s\n", dev->dv_xname);
215 #endif
216 return;
217 }
218 }
219
220 if (ctrlrdev == NULL) {
221 if (parent != pcidev)
222 return;
223 else {
224 struct pci_attach_args *pa = aux;
225 int slot;
226
227 slot = pa->pa_bus * 1000 + pa->pa_function * 100 +
228 pa->pa_device;
229 if (b->slot != slot)
230 return;
231
232 if (netboot) {
233 booted_device = dev;
234 #if 0
235 printf("\nbooted_device = %s\n", dev->dv_xname);
236 #endif
237 found = 1;
238 } else {
239 ctrlrdev = dev;
240 #if 0
241 printf("\nctrlrdev = %s\n", dev->dv_xname);
242 #endif
243 }
244 return;
245 }
246 }
247
248 if (!diskboot)
249 return;
250
251 if (!strcmp(cd->cd_name, "sd") || !strcmp(cd->cd_name, "st") ||
252 !strcmp(cd->cd_name, "cd")) {
253 struct scsi_attach_args *sa = aux;
254 struct scsi_link *periph = sa->sa_sc_link;
255 int unit;
256
257 if (parent->dv_parent != ctrlrdev)
258 return;
259
260 unit = periph->target * 100 + periph->lun;
261 if (b->unit != unit)
262 return;
263
264 /* we've found it! */
265 booted_device = dev;
266 #if 0
267 printf("\nbooted_device = %s\n", dev->dv_xname);
268 #endif
269 found = 1;
270 }
271 }
272
273 #ifndef SMALL_KERNEL
274 static void
dec_2100_a50_mcheck(mces,type,logout,framep)275 dec_2100_a50_mcheck(mces, type, logout, framep)
276 unsigned long mces;
277 unsigned long type;
278 unsigned long logout;
279 struct trapframe *framep;
280 {
281 struct mchkinfo *mcp;
282 static const char *fmt1 = " %-25s = 0x%016lx\n";
283 int i, sysaddr;
284 mc_hdr_avanti *hdr;
285 mc_uc_avanti *ptr;
286
287 /*
288 * If we expected a machine check, just go handle it in common code.
289 */
290 mcp = &curcpu()->ci_mcinfo;
291 if (mcp->mc_expected) {
292 machine_check(mces, framep, type, logout);
293 return;
294 }
295
296 hdr = (mc_hdr_avanti *) logout;
297 ptr = (mc_uc_avanti *) (logout + sizeof (*hdr));
298
299 printf(" Processor Machine Check (%lx), Code 0x%x\n",
300 type, hdr->mcheck_code);
301 printf("CPU state:\n");
302 /* Print PAL fields */
303 for (i = 0; i < 32; i += 2) {
304 printf("\tPAL temp[%d-%d]\t\t= 0x%16lx 0x%16lx\n", i, i+1,
305 (unsigned long)ptr->paltemp[i],
306 (unsigned long)ptr->paltemp[i+1]);
307 }
308 printf(fmt1, "Excepting Instruction Addr", ptr->exc_addr);
309 printf(fmt1, "Summary of arithmetic traps", ptr->exc_sum);
310 printf(fmt1, "Exception mask", ptr->exc_mask);
311 printf(fmt1, "ICCSR", ptr->iccsr);
312 printf(fmt1, "Base address for PALcode", ptr->pal_base);
313 printf(fmt1, "HIER", ptr->hier);
314 printf(fmt1, "HIRR", ptr->hirr);
315 printf(fmt1, "MM_CSR", ptr->mm_csr);
316 printf(fmt1, "DC_STAT", ptr->dc_stat);
317 printf(fmt1, "DC_ADDR", ptr->dc_addr);
318 printf(fmt1, "ABOX_CTL", ptr->abox_ctl);
319 printf(fmt1, "Bus Interface Unit status", ptr->biu_stat);
320 printf(fmt1, "Bus Interface Unit addr", ptr->biu_addr);
321 printf(fmt1, "Bus Interface Unit control", ptr->biu_ctl);
322 printf(fmt1, "Fill Syndrome", ptr->fill_syndrome);
323 printf(fmt1, "Fill Address", ptr->fill_addr);
324 printf(fmt1, "Effective VA", ptr->va);
325 printf(fmt1, "BC_TAG", ptr->bc_tag);
326
327 printf("\nCache and Memory Controller (21071-CA) state:\n");
328 printf(fmt1, "COMA_GCR", ptr->coma_gcr);
329 printf(fmt1, "COMA_EDSR", ptr->coma_edsr);
330 printf(fmt1, "COMA_TER", ptr->coma_ter);
331 printf(fmt1, "COMA_ELAR", ptr->coma_elar);
332 printf(fmt1, "COMA_EHAR", ptr->coma_ehar);
333 printf(fmt1, "COMA_LDLR", ptr->coma_ldlr);
334 printf(fmt1, "COMA_LDHR", ptr->coma_ldhr);
335 printf(fmt1, "COMA_BASE0", ptr->coma_base0);
336 printf(fmt1, "COMA_BASE1", ptr->coma_base1);
337 printf(fmt1, "COMA_BASE2", ptr->coma_base2);
338 printf(fmt1, "COMA_CNFG0", ptr->coma_cnfg0);
339 printf(fmt1, "COMA_CNFG1", ptr->coma_cnfg1);
340 printf(fmt1, "COMA_CNFG2", ptr->coma_cnfg2);
341
342 printf("\nPCI bridge (21071-DA) state:\n");
343
344 printf(fmt1, "EPIC Diag. control/status", ptr->epic_dcsr);
345 printf(fmt1, "EPIC_PEAR", ptr->epic_pear);
346 printf(fmt1, "EPIC_SEAR", ptr->epic_sear);
347 printf(fmt1, "EPIC_TBR1", ptr->epic_tbr1);
348 printf(fmt1, "EPIC_TBR2", ptr->epic_tbr2);
349 printf(fmt1, "EPIC_PBR1", ptr->epic_pbr1);
350 printf(fmt1, "EPIC_PBR2", ptr->epic_pbr2);
351 printf(fmt1, "EPIC_PMR1", ptr->epic_pmr1);
352 printf(fmt1, "EPIC_PMR2", ptr->epic_pmr2);
353 printf(fmt1, "EPIC_HARX1", ptr->epic_harx1);
354 printf(fmt1, "EPIC_HARX2", ptr->epic_harx2);
355 printf(fmt1, "EPIC_PMLT", ptr->epic_pmlt);
356 printf(fmt1, "EPIC_TAG0", ptr->epic_tag0);
357 printf(fmt1, "EPIC_TAG1", ptr->epic_tag1);
358 printf(fmt1, "EPIC_TAG2", ptr->epic_tag2);
359 printf(fmt1, "EPIC_TAG3", ptr->epic_tag3);
360 printf(fmt1, "EPIC_TAG4", ptr->epic_tag4);
361 printf(fmt1, "EPIC_TAG5", ptr->epic_tag5);
362 printf(fmt1, "EPIC_TAG6", ptr->epic_tag6);
363 printf(fmt1, "EPIC_TAG7", ptr->epic_tag7);
364 printf(fmt1, "EPIC_DATA0", ptr->epic_data0);
365 printf(fmt1, "EPIC_DATA1", ptr->epic_data1);
366 printf(fmt1, "EPIC_DATA2", ptr->epic_data2);
367 printf(fmt1, "EPIC_DATA3", ptr->epic_data3);
368 printf(fmt1, "EPIC_DATA4", ptr->epic_data4);
369 printf(fmt1, "EPIC_DATA5", ptr->epic_data5);
370 printf(fmt1, "EPIC_DATA6", ptr->epic_data6);
371 printf(fmt1, "EPIC_DATA7", ptr->epic_data7);
372
373 printf("\n");
374
375 if (type == ALPHA_SYS_MCHECK) {
376 printf("\nPCI bridge fault\n");
377 switch(hdr->mcheck_code) {
378 case AVANTI_RETRY_TIMEOUT:
379 printf("\tRetry timeout error accessing 0x%08lx.\n",
380 (unsigned long)ptr->epic_pear & 0xffffffff);
381 break;
382
383 case AVANTI_DMA_DATA_PARITY:
384 printf("\tDMA data parity error accessing 0x%08lx.\n",
385 (unsigned long)ptr->epic_pear & 0xffffffff);
386 break;
387
388 case AVANTI_IO_PARITY:
389 printf("\tI/O parity error at 0x%08lx during PCI cycle 0x%0lx.\n",
390 (unsigned long)ptr->epic_pear & 0xffffffff,
391 (unsigned long)(ptr->epic_dcsr >> 18) & 0xf);
392 break;
393
394 case AVANTI_TARGET_ABORT:
395 printf("\tPCI target abort at 0x%08lx during PCI cycle 0x%0lx.\n",
396 (unsigned long)ptr->epic_pear & 0xffffffff,
397 (unsigned long)(ptr->epic_dcsr >> 18) & 0xf);
398 break;
399
400 case AVANTI_NO_DEVICE:
401 printf("\tNo device responded at 0x%08lx during PCI cycle 0x%0lx\n.",
402 (unsigned long)ptr->epic_pear & 0xffffffff,
403 (unsigned long)(ptr->epic_dcsr >> 18) & 0xf);
404 break;
405
406 case AVANTI_CORRRECTABLE_MEMORY:
407 printf("\tCorrectable memory error reported.\n"
408 "\tWARNING ECC not implemented on this system!\n"
409 "\tError is incorrect.\n");
410 break;
411
412 case AVANTI_UNCORRECTABLE_PCI_MEMORY:
413 printf("\tUncorrectable memory error at %016lx reported "
414 "during DMA read.\n",
415 (unsigned long)(ptr->epic_sear & 0xfffffff0) << 2);
416 break;
417
418 case AVANTI_INVALID_PT_LOOKUP:
419 printf("\tInvalid page table lookup during scatter/gather.\n" );
420 if (ptr->epic_dcsr & 0xf20)
421 printf("\tAddress lost.\n");
422 else
423 printf("\tBus address to 0x%08lx, PCI cycle 0x%0lx\n",
424 (unsigned long)ptr->epic_pear & 0xffffffff,
425 (unsigned long)(ptr->epic_dcsr >> 18) & 0xf);
426 break;
427
428 case AVANTI_MEMORY:
429 printf("\tMemory error at %016lx, ",
430 (unsigned long)(ptr->epic_sear & 0xfffffff0) << 2);
431 sysaddr = (ptr->epic_sear & 0xffffffff) >> 21;
432 if (sysaddr >= ((ptr->coma_base0 >> 5) & 0x7ff) &&
433 sysaddr < (((ptr->coma_base0 >> 5) & 0x7ff) +
434 (1 << (7 - (ptr->coma_cnfg0 >> 1)))))
435 printf("SIMM bank 0\n");
436 else if (sysaddr >= ((ptr->coma_base1 >> 5) & 0x7ff) &&
437 sysaddr < (((ptr->coma_base1 >> 5) & 0x7ff) +
438 (1 << (7 - (ptr->coma_cnfg1 >> 1)))))
439 printf("SIMM bank 1\n");
440 else if (sysaddr >= ((ptr->coma_base2 >> 5) & 0x7ff) &&
441 sysaddr < (((ptr->coma_base2 >> 5) & 0x7ff) +
442 (1 << (7 - (ptr->coma_cnfg2 >> 1)))))
443 printf("SIMM bank 2\n");
444 else
445 printf("invalid memory bank?\n");
446 break;
447
448 case AVANTI_BCACHE_TAG_ADDR_PARITY:
449 printf("\tBcache tag address parity error, caused by ");
450 if (ptr->coma_edsr & 0x20)
451 printf("victim write\n");
452 else if (ptr->coma_edsr & 0x10)
453 printf("DMA. ioCmd<2:0> = %0lx\n",
454 (unsigned long)(ptr->coma_edsr >> 6) & 7);
455 else
456 printf("CPU. cpuCReq<2:0> = %0lx\n",
457 (unsigned long)(ptr->coma_edsr >> 6) & 7);
458 break;
459
460 case AVANTI_BCACHE_TAG_CTRL_PARITY:
461 printf("\tBcache tag control parity error, caused by ");
462 if (ptr->coma_edsr & 0x20)
463 printf("victim write\n");
464 else if (ptr->coma_edsr & 0x10)
465 printf("DMA. ioCmd<2:0> = %0lx\n",
466 (unsigned long)(ptr->coma_edsr >> 6) & 7);
467 else
468 printf("CPU. cpuCReq<2:0> = %0lx\n",
469 (unsigned long)(ptr->coma_edsr >> 6) & 7);
470 break;
471
472 case AVANTI_NONEXISTENT_MEMORY:
473 printf("\tNonexistent memory error, caused by ");
474 if (ptr->coma_edsr & 0x20)
475 printf("victim write\n");
476 else if (ptr->coma_edsr & 0x10)
477 printf("DMA. ioCmd<2:0> = %0lx\n",
478 (unsigned long)(ptr->coma_edsr >> 6) & 7);
479 else
480 printf("CPU. cpuCReq<2:0> = %0lx\n",
481 (unsigned long)(ptr->coma_edsr >> 6) & 7);
482 break;
483
484 case AVANTI_IO_BUS:
485 printf("\tI/O bus error at %08lx during PCI cycle %0lx\n",
486 (unsigned long)ptr->epic_pear & 0xffffffff,
487 (unsigned long)(ptr->epic_dcsr >> 18) & 0xf);
488 break;
489
490 case AVANTI_BCACHE_TAG_PARITY:
491 printf("\tBcache tag address parity error.\n"
492 "\tcReg_h cycle %0lx, address<7:0> 0x%02lx\n",
493 (unsigned long)(ptr->biu_stat >> 4) & 7,
494 (unsigned long)ptr->biu_addr & 0xff);
495 break;
496
497 case AVANTI_BCACHE_TAG_CTRL_PARITY2:
498 printf("\tBcache tag control parity error.\n"
499 "\tcReg_h cycle %0lx, address<7:0> 0x%02lx\n",
500 (unsigned long)(ptr->biu_stat >> 4) & 7,
501 (unsigned long)ptr->biu_addr & 0xff);
502 break;
503
504 }
505 } else { /* ALPHA_PROC_MCHECK */
506 printf("\nProcessor fault\n");
507 switch(hdr->mcheck_code) {
508 case AVANTI_HARD_ERROR:
509 printf("\tHard error cycle.\n");
510 break;
511
512 case AVANTI_CORRECTABLE_ECC:
513 printf("\tCorrectable ECC error.\n"
514 "\tWARNING ECC not implemented on this system!\n"
515 "\tError is incorrect.\n");
516 break;
517
518 case AVANTI_NONCORRECTABLE_ECC:
519 printf("\tNoncorrectable ECC error.\n"
520 "\tWARNING ECC not implemented on this system!\n"
521 "\tError is incorrect.\n");
522 break;
523
524 case AVANTI_UNKNOWN_ERROR:
525 printf("\tUnknown error.\n");
526 break;
527
528 case AVANTI_SOFT_ERROR:
529 printf("\tSoft error cycle.\n");
530 break;
531
532 case AVANTI_BUGCHECK:
533 printf("\tBugcheck.\n");
534 break;
535
536 case AVANTI_OS_BUGCHECK:
537 printf("\tOS Bugcheck.\n");
538 break;
539
540 case AVANTI_DCACHE_FILL_PARITY:
541 printf("\tPrimary Dcache data fill parity error.\n"
542 "\tDcache Quadword %lx, address %08lx\n",
543 (unsigned long)(ptr->biu_stat >> 12) & 0x3,
544 (unsigned long)(ptr->fill_addr >> 8) & 0x7f);
545 break;
546
547 case AVANTI_ICACHE_FILL_PARITY:
548 printf("\tPrimary Icache data fill parity error.\n"
549 "\tDcache Quadword %lx, address %08lx\n",
550 (unsigned long)(ptr->biu_stat >> 12) & 0x3,
551 (unsigned long)(ptr->fill_addr >> 8) & 0x7f);
552 break;
553 }
554 }
555
556 /*
557 * Now that we've printed all sorts of useful information
558 * and have decided that we really can't do any more to
559 * respond to the error, go on to the common code for
560 * final disposition. Usually this means that we die.
561 */
562 /*
563 * XXX: HANDLE PCI ERRORS HERE?
564 */
565 machine_check(mces, framep, type, logout);
566 }
567
568 static void
dec_2100_a50_mcheck_handler(mces,framep,vector,param)569 dec_2100_a50_mcheck_handler(mces, framep, vector, param)
570 unsigned long mces;
571 struct trapframe *framep;
572 unsigned long vector;
573 unsigned long param;
574 {
575 switch (vector) {
576 case ALPHA_SYS_MCHECK:
577 case ALPHA_PROC_MCHECK:
578 dec_2100_a50_mcheck(mces, vector, param, framep);
579 break;
580 default:
581 printf("2100_A50_MCHECK: unknown check vector 0x%lx\n", vector);
582 machine_check(mces, framep, vector, param);
583 break;
584 }
585 }
586 #endif /* !SMALL_KERNEL */
587