1 /* $NetBSD: i80321_space.c,v 1.18 2018/11/21 19:03:18 macallan Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * bus_space functions for i80321 I/O Processor.
40 */
41
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: i80321_space.c,v 1.18 2018/11/21 19:03:18 macallan Exp $");
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47
48 #include <uvm/uvm_extern.h>
49
50 #include <sys/bus.h>
51
52 #include <arm/xscale/i80321reg.h>
53 #include <arm/xscale/i80321var.h>
54
55 #include "opt_i80321.h"
56
57 /* Prototypes for all the bus_space structure functions */
58 bs_protos(i80321);
59 bs_protos(i80321_io);
60 bs_protos(i80321_mem);
61 bs_protos(generic);
62 bs_protos(generic_armv4);
63 bs_protos(bs_notimpl);
64
65 /*
66 * Template bus_space -- copied, and the bits that are NULL are
67 * filled in.
68 */
69 const struct bus_space i80321_bs_tag_template = {
70 /* cookie */
71 .bs_cookie = (void *) 0,
72
73 /* mapping/unmapping */
74 .bs_map = NULL,
75 .bs_unmap = NULL,
76 .bs_subregion = i80321_bs_subregion,
77
78 /* allocation/deallocation */
79 .bs_alloc = NULL,
80 .bs_free = NULL,
81
82 /* get kernel virtual address */
83 .bs_vaddr = i80321_bs_vaddr,
84
85 /* mmap */
86 .bs_mmap = i80321_bs_mmap,
87
88 /* barrier */
89 .bs_barrier = i80321_bs_barrier,
90
91 /* read (single) */
92 .bs_r_1 = generic_bs_r_1,
93 .bs_r_2 = generic_armv4_bs_r_2,
94 .bs_r_4 = generic_bs_r_4,
95 .bs_r_8 = bs_notimpl_bs_r_8,
96
97 #ifdef __BUS_SPACE_HAS_STREAM_METHODS
98 /* read (single, stream) */
99 .bs_r_1_s = generic_bs_r_1,
100 .bs_r_2_s = generic_armv4_bs_r_2,
101 .bs_r_4_s = generic_bs_r_4,
102 .bs_r_8_s = bs_notimpl_bs_r_8,
103 #endif
104
105 /* read multiple */
106 .bs_rm_1 = generic_bs_rm_1,
107 .bs_rm_2 = generic_armv4_bs_rm_2,
108 .bs_rm_4 = generic_bs_rm_4,
109 .bs_rm_8 = bs_notimpl_bs_rm_8,
110
111 #ifdef __BUS_SPACE_HAS_STREAM_METHODS
112 /* read multiple, stream */
113 .bs_rm_1_s = generic_bs_rm_1,
114 .bs_rm_2_s = generic_armv4_bs_rm_2,
115 .bs_rm_4_s = generic_bs_rm_4,
116 .bs_rm_8_s = bs_notimpl_bs_rm_8,
117 #endif
118
119 /* read region */
120 .bs_rr_1 = generic_bs_rr_1,
121 .bs_rr_2 = generic_armv4_bs_rr_2,
122 .bs_rr_4 = generic_bs_rr_4,
123 .bs_rr_8 = bs_notimpl_bs_rr_8,
124
125 #ifdef __BUS_SPACE_HAS_STREAM_METHODS
126 /* read region, stream */
127 .bs_rr_1_s = generic_bs_rr_1,
128 .bs_rr_2_s = generic_armv4_bs_rr_2,
129 .bs_rr_4_s = generic_bs_rr_4,
130 .bs_rr_8_s = bs_notimpl_bs_rr_8,
131 #endif
132
133 /* write (single) */
134 .bs_w_1 = generic_bs_w_1,
135 .bs_w_2 = generic_armv4_bs_w_2,
136 .bs_w_4 = generic_bs_w_4,
137 .bs_w_8 = bs_notimpl_bs_w_8,
138
139 #ifdef __BUS_SPACE_HAS_STREAM_METHODS
140 /* write (single, stream) */
141 .bs_w_1_s = generic_bs_w_1,
142 .bs_w_2_s = generic_armv4_bs_w_2,
143 .bs_w_4_s = generic_bs_w_4,
144 .bs_w_8_s = bs_notimpl_bs_w_8,
145 #endif
146
147 /* write multiple */
148 .bs_wm_1 = generic_bs_wm_1,
149 .bs_wm_2 = generic_armv4_bs_wm_2,
150 .bs_wm_4 = generic_bs_wm_4,
151 .bs_wm_8 = bs_notimpl_bs_wm_8,
152
153 #ifdef __BUS_SPACE_HAS_STREAM_METHODS
154 /* write multiple, stream */
155 .bs_wm_1_s = generic_bs_wm_1,
156 .bs_wm_2_s = generic_armv4_bs_wm_2,
157 .bs_wm_4_s = generic_bs_wm_4,
158 .bs_wm_8_s = bs_notimpl_bs_wm_8,
159 #endif
160
161 /* write region */
162 .bs_wr_1 = generic_bs_wr_1,
163 .bs_wr_2 = generic_armv4_bs_wr_2,
164 .bs_wr_4 = generic_bs_wr_4,
165 .bs_wr_8 = bs_notimpl_bs_wr_8,
166
167 #ifdef __BUS_SPACE_HAS_STREAM_METHODS
168 /* write region, stream */
169 .bs_wr_1_s = generic_bs_wr_1,
170 .bs_wr_2_s = generic_armv4_bs_wr_2,
171 .bs_wr_4_s = generic_bs_wr_4,
172 .bs_wr_8_s = bs_notimpl_bs_wr_8,
173 #endif
174
175 /* set multiple */
176 .bs_sm_1 = bs_notimpl_bs_sm_1,
177 .bs_sm_2 = bs_notimpl_bs_sm_2,
178 .bs_sm_4 = bs_notimpl_bs_sm_4,
179 .bs_sm_8 = bs_notimpl_bs_sm_8,
180
181 /* set region */
182 .bs_sr_1 = bs_notimpl_bs_sr_1,
183 .bs_sr_2 = generic_armv4_bs_sr_2,
184 .bs_sr_4 = generic_bs_sr_4,
185 .bs_sr_8 = bs_notimpl_bs_sr_8,
186
187 /* copy */
188 .bs_c_1 = bs_notimpl_bs_c_1,
189 .bs_c_2 = generic_armv4_bs_c_2,
190 .bs_c_4 = bs_notimpl_bs_c_4,
191 .bs_c_8 = bs_notimpl_bs_c_8,
192 };
193
194 void
i80321_bs_init(bus_space_tag_t bs,void * cookie)195 i80321_bs_init(bus_space_tag_t bs, void *cookie)
196 {
197
198 *bs = i80321_bs_tag_template;
199 bs->bs_cookie = cookie;
200 }
201
202 void
i80321_io_bs_init(bus_space_tag_t bs,void * cookie)203 i80321_io_bs_init(bus_space_tag_t bs, void *cookie)
204 {
205
206 *bs = i80321_bs_tag_template;
207 bs->bs_cookie = cookie;
208
209 bs->bs_map = i80321_io_bs_map;
210 bs->bs_unmap = i80321_io_bs_unmap;
211 bs->bs_alloc = i80321_io_bs_alloc;
212 bs->bs_free = i80321_io_bs_free;
213
214 bs->bs_vaddr = i80321_io_bs_vaddr;
215 bs->bs_mmap = i80321_io_bs_mmap;
216 }
217
218 void
i80321_mem_bs_init(bus_space_tag_t bs,void * cookie)219 i80321_mem_bs_init(bus_space_tag_t bs, void *cookie)
220 {
221
222 *bs = i80321_bs_tag_template;
223 bs->bs_cookie = cookie;
224
225 bs->bs_map = i80321_mem_bs_map;
226 bs->bs_unmap = i80321_mem_bs_unmap;
227 bs->bs_alloc = i80321_mem_bs_alloc;
228 bs->bs_free = i80321_mem_bs_free;
229 bs->bs_mmap = i80321_mem_bs_mmap;
230 }
231
232 /* *** Routines shared by i80321, PCI IO, and PCI MEM. *** */
233
234 int
i80321_bs_subregion(void * t,bus_space_handle_t bsh,bus_size_t offset,bus_size_t size,bus_space_handle_t * nbshp)235 i80321_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
236 bus_size_t size, bus_space_handle_t *nbshp)
237 {
238
239 *nbshp = bsh + offset;
240 return (0);
241 }
242
243 void
i80321_bs_barrier(void * t,bus_space_handle_t bsh,bus_size_t offset,bus_size_t len,int flags)244 i80321_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
245 bus_size_t len, int flags)
246 {
247
248 /* Nothing to do. */
249 }
250
251 void *
i80321_bs_vaddr(void * t,bus_space_handle_t bsh)252 i80321_bs_vaddr(void *t, bus_space_handle_t bsh)
253 {
254
255 return ((void *)bsh);
256 }
257
258 paddr_t
i80321_bs_mmap(void * t,bus_addr_t addr,off_t off,int prot,int flags)259 i80321_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags)
260 {
261
262 /* Not supported. */
263 return (-1);
264 }
265
266 /* *** Routines for PCI IO. *** */
267
268 int
i80321_io_bs_map(void * t,bus_addr_t bpa,bus_size_t size,int flags,bus_space_handle_t * bshp)269 i80321_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
270 bus_space_handle_t *bshp)
271 {
272 struct i80321_softc *sc = t;
273 vaddr_t winvaddr;
274 uint32_t busbase;
275
276 if (bpa >= sc->sc_ioout_xlate &&
277 bpa < (sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE)) {
278 busbase = sc->sc_ioout_xlate;
279 winvaddr = sc->sc_iow_vaddr;
280 } else
281 return (EINVAL);
282
283 if ((bpa + size) >= (busbase + VERDE_OUT_XLATE_IO_WIN_SIZE))
284 return (EINVAL);
285
286 /*
287 * Found the window -- PCI I/O space is mapped at a fixed
288 * virtual address by board-specific code. Translate the
289 * bus address to the virtual address.
290 */
291 *bshp = winvaddr + (bpa - busbase);
292
293 return (0);
294 }
295
296 paddr_t
i80321_io_bs_mmap(void * t,bus_addr_t addr,off_t off,int prot,int flags)297 i80321_io_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags)
298 {
299 struct i80321_softc *sc = t;
300 paddr_t bpa = addr + off, winpaddr, busbase;
301
302 if (bpa >= sc->sc_ioout_xlate &&
303 bpa < (sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE)) {
304 busbase = sc->sc_ioout_xlate;
305 winpaddr = VERDE_OUT_XLATE_IO_WIN0_BASE;
306 } else
307 return (-1);
308
309 return (arm_btop(winpaddr + (bpa - busbase)));
310 }
311
312 void
i80321_io_bs_unmap(void * t,bus_space_handle_t bsh,bus_size_t size)313 i80321_io_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
314 {
315
316 /* Nothing to do. */
317 }
318
319 int
i80321_io_bs_alloc(void * t,bus_addr_t rstart,bus_addr_t rend,bus_size_t size,bus_size_t alignment,bus_size_t boundary,int flags,bus_addr_t * bpap,bus_space_handle_t * bshp)320 i80321_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
321 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
322 bus_addr_t *bpap, bus_space_handle_t *bshp)
323 {
324
325 panic("i80321_io_bs_alloc(): not implemented");
326 }
327
328 void
i80321_io_bs_free(void * t,bus_space_handle_t bsh,bus_size_t size)329 i80321_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
330 {
331
332 panic("i80321_io_bs_free(): not implemented");
333 }
334
335 void *
i80321_io_bs_vaddr(void * t,bus_space_handle_t bsh)336 i80321_io_bs_vaddr(void *t, bus_space_handle_t bsh)
337 {
338
339 /* Not supported. */
340 return (NULL);
341 }
342
343 /* *** Routines for PCI MEM. *** */
344
345 int
i80321_mem_bs_map(void * t,bus_addr_t bpa,bus_size_t size,int flags,bus_space_handle_t * bshp)346 i80321_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
347 bus_space_handle_t *bshp)
348 {
349
350 #ifndef I80321_USE_DIRECT_WIN
351 struct i80321_softc *sc = t;
352 #endif
353 vaddr_t va;
354 uint32_t busbase;
355 paddr_t pa, endpa, physbase;
356
357 #ifdef I80321_USE_DIRECT_WIN
358 if (
359 #if VERDE_OUT_DIRECT_WIN_BASE != 0
360 bpa >= (VERDE_OUT_DIRECT_WIN_BASE) &&
361 #endif
362 bpa < (VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SIZE)) {
363 busbase = VERDE_OUT_DIRECT_WIN_BASE;
364 physbase = VERDE_OUT_DIRECT_WIN_BASE;
365 } else
366 return (EINVAL);
367 if ((bpa + size) >= (VERDE_OUT_DIRECT_WIN_BASE +
368 VERDE_OUT_DIRECT_WIN_SIZE))
369 return (EINVAL);
370 #else
371 if (bpa >= sc->sc_owin[0].owin_xlate_lo &&
372 bpa < (sc->sc_owin[0].owin_xlate_lo +
373 VERDE_OUT_XLATE_MEM_WIN_SIZE)) {
374 busbase = sc->sc_owin[0].owin_xlate_lo;
375 physbase = sc->sc_iwin[1].iwin_xlate;
376 } else
377 return (EINVAL);
378
379 if ((bpa + size) >= (busbase + VERDE_OUT_XLATE_MEM_WIN_SIZE))
380 return (EINVAL);
381 #endif
382
383 /*
384 * Found the window -- PCI MEM space is now mapped by allocating
385 * some kernel VA space and mapping the pages with pmap_enter().
386 * pmap_enter() will map unmanaged pages as non-cacheable.
387 */
388 pa = trunc_page((bpa - busbase) + physbase);
389 endpa = round_page(((bpa - busbase) + physbase) + size);
390
391 va = uvm_km_alloc(kernel_map, endpa - pa, 0,
392 UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
393 if (va == 0)
394 return (ENOMEM);
395
396 *bshp = va + (bpa & PAGE_MASK);
397
398 for (; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
399 pmap_enter(pmap_kernel(), va, pa,
400 VM_PROT_READ | VM_PROT_WRITE,
401 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED |
402 ((flags & BUS_SPACE_MAP_PREFETCHABLE) ?
403 ARM_MMAP_WRITECOMBINE : 0));
404 }
405 pmap_update(pmap_kernel());
406
407 return (0);
408 }
409
410 void
i80321_mem_bs_unmap(void * t,bus_space_handle_t bsh,bus_size_t size)411 i80321_mem_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
412 {
413 vaddr_t va, endva;
414
415 va = trunc_page(bsh);
416 endva = round_page(bsh + size);
417
418 pmap_remove(pmap_kernel(), va, endva - va);
419 pmap_update(pmap_kernel());
420
421 /* Free the kernel virtual mapping. */
422 uvm_km_free(kernel_map, va, endva - va, UVM_KMF_VAONLY);
423 }
424
425 int
i80321_mem_bs_alloc(void * t,bus_addr_t rstart,bus_addr_t rend,bus_size_t size,bus_size_t alignment,bus_size_t boundary,int flags,bus_addr_t * bpap,bus_space_handle_t * bshp)426 i80321_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
427 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
428 bus_addr_t *bpap, bus_space_handle_t *bshp)
429 {
430
431 panic("i80321_mem_bs_alloc(): not implemented");
432 }
433
434 void
i80321_mem_bs_free(void * t,bus_space_handle_t bsh,bus_size_t size)435 i80321_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
436 {
437
438 panic("i80321_mem_bs_free(): not implemented");
439 }
440
441 paddr_t
i80321_mem_bs_mmap(void * t,bus_addr_t addr,off_t off,int prot,int flags)442 i80321_mem_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags)
443 {
444 #ifndef I80321_USE_DIRECT_WIN
445 struct i80321_softc *sc = t;
446 #endif
447 uint32_t busbase;
448 paddr_t pa, physbase, bpa = addr + off, pflags = 0;
449
450 #ifdef I80321_USE_DIRECT_WIN
451 if (
452 #if VERDE_OUT_DIRECT_WIN_BASE != 0
453 bpa >= (VERDE_OUT_DIRECT_WIN_BASE) &&
454 #endif
455 bpa < (VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SIZE)) {
456 busbase = VERDE_OUT_DIRECT_WIN_BASE;
457 physbase = VERDE_OUT_DIRECT_WIN_BASE;
458 } else
459 return (-1);
460 #else
461 if (bpa >= sc->sc_owin[0].owin_xlate_lo &&
462 bpa < (sc->sc_owin[0].owin_xlate_lo +
463 VERDE_OUT_XLATE_MEM_WIN_SIZE)) {
464 busbase = sc->sc_owin[0].owin_xlate_lo;
465 physbase = sc->sc_iwin[1].iwin_xlate;
466 } else
467 return (-1);
468 #endif
469
470 pa = trunc_page((bpa - busbase) + physbase);
471 if (flags & BUS_SPACE_MAP_PREFETCHABLE) {
472 pflags = ARM_MMAP_WRITECOMBINE;
473 }
474 return (arm_btop(pa) | pflags);
475 }
476