1 /* $OpenBSD: apic.c,v 1.19 2018/05/14 13:54:39 kettenis Exp $ */
2
3 /*
4 * Copyright (c) 2005 Michael Shalayeff
5 * Copyright (c) 2007 Mark Kettenis
6 * All rights reserved.
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
17 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
18 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
19
20 #include <sys/param.h>
21 #include <sys/systm.h>
22 #include <sys/device.h>
23 #include <sys/evcount.h>
24 #include <sys/malloc.h>
25
26 #include <machine/autoconf.h>
27 #include <machine/pdc.h>
28
29 #include <dev/pci/pcireg.h>
30 #include <dev/pci/pcivar.h>
31 #include <dev/pci/pcidevs.h>
32
33 #include <hppa/dev/elroyreg.h>
34 #include <hppa/dev/elroyvar.h>
35
36 #define APIC_INT_LINE_MASK 0x0000ff00
37 #define APIC_INT_LINE_SHIFT 8
38 #define APIC_INT_IRQ_MASK 0x0000001f
39
40 #define APIC_INT_LINE(x) (((x) & APIC_INT_LINE_MASK) >> APIC_INT_LINE_SHIFT)
41 #define APIC_INT_IRQ(x) ((x) & APIC_INT_IRQ_MASK)
42
43 /*
44 * Interrupt types match the Intel MP Specification.
45 */
46
47 #define MPS_INTPO_DEF 0
48 #define MPS_INTPO_ACTHI 1
49 #define MPS_INTPO_ACTLO 3
50 #define MPS_INTPO_SHIFT 0
51 #define MPS_INTPO_MASK 3
52
53 #define MPS_INTTR_DEF 0
54 #define MPS_INTTR_EDGE 1
55 #define MPS_INTTR_LEVEL 3
56 #define MPS_INTTR_SHIFT 2
57 #define MPS_INTTR_MASK 3
58
59 #define MPS_INT(p,t) \
60 ((((p) & MPS_INTPO_MASK) << MPS_INTPO_SHIFT) | \
61 (((t) & MPS_INTTR_MASK) << MPS_INTTR_SHIFT))
62
63 struct apic_iv {
64 struct elroy_softc *sc;
65 pci_intr_handle_t ih;
66 int (*handler)(void *);
67 void *arg;
68 struct apic_iv *next;
69 struct evcount *cnt;
70 };
71
72 struct apic_iv *apic_intr_list[CPU_NINTS];
73
74 void apic_get_int_tbl(struct elroy_softc *);
75 u_int32_t apic_get_int_ent0(struct elroy_softc *, int);
76 #ifdef DEBUG
77 void apic_dump(struct elroy_softc *);
78 #endif
79
80 void apic_write(volatile struct elroy_regs *r, u_int32_t reg,
81 u_int32_t val);
82 u_int32_t apic_read(volatile struct elroy_regs *r, u_int32_t reg);
83
84 void
apic_write(volatile struct elroy_regs * r,u_int32_t reg,u_int32_t val)85 apic_write(volatile struct elroy_regs *r, u_int32_t reg, u_int32_t val)
86 {
87 elroy_write32(&r->apic_addr, htole32(reg));
88 elroy_write32(&r->apic_data, htole32(val));
89 elroy_read32(&r->apic_data);
90 }
91
92 u_int32_t
apic_read(volatile struct elroy_regs * r,u_int32_t reg)93 apic_read(volatile struct elroy_regs *r, u_int32_t reg)
94 {
95 elroy_write32(&r->apic_addr, htole32(reg));
96 return letoh32(elroy_read32(&r->apic_data));
97 }
98
99 void
apic_attach(struct elroy_softc * sc)100 apic_attach(struct elroy_softc *sc)
101 {
102 volatile struct elroy_regs *r = sc->sc_regs;
103 u_int32_t data;
104
105 data = apic_read(r, APIC_VERSION);
106 sc->sc_nints = (data & APIC_VERSION_NENT) >> APIC_VERSION_NENT_SHIFT;
107 printf(" APIC ver %x, %d pins",
108 data & APIC_VERSION_MASK, sc->sc_nints);
109
110 sc->sc_irq = mallocarray(sc->sc_nints, sizeof(int), M_DEVBUF,
111 M_NOWAIT | M_ZERO);
112 if (sc->sc_irq == NULL)
113 panic("apic_attach: cannot allocate irq table");
114
115 apic_get_int_tbl(sc);
116
117 #ifdef DEBUG
118 apic_dump(sc);
119 #endif
120 }
121
122 int
apic_intr_map(struct pci_attach_args * pa,pci_intr_handle_t * ihp)123 apic_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
124 {
125 struct elroy_softc *sc = pa->pa_pc->_cookie;
126 pci_chipset_tag_t pc = pa->pa_pc;
127 pcitag_t tag = pa->pa_tag;
128 pcireg_t reg;
129 int line;
130
131 reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
132 #ifdef DEBUG
133 printf(" pin=%d line=%d ", PCI_INTERRUPT_PIN(reg),
134 PCI_INTERRUPT_LINE(reg));
135 #endif
136 line = PCI_INTERRUPT_LINE(reg);
137 if (sc->sc_irq[line] <= 0) {
138 if ((sc->sc_irq[line] = cpu_intr_findirq()) == -1)
139 return 1;
140 }
141 *ihp = (line << APIC_INT_LINE_SHIFT) | sc->sc_irq[line];
142 return (APIC_INT_IRQ(*ihp) == 0);
143 }
144
145 const char *
apic_intr_string(void * v,pci_intr_handle_t ih)146 apic_intr_string(void *v, pci_intr_handle_t ih)
147 {
148 static char buf[32];
149
150 snprintf(buf, 32, "line %ld irq %ld",
151 APIC_INT_LINE(ih), APIC_INT_IRQ(ih));
152
153 return (buf);
154 }
155
156 void *
apic_intr_establish(void * v,pci_intr_handle_t ih,int pri,int (* handler)(void *),void * arg,const char * name)157 apic_intr_establish(void *v, pci_intr_handle_t ih,
158 int pri, int (*handler)(void *), void *arg, const char *name)
159 {
160 struct elroy_softc *sc = v;
161 volatile struct elroy_regs *r = sc->sc_regs;
162 hppa_hpa_t hpa = cpu_gethpa(0);
163 struct evcount *cnt;
164 struct apic_iv *aiv, *biv;
165 void *iv;
166 int irq = APIC_INT_IRQ(ih);
167 int line = APIC_INT_LINE(ih);
168 u_int32_t ent0;
169
170 /* no mapping or bogus */
171 if (irq <= 0 || irq > 31)
172 return (NULL);
173
174 aiv = malloc(sizeof(struct apic_iv), M_DEVBUF, M_NOWAIT);
175 if (aiv == NULL)
176 return (NULL);
177
178 cnt = malloc(sizeof(struct evcount), M_DEVBUF, M_NOWAIT);
179 if (!cnt) {
180 free(aiv, M_DEVBUF, sizeof *aiv);
181 return (NULL);
182 }
183
184 aiv->sc = sc;
185 aiv->ih = ih;
186 aiv->handler = handler;
187 aiv->arg = arg;
188 aiv->next = NULL;
189 aiv->cnt = cnt;
190
191 evcount_attach(cnt, name, NULL);
192
193 if (apic_intr_list[irq]) {
194 biv = apic_intr_list[irq];
195 while (biv->next)
196 biv = biv->next;
197 biv->next = aiv;
198 return (arg);
199 }
200
201 if ((iv = cpu_intr_establish(pri, irq, apic_intr, aiv, NULL))) {
202 ent0 = (31 - irq) & APIC_ENT0_VEC;
203 ent0 |= apic_get_int_ent0(sc, line);
204 #if 0
205 if (cold) {
206 sc->sc_imr |= (1 << irq);
207 ent0 |= APIC_ENT0_MASK;
208 }
209 #endif
210 apic_write(sc->sc_regs, APIC_ENT0(line), APIC_ENT0_MASK);
211 apic_write(sc->sc_regs, APIC_ENT1(line),
212 ((hpa & 0x0ff00000) >> 4) | ((hpa & 0x000ff000) << 12));
213 apic_write(sc->sc_regs, APIC_ENT0(line), ent0);
214
215 /* Signal EOI. */
216 elroy_write32(&r->apic_eoi,
217 htole32((31 - irq) & APIC_ENT0_VEC));
218
219 apic_intr_list[irq] = aiv;
220 }
221
222 return (arg);
223 }
224
225 void
apic_intr_disestablish(void * v,void * cookie)226 apic_intr_disestablish(void *v, void *cookie)
227 {
228 }
229
230 int
apic_intr(void * v)231 apic_intr(void *v)
232 {
233 struct apic_iv *iv = v;
234 struct elroy_softc *sc = iv->sc;
235 volatile struct elroy_regs *r = sc->sc_regs;
236 pci_intr_handle_t ih = iv->ih;
237 int claimed = 0;
238
239 while (iv) {
240 claimed = iv->handler(iv->arg);
241 if (claimed != 0 && iv->cnt)
242 iv->cnt->ec_count++;
243 if (claimed == 1)
244 break;
245 iv = iv->next;
246 }
247
248 /* Signal EOI. */
249 elroy_write32(&r->apic_eoi,
250 htole32((31 - APIC_INT_IRQ(ih)) & APIC_ENT0_VEC));
251
252 return (claimed);
253 }
254
255 /* Maximum number of supported interrupt routing entries. */
256 #define MAX_INT_TBL_SZ 16
257
258 void
apic_get_int_tbl(struct elroy_softc * sc)259 apic_get_int_tbl(struct elroy_softc *sc)
260 {
261 struct pdc_pat_io_num int_tbl_sz PDC_ALIGNMENT;
262 struct pdc_pat_pci_rt int_tbl[MAX_INT_TBL_SZ] PDC_ALIGNMENT;
263 size_t size;
264
265 /*
266 * XXX int_tbl should not be allocated on the stack, but we need a
267 * 1:1 mapping, and malloc doesn't provide that.
268 */
269
270 if (pdc_call((iodcio_t)pdc, 0, PDC_PCI_INDEX, PDC_PCI_GET_INT_TBL_SZ,
271 &int_tbl_sz, 0, 0, 0, 0, 0))
272 return;
273
274 if (int_tbl_sz.num > MAX_INT_TBL_SZ)
275 panic("interrupt routing table too big (%d entries)",
276 int_tbl_sz.num);
277
278 size = int_tbl_sz.num * sizeof(struct pdc_pat_pci_rt);
279 sc->sc_int_tbl_sz = int_tbl_sz.num;
280 sc->sc_int_tbl = malloc(size, M_DEVBUF, M_NOWAIT);
281 if (sc->sc_int_tbl == NULL)
282 return;
283
284 if (pdc_call((iodcio_t)pdc, 0, PDC_PCI_INDEX, PDC_PCI_GET_INT_TBL,
285 &int_tbl_sz, 0, &int_tbl, 0, 0, 0))
286 return;
287
288 memcpy(sc->sc_int_tbl, int_tbl, size);
289 }
290
291 u_int32_t
apic_get_int_ent0(struct elroy_softc * sc,int line)292 apic_get_int_ent0(struct elroy_softc *sc, int line)
293 {
294 volatile struct elroy_regs *r = sc->sc_regs;
295 int trigger = MPS_INT(MPS_INTPO_DEF, MPS_INTTR_DEF);
296 u_int32_t ent0 = APIC_ENT0_LOW | APIC_ENT0_LEV;
297 int bus, mpspo, mpstr;
298 int i;
299
300 bus = letoh32(elroy_read32(&r->busnum)) & 0xff;
301 for (i = 0; i < sc->sc_int_tbl_sz; i++) {
302 if (bus == sc->sc_int_tbl[i].bus &&
303 line == sc->sc_int_tbl[i].line)
304 trigger = sc->sc_int_tbl[i].trigger;
305 }
306
307 mpspo = (trigger >> MPS_INTPO_SHIFT) & MPS_INTPO_MASK;
308 mpstr = (trigger >> MPS_INTTR_SHIFT) & MPS_INTTR_MASK;
309
310 switch (mpspo) {
311 case MPS_INTPO_DEF:
312 break;
313 case MPS_INTPO_ACTHI:
314 ent0 &= ~APIC_ENT0_LOW;
315 break;
316 case MPS_INTPO_ACTLO:
317 ent0 |= APIC_ENT0_LOW;
318 break;
319 default:
320 panic("unknown MPS interrupt polarity %d", mpspo);
321 }
322
323 switch(mpstr) {
324 case MPS_INTTR_DEF:
325 break;
326 case MPS_INTTR_LEVEL:
327 ent0 |= APIC_ENT0_LEV;
328 break;
329 case MPS_INTTR_EDGE:
330 ent0 &= ~APIC_ENT0_LEV;
331 break;
332 default:
333 panic("unknown MPS interrupt trigger %d", mpstr);
334 }
335
336 return ent0;
337 }
338
339 #ifdef DEBUG
340 void
apic_dump(struct elroy_softc * sc)341 apic_dump(struct elroy_softc *sc)
342 {
343 int i;
344
345 for (i = 0; i < sc->sc_nints; i++)
346 printf("0x%04x 0x%04x\n", apic_read(sc->sc_regs, APIC_ENT0(i)),
347 apic_read(sc->sc_regs, APIC_ENT1(i)));
348
349 for (i = 0; i < sc->sc_int_tbl_sz; i++) {
350 printf("type=%x ", sc->sc_int_tbl[i].type);
351 printf("len=%d ", sc->sc_int_tbl[i].len);
352 printf("itype=%d ", sc->sc_int_tbl[i].itype);
353 printf("trigger=%x ", sc->sc_int_tbl[i].trigger);
354 printf("pin=%x ", sc->sc_int_tbl[i].pin);
355 printf("bus=%d ", sc->sc_int_tbl[i].bus);
356 printf("line=%d ", sc->sc_int_tbl[i].line);
357 printf("addr=%x\n", sc->sc_int_tbl[i].addr);
358 }
359 }
360 #endif
361