1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Unaligned memory access handler
4 *
5 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
6 * Copyright (C) 2022 Helge Deller <deller@gmx.de>
7 * Significantly tweaked by LaMont Jones <lamont@debian.org>
8 */
9
10 #include <linux/sched/signal.h>
11 #include <linux/signal.h>
12 #include <linux/ratelimit.h>
13 #include <linux/uaccess.h>
14 #include <linux/sysctl.h>
15 #include <asm/unaligned.h>
16 #include <asm/hardirq.h>
17 #include <asm/traps.h>
18
19 /* #define DEBUG_UNALIGNED 1 */
20
21 #ifdef DEBUG_UNALIGNED
22 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
23 #else
24 #define DPRINTF(fmt, args...)
25 #endif
26
27 #define RFMT "%#08lx"
28
29 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
30 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
31 #define OPCODE2(a,b) ((a)<<26|(b)<<1)
32 #define OPCODE3(a,b) ((a)<<26|(b)<<2)
33 #define OPCODE4(a) ((a)<<26)
34 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
35 #define OPCODE2_MASK OPCODE2(0x3f,1)
36 #define OPCODE3_MASK OPCODE3(0x3f,1)
37 #define OPCODE4_MASK OPCODE4(0x3f)
38
39 /* skip LDB - never unaligned (index) */
40 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
41 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
42 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
43 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
44 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
45 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
46 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
47 /* skip LDB - never unaligned (short) */
48 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
49 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
50 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
51 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
52 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
53 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
54 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
55 /* skip STB - never unaligned */
56 #define OPCODE_STH OPCODE1(0x03,1,0x9)
57 #define OPCODE_STW OPCODE1(0x03,1,0xa)
58 #define OPCODE_STD OPCODE1(0x03,1,0xb)
59 /* skip STBY - never unaligned */
60 /* skip STDBY - never unaligned */
61 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
62 #define OPCODE_STDA OPCODE1(0x03,1,0xf)
63
64 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
65 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
66 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
67 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
68 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
69 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
70 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
71 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
72 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
73 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
74 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
75 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
76
77 #define OPCODE_LDD_L OPCODE2(0x14,0)
78 #define OPCODE_FLDD_L OPCODE2(0x14,1)
79 #define OPCODE_STD_L OPCODE2(0x1c,0)
80 #define OPCODE_FSTD_L OPCODE2(0x1c,1)
81
82 #define OPCODE_LDW_M OPCODE3(0x17,1)
83 #define OPCODE_FLDW_L OPCODE3(0x17,0)
84 #define OPCODE_FSTW_L OPCODE3(0x1f,0)
85 #define OPCODE_STW_M OPCODE3(0x1f,1)
86
87 #define OPCODE_LDH_L OPCODE4(0x11)
88 #define OPCODE_LDW_L OPCODE4(0x12)
89 #define OPCODE_LDWM OPCODE4(0x13)
90 #define OPCODE_STH_L OPCODE4(0x19)
91 #define OPCODE_STW_L OPCODE4(0x1A)
92 #define OPCODE_STWM OPCODE4(0x1B)
93
94 #define MAJOR_OP(i) (((i)>>26)&0x3f)
95 #define R1(i) (((i)>>21)&0x1f)
96 #define R2(i) (((i)>>16)&0x1f)
97 #define R3(i) ((i)&0x1f)
98 #define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
99 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
100 #define IM5_2(i) IM((i)>>16,5)
101 #define IM5_3(i) IM((i),5)
102 #define IM14(i) IM((i),14)
103
104 #define ERR_NOTHANDLED -1
105
106 int unaligned_enabled __read_mostly = 1;
107
emulate_ldh(struct pt_regs * regs,int toreg)108 static int emulate_ldh(struct pt_regs *regs, int toreg)
109 {
110 unsigned long saddr = regs->ior;
111 unsigned long val = 0, temp1;
112 ASM_EXCEPTIONTABLE_VAR(ret);
113
114 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
115 regs->isr, regs->ior, toreg);
116
117 __asm__ __volatile__ (
118 " mtsp %4, %%sr1\n"
119 "1: ldbs 0(%%sr1,%3), %2\n"
120 "2: ldbs 1(%%sr1,%3), %0\n"
121 " depw %2, 23, 24, %0\n"
122 "3: \n"
123 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
124 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
125 : "+r" (val), "+r" (ret), "=&r" (temp1)
126 : "r" (saddr), "r" (regs->isr) );
127
128 DPRINTF("val = " RFMT "\n", val);
129
130 if (toreg)
131 regs->gr[toreg] = val;
132
133 return ret;
134 }
135
emulate_ldw(struct pt_regs * regs,int toreg,int flop)136 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
137 {
138 unsigned long saddr = regs->ior;
139 unsigned long val = 0, temp1, temp2;
140 ASM_EXCEPTIONTABLE_VAR(ret);
141
142 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
143 regs->isr, regs->ior, toreg);
144
145 __asm__ __volatile__ (
146 " zdep %4,28,2,%2\n" /* r19=(ofs&3)*8 */
147 " mtsp %5, %%sr1\n"
148 " depw %%r0,31,2,%4\n"
149 "1: ldw 0(%%sr1,%4),%0\n"
150 "2: ldw 4(%%sr1,%4),%3\n"
151 " subi 32,%2,%2\n"
152 " mtctl %2,11\n"
153 " vshd %0,%3,%0\n"
154 "3: \n"
155 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
156 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
157 : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
158 : "r" (saddr), "r" (regs->isr) );
159
160 DPRINTF("val = " RFMT "\n", val);
161
162 if (flop)
163 ((__u32*)(regs->fr))[toreg] = val;
164 else if (toreg)
165 regs->gr[toreg] = val;
166
167 return ret;
168 }
emulate_ldd(struct pt_regs * regs,int toreg,int flop)169 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
170 {
171 unsigned long saddr = regs->ior;
172 unsigned long shift, temp1;
173 __u64 val = 0;
174 ASM_EXCEPTIONTABLE_VAR(ret);
175
176 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
177 regs->isr, regs->ior, toreg);
178
179 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
180 return ERR_NOTHANDLED;
181
182 #ifdef CONFIG_64BIT
183 __asm__ __volatile__ (
184 " depd,z %2,60,3,%3\n" /* shift=(ofs&7)*8 */
185 " mtsp %5, %%sr1\n"
186 " depd %%r0,63,3,%2\n"
187 "1: ldd 0(%%sr1,%2),%0\n"
188 "2: ldd 8(%%sr1,%2),%4\n"
189 " subi 64,%3,%3\n"
190 " mtsar %3\n"
191 " shrpd %0,%4,%%sar,%0\n"
192 "3: \n"
193 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
194 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
195 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
196 : "r" (regs->isr) );
197 #else
198 __asm__ __volatile__ (
199 " zdep %2,29,2,%3\n" /* shift=(ofs&3)*8 */
200 " mtsp %5, %%sr1\n"
201 " dep %%r0,31,2,%2\n"
202 "1: ldw 0(%%sr1,%2),%0\n"
203 "2: ldw 4(%%sr1,%2),%R0\n"
204 "3: ldw 8(%%sr1,%2),%4\n"
205 " subi 32,%3,%3\n"
206 " mtsar %3\n"
207 " vshd %0,%R0,%0\n"
208 " vshd %R0,%4,%R0\n"
209 "4: \n"
210 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b, "%1")
211 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b, "%1")
212 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")
213 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
214 : "r" (regs->isr) );
215 #endif
216
217 DPRINTF("val = 0x%llx\n", val);
218
219 if (flop)
220 regs->fr[toreg] = val;
221 else if (toreg)
222 regs->gr[toreg] = val;
223
224 return ret;
225 }
226
emulate_sth(struct pt_regs * regs,int frreg)227 static int emulate_sth(struct pt_regs *regs, int frreg)
228 {
229 unsigned long val = regs->gr[frreg], temp1;
230 ASM_EXCEPTIONTABLE_VAR(ret);
231
232 if (!frreg)
233 val = 0;
234
235 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
236 val, regs->isr, regs->ior);
237
238 __asm__ __volatile__ (
239 " mtsp %4, %%sr1\n"
240 " extrw,u %2, 23, 8, %1\n"
241 "1: stb %1, 0(%%sr1, %3)\n"
242 "2: stb %2, 1(%%sr1, %3)\n"
243 "3: \n"
244 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
245 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
246 : "+r" (ret), "=&r" (temp1)
247 : "r" (val), "r" (regs->ior), "r" (regs->isr) );
248
249 return ret;
250 }
251
emulate_stw(struct pt_regs * regs,int frreg,int flop)252 static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
253 {
254 unsigned long val;
255 ASM_EXCEPTIONTABLE_VAR(ret);
256
257 if (flop)
258 val = ((__u32*)(regs->fr))[frreg];
259 else if (frreg)
260 val = regs->gr[frreg];
261 else
262 val = 0;
263
264 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
265 val, regs->isr, regs->ior);
266
267
268 __asm__ __volatile__ (
269 " mtsp %3, %%sr1\n"
270 " zdep %2, 28, 2, %%r19\n"
271 " dep %%r0, 31, 2, %2\n"
272 " mtsar %%r19\n"
273 " depwi,z -2, %%sar, 32, %%r19\n"
274 "1: ldw 0(%%sr1,%2),%%r20\n"
275 "2: ldw 4(%%sr1,%2),%%r21\n"
276 " vshd %%r0, %1, %%r22\n"
277 " vshd %1, %%r0, %%r1\n"
278 " and %%r20, %%r19, %%r20\n"
279 " andcm %%r21, %%r19, %%r21\n"
280 " or %%r22, %%r20, %%r20\n"
281 " or %%r1, %%r21, %%r21\n"
282 " stw %%r20,0(%%sr1,%2)\n"
283 " stw %%r21,4(%%sr1,%2)\n"
284 "3: \n"
285 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
286 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
287 : "+r" (ret)
288 : "r" (val), "r" (regs->ior), "r" (regs->isr)
289 : "r19", "r20", "r21", "r22", "r1" );
290
291 return ret;
292 }
emulate_std(struct pt_regs * regs,int frreg,int flop)293 static int emulate_std(struct pt_regs *regs, int frreg, int flop)
294 {
295 __u64 val;
296 ASM_EXCEPTIONTABLE_VAR(ret);
297
298 if (flop)
299 val = regs->fr[frreg];
300 else if (frreg)
301 val = regs->gr[frreg];
302 else
303 val = 0;
304
305 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
306 val, regs->isr, regs->ior);
307
308 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
309 return ERR_NOTHANDLED;
310
311 #ifdef CONFIG_64BIT
312 __asm__ __volatile__ (
313 " mtsp %3, %%sr1\n"
314 " depd,z %2, 60, 3, %%r19\n"
315 " depd %%r0, 63, 3, %2\n"
316 " mtsar %%r19\n"
317 " depdi,z -2, %%sar, 64, %%r19\n"
318 "1: ldd 0(%%sr1,%2),%%r20\n"
319 "2: ldd 8(%%sr1,%2),%%r21\n"
320 " shrpd %%r0, %1, %%sar, %%r22\n"
321 " shrpd %1, %%r0, %%sar, %%r1\n"
322 " and %%r20, %%r19, %%r20\n"
323 " andcm %%r21, %%r19, %%r21\n"
324 " or %%r22, %%r20, %%r20\n"
325 " or %%r1, %%r21, %%r21\n"
326 "3: std %%r20,0(%%sr1,%2)\n"
327 "4: std %%r21,8(%%sr1,%2)\n"
328 "5: \n"
329 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b, "%0")
330 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b, "%0")
331 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0")
332 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b, "%0")
333 : "+r" (ret)
334 : "r" (val), "r" (regs->ior), "r" (regs->isr)
335 : "r19", "r20", "r21", "r22", "r1" );
336 #else
337 {
338 __asm__ __volatile__ (
339 " mtsp %3, %%sr1\n"
340 " zdep %R1, 29, 2, %%r19\n"
341 " dep %%r0, 31, 2, %2\n"
342 " mtsar %%r19\n"
343 " zvdepi -2, 32, %%r19\n"
344 "1: ldw 0(%%sr1,%2),%%r20\n"
345 "2: ldw 8(%%sr1,%2),%%r21\n"
346 " vshd %1, %R1, %%r1\n"
347 " vshd %%r0, %1, %1\n"
348 " vshd %R1, %%r0, %R1\n"
349 " and %%r20, %%r19, %%r20\n"
350 " andcm %%r21, %%r19, %%r21\n"
351 " or %1, %%r20, %1\n"
352 " or %R1, %%r21, %R1\n"
353 "3: stw %1,0(%%sr1,%2)\n"
354 "4: stw %%r1,4(%%sr1,%2)\n"
355 "5: stw %R1,8(%%sr1,%2)\n"
356 "6: \n"
357 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b, "%0")
358 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b, "%0")
359 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0")
360 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b, "%0")
361 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b, "%0")
362 : "+r" (ret)
363 : "r" (val), "r" (regs->ior), "r" (regs->isr)
364 : "r19", "r20", "r21", "r1" );
365 }
366 #endif
367
368 return ret;
369 }
370
handle_unaligned(struct pt_regs * regs)371 void handle_unaligned(struct pt_regs *regs)
372 {
373 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
374 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
375 int modify = 0;
376 int ret = ERR_NOTHANDLED;
377
378 __inc_irq_stat(irq_unaligned_count);
379
380 /* log a message with pacing */
381 if (user_mode(regs)) {
382 if (current->thread.flags & PARISC_UAC_SIGBUS) {
383 goto force_sigbus;
384 }
385
386 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
387 __ratelimit(&ratelimit)) {
388 printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
389 " at ip " RFMT " (iir " RFMT ")\n",
390 current->comm, task_pid_nr(current), regs->ior,
391 regs->iaoq[0], regs->iir);
392 #ifdef DEBUG_UNALIGNED
393 show_regs(regs);
394 #endif
395 }
396
397 if (!unaligned_enabled)
398 goto force_sigbus;
399 } else {
400 static DEFINE_RATELIMIT_STATE(kernel_ratelimit, 5 * HZ, 5);
401 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
402 __ratelimit(&kernel_ratelimit))
403 pr_warn("Kernel: unaligned access to " RFMT " in %pS "
404 "(iir " RFMT ")\n",
405 regs->ior, (void *)regs->iaoq[0], regs->iir);
406 }
407
408 /* handle modification - OK, it's ugly, see the instruction manual */
409 switch (MAJOR_OP(regs->iir))
410 {
411 case 0x03:
412 case 0x09:
413 case 0x0b:
414 if (regs->iir&0x20)
415 {
416 modify = 1;
417 if (regs->iir&0x1000) /* short loads */
418 if (regs->iir&0x200)
419 newbase += IM5_3(regs->iir);
420 else
421 newbase += IM5_2(regs->iir);
422 else if (regs->iir&0x2000) /* scaled indexed */
423 {
424 int shift=0;
425 switch (regs->iir & OPCODE1_MASK)
426 {
427 case OPCODE_LDH_I:
428 shift= 1; break;
429 case OPCODE_LDW_I:
430 shift= 2; break;
431 case OPCODE_LDD_I:
432 case OPCODE_LDDA_I:
433 shift= 3; break;
434 }
435 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
436 } else /* simple indexed */
437 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
438 }
439 break;
440 case 0x13:
441 case 0x1b:
442 modify = 1;
443 newbase += IM14(regs->iir);
444 break;
445 case 0x14:
446 case 0x1c:
447 if (regs->iir&8)
448 {
449 modify = 1;
450 newbase += IM14(regs->iir&~0xe);
451 }
452 break;
453 case 0x16:
454 case 0x1e:
455 modify = 1;
456 newbase += IM14(regs->iir&6);
457 break;
458 case 0x17:
459 case 0x1f:
460 if (regs->iir&4)
461 {
462 modify = 1;
463 newbase += IM14(regs->iir&~4);
464 }
465 break;
466 }
467
468 /* TODO: make this cleaner... */
469 switch (regs->iir & OPCODE1_MASK)
470 {
471 case OPCODE_LDH_I:
472 case OPCODE_LDH_S:
473 ret = emulate_ldh(regs, R3(regs->iir));
474 break;
475
476 case OPCODE_LDW_I:
477 case OPCODE_LDWA_I:
478 case OPCODE_LDW_S:
479 case OPCODE_LDWA_S:
480 ret = emulate_ldw(regs, R3(regs->iir), 0);
481 break;
482
483 case OPCODE_STH:
484 ret = emulate_sth(regs, R2(regs->iir));
485 break;
486
487 case OPCODE_STW:
488 case OPCODE_STWA:
489 ret = emulate_stw(regs, R2(regs->iir), 0);
490 break;
491
492 #ifdef CONFIG_64BIT
493 case OPCODE_LDD_I:
494 case OPCODE_LDDA_I:
495 case OPCODE_LDD_S:
496 case OPCODE_LDDA_S:
497 ret = emulate_ldd(regs, R3(regs->iir), 0);
498 break;
499
500 case OPCODE_STD:
501 case OPCODE_STDA:
502 ret = emulate_std(regs, R2(regs->iir), 0);
503 break;
504 #endif
505
506 case OPCODE_FLDWX:
507 case OPCODE_FLDWS:
508 case OPCODE_FLDWXR:
509 case OPCODE_FLDWSR:
510 ret = emulate_ldw(regs, FR3(regs->iir), 1);
511 break;
512
513 case OPCODE_FLDDX:
514 case OPCODE_FLDDS:
515 ret = emulate_ldd(regs, R3(regs->iir), 1);
516 break;
517
518 case OPCODE_FSTWX:
519 case OPCODE_FSTWS:
520 case OPCODE_FSTWXR:
521 case OPCODE_FSTWSR:
522 ret = emulate_stw(regs, FR3(regs->iir), 1);
523 break;
524
525 case OPCODE_FSTDX:
526 case OPCODE_FSTDS:
527 ret = emulate_std(regs, R3(regs->iir), 1);
528 break;
529
530 case OPCODE_LDCD_I:
531 case OPCODE_LDCW_I:
532 case OPCODE_LDCD_S:
533 case OPCODE_LDCW_S:
534 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
535 break;
536 }
537 switch (regs->iir & OPCODE2_MASK)
538 {
539 case OPCODE_FLDD_L:
540 ret = emulate_ldd(regs,R2(regs->iir),1);
541 break;
542 case OPCODE_FSTD_L:
543 ret = emulate_std(regs, R2(regs->iir),1);
544 break;
545 #ifdef CONFIG_64BIT
546 case OPCODE_LDD_L:
547 ret = emulate_ldd(regs, R2(regs->iir),0);
548 break;
549 case OPCODE_STD_L:
550 ret = emulate_std(regs, R2(regs->iir),0);
551 break;
552 #endif
553 }
554 switch (regs->iir & OPCODE3_MASK)
555 {
556 case OPCODE_FLDW_L:
557 ret = emulate_ldw(regs, R2(regs->iir), 1);
558 break;
559 case OPCODE_LDW_M:
560 ret = emulate_ldw(regs, R2(regs->iir), 0);
561 break;
562
563 case OPCODE_FSTW_L:
564 ret = emulate_stw(regs, R2(regs->iir),1);
565 break;
566 case OPCODE_STW_M:
567 ret = emulate_stw(regs, R2(regs->iir),0);
568 break;
569 }
570 switch (regs->iir & OPCODE4_MASK)
571 {
572 case OPCODE_LDH_L:
573 ret = emulate_ldh(regs, R2(regs->iir));
574 break;
575 case OPCODE_LDW_L:
576 case OPCODE_LDWM:
577 ret = emulate_ldw(regs, R2(regs->iir),0);
578 break;
579 case OPCODE_STH_L:
580 ret = emulate_sth(regs, R2(regs->iir));
581 break;
582 case OPCODE_STW_L:
583 case OPCODE_STWM:
584 ret = emulate_stw(regs, R2(regs->iir),0);
585 break;
586 }
587
588 if (ret == 0 && modify && R1(regs->iir))
589 regs->gr[R1(regs->iir)] = newbase;
590
591
592 if (ret == ERR_NOTHANDLED)
593 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
594
595 DPRINTF("ret = %d\n", ret);
596
597 if (ret)
598 {
599 /*
600 * The unaligned handler failed.
601 * If we were called by __get_user() or __put_user() jump
602 * to it's exception fixup handler instead of crashing.
603 */
604 if (!user_mode(regs) && fixup_exception(regs))
605 return;
606
607 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
608 die_if_kernel("Unaligned data reference", regs, 28);
609
610 if (ret == -EFAULT)
611 {
612 force_sig_fault(SIGSEGV, SEGV_MAPERR,
613 (void __user *)regs->ior);
614 }
615 else
616 {
617 force_sigbus:
618 /* couldn't handle it ... */
619 force_sig_fault(SIGBUS, BUS_ADRALN,
620 (void __user *)regs->ior);
621 }
622
623 return;
624 }
625
626 /* else we handled it, let life go on. */
627 regs->gr[0]|=PSW_N;
628 }
629
630 /*
631 * NB: check_unaligned() is only used for PCXS processors right
632 * now, so we only check for PA1.1 encodings at this point.
633 */
634
635 int
check_unaligned(struct pt_regs * regs)636 check_unaligned(struct pt_regs *regs)
637 {
638 unsigned long align_mask;
639
640 /* Get alignment mask */
641
642 align_mask = 0UL;
643 switch (regs->iir & OPCODE1_MASK) {
644
645 case OPCODE_LDH_I:
646 case OPCODE_LDH_S:
647 case OPCODE_STH:
648 align_mask = 1UL;
649 break;
650
651 case OPCODE_LDW_I:
652 case OPCODE_LDWA_I:
653 case OPCODE_LDW_S:
654 case OPCODE_LDWA_S:
655 case OPCODE_STW:
656 case OPCODE_STWA:
657 align_mask = 3UL;
658 break;
659
660 default:
661 switch (regs->iir & OPCODE4_MASK) {
662 case OPCODE_LDH_L:
663 case OPCODE_STH_L:
664 align_mask = 1UL;
665 break;
666 case OPCODE_LDW_L:
667 case OPCODE_LDWM:
668 case OPCODE_STW_L:
669 case OPCODE_STWM:
670 align_mask = 3UL;
671 break;
672 }
673 break;
674 }
675
676 return (int)(regs->ior & align_mask);
677 }
678
679