1 /* $NetBSD: eprtcreg.h,v 1.2 2022/03/24 12:12:00 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Cirrus Logic EP9315 29 RealTime Clock register 30 http://www.cirrus.com/jp/pubs/manual/EP9315_Users_Guide.pdf */ 31 32 #ifndef _EPRTCREG_H_ 33 #define _EPRTCREG_H_ 34 35 #define EP93XX_RTC_Data 0x00 /* RTC Data Register (RO) */ 36 #define EP93XX_RTC_Match 0x04 /* RTC Match Register (R/W) */ 37 #define EP93XX_RTC_Sts 0x08 /* RTC Status/EOI Register (R/W) */ 38 #define EP93XX_RTC_INTR (1<<0) /* Interrupt status */ 39 #define EP93XX_RTC_Load 0x0c /* RTC Load Register (R/W) */ 40 #define EP93XX_RTC_Ctrl 0x10 /* RTC Control Register (R/W) */ 41 #define EP93XX_RTC_MIE (1<<0) /* Match Interrupt Enable */ 42 #define EP93XX_RTC_SWComp 0x108 /* RTC Software Compensation (R/W) */ 43 #define EP93XX_RTC_DEL_SHIFT (1<<16) /* Number of clocks to delete */ 44 #define EP93XX_RTC_DEL_MASK 0x001f0000 45 #define EP93XX_RTC_INT_SHIFT (1<<0) /* Counter pre-load Integer value */ 46 #define EP93XX_RTC_INT_MASK 0x0000ffff 47 48 #endif /* _EPRTCREG_H_ */ 49