1 #ifndef __asm_regnames_h__ 2 #define __asm_regnames_h__ 3 4 /* Special names */ 5 #define zero $0 /* always zero */ 6 /*#define at $1 (* assembler temporary *) */ 7 /* above conflicts with the .set at assembler directive. just use $1 instead */ 8 #define v0 $2 /* function values */ 9 #define v1 $3 10 #define a0 $4 /* function arguments */ 11 #define a1 $5 12 #define a2 $6 13 #define a3 $7 14 #define t0 $8 /* temporary registers; not preserved across func calls */ 15 #define t1 $9 16 #define t2 $10 17 #define t3 $11 18 #define t4 $12 19 #define t5 $13 20 #define t6 $14 21 #define t7 $15 22 #define s0 $16 /* "saved" regs - must preserve these if you use them */ 23 #define s1 $17 24 #define s2 $18 25 #define s3 $19 26 #define s4 $20 27 #define s5 $21 28 #define s6 $22 29 #define s7 $23 30 #define t8 $24 /* more temporary regs */ 31 #define t9 $25 32 #define k0 $26 /* kernel temporary variables */ 33 #define kt0 $26 34 #define k1 $27 35 #define kt1 $27 36 #define gp $28 /* pointer to globals */ 37 #define sp $29 /* stack pointer */ 38 #define s8 $30 /* another "saved" reg */ 39 #define ra $31 /* return address */ 40 41 /* FPU register names - included for a consistent appearance */ 42 #define f0 $f0 43 #define f1 $f1 44 #define f2 $f2 45 #define f3 $f3 46 #define f4 $f4 47 #define f5 $f5 48 #define f6 $f6 49 #define f7 $f7 50 #define f8 $f8 51 #define f9 $f9 52 #define f10 $f10 53 #define f11 $f11 54 #define f12 $f12 55 #define f13 $f13 56 #define f14 $f14 57 #define f15 $f15 58 #define f16 $f16 59 #define f17 $f17 60 #define f18 $f18 61 #define f19 $f19 62 #define f20 $f20 63 #define f21 $f21 64 #define f22 $f22 65 #define f23 $f23 66 #define f24 $f24 67 #define f25 $f25 68 #define f26 $f26 69 #define f27 $f27 70 #define f28 $f28 71 #define f29 $f29 72 #define f30 $f30 73 #define f31 $f31 74 75 /* CP0 reg names - these pertain to address translation and 76 * exception handling, and not all of them are implemented on the 77 * R3000. (But they have such cool names...) 78 */ 79 #define Index $0 /* selects TLB entry for r/w ops & shows probe success */ 80 #define Random $1 /* continuously decrementing number (range 8..63) */ 81 #define EntryLo $2 /* low word of a TLB entry */ 82 #define EntryLo0 $2 /* R4k uses this for even-numbered virtual pages */ 83 #define EntryLo1 $3 /* R4k uses this for odd-numbered virtual pages */ 84 #define Context $4 /* TLB refill handler's kernel PTE entry pointer */ 85 #define PageMask $5 /* R4k page number bit mask (impl. variable page sizes) */ 86 #define Wired $6 /* R4k lower bnd for Random (controls randomness of TLB) */ 87 #define Error $7 /* R6k status/control register for parity checking */ 88 #define BadVAddr $8 /* "bad" virt. addr (VA of last failed v->p translation) */ 89 #define Count $9 /* R4k r/w reg - continuously incrementing counter */ 90 #define EntryHi $10 /* High word of a TLB entry */ 91 #define ASID $10 /* R6k uses this to store the ASID (only) */ 92 #define Compare $11 /* R4k traps when this register equals Count */ 93 #define Status $12 /* Kernel/User mode, interrupt enb., & diagnostic states */ 94 #define Cause $13 /* Cause of last exception */ 95 #define EPC $14 /* Address to return to after processing this exception */ 96 #define PRId $15 /* Processor revision identifier */ 97 #define Config $16 /* R4k config options for caches, etc. */ 98 #define LLAdr $17 /* R4k last instruction read by a Load Linked */ 99 #define LLAddr $17 /* Inconsistencies in naming... sigh. */ 100 #define WatchLo $18 /* R4k hardware watchpoint data */ 101 #define WatchHi $19 /* R4k hardware watchpoint data */ 102 /* 20-25 - reserved */ 103 #define ECC $26 /* R4k cache Error Correction Code */ 104 #define CacheErr $27 /* R4k read-only cache error codes */ 105 #define TagLo $28 /* R4k primary or secondary cache tag and parity */ 106 #define TagHi $29 /* R4k primary or secondary cache tag and parity */ 107 #define ErrorEPC $30 /* R4k cache error EPC */ 108 /* 31 - reserved */ 109 110 /* Exceptions - Cause register ExcCode field */ 111 #define Int 0 /* Interrupt */ 112 #define Mod 1 /* TLB modification exception */ 113 #define TLBL 2 /* TLB exception (load or instruction fetch) */ 114 #define TLBS 3 /* TLB exception (store) */ 115 #define AdEL 4 /* Address error exception (load or instruction fetch) */ 116 #define AdES 5 /* Address error exception (store) */ 117 #define IBE 6 /* Instruction bus error */ 118 #define DBE 7 /* Data (load or store) bus error */ 119 #define Sys 8 /* SYSCALL exception */ 120 #define Bp 9 /* Breakpoint exception (BREAK instruction) */ 121 #define RI 10 /* Reserved instruction exception */ 122 #define CpU 11 /* Coprocessor Unusable */ 123 #define Ov 12 /* Arithmetic Overflow */ 124 #define Tr 13 /* Trap (R4k/R6k only) */ 125 #define NCD 14 /* LDCz or SDCz to uncached address (R6k) */ 126 #define VCEI 14 /* Virtual Coherency Exception (instruction) (R4k) */ 127 #define MV 15 /* Machine check exception (R6k) */ 128 #define FPE 15 /* Floating-point exception (R4k) */ 129 /* 16-22 - reserved */ 130 #define WATCH 23 /* Reference to WatchHi/WatchLo address detected (R4k) */ 131 /* 24-30 - reserved */ 132 #define VCED 31 /* Virtual Coherency Exception (data) (R4k) */ 133 134 #endif /* __asm_regnames_h__ */ 135