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3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
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10 http://www.apache.org/licenses/LICENSE-2.0
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19
20 //=====================================================================
21 /// @file example_system_top.cpp
22 //
23 /// @brief This class instantiates components that compose the TLM2
24 /// example system. A similar block diagram is created
25 /// for each version, but with different components
26 //
27 //=====================================================================
28 // Authors:
29 // Bill Bunton, ESLX
30 // Anna Keist, ESLX
31 // Charles Wilson, ESLX
32 // Jack Donovan, ESLX
33 //=====================================================================
34 #include "at_1_phase_top.h" // example system top header
35
36 //=====================================================================
37 /// @fn example_system_top::example_system_top
38 //
39 /// @details
40 /// The construcor method calls the bind methods
41 /// to connect the example components.
42 //
43 //=====================================================================
example_system_top(sc_core::sc_module_name name)44 example_system_top::example_system_top
45 ( sc_core::sc_module_name name
46 )
47 : sc_core::sc_module /// Init SC base
48 ( name
49 )
50 , m_bus /// Init Simple Bus
51 ( "m_bus"
52 )
53 , m_at_target_1_phase_1 /// Init intance 1 of AT target
54 ( "m_at_target_1_phase_1" // module name
55 , 201 /// 1st Target ID is 201
56 , "memory_socket_1" // socket name
57 , 4*1024 // memory size (bytes)
58 , 4 // memory width (bytes)
59 , sc_core::sc_time(10, sc_core::SC_NS) // accept delay
60 , sc_core::sc_time(50, sc_core::SC_NS) // read response delay
61 , sc_core::sc_time(30, sc_core::SC_NS) // write response delay
62 )
63 , m_at_target_1_phase_2 /// Init instance 2 of AT target
64 ( "m_at_target_1_phase_2" // module name
65 , 202 /// 2nd Target ID is 202
66 , "memory_socket_1" // socket name
67 , 4*1024 // memory size (bytes)
68 , 4 // memory width (bytes)
69 , sc_core::sc_time(10, sc_core::SC_NS) // accept delay
70 , sc_core::sc_time(50, sc_core::SC_NS) // read response delay
71 , sc_core::sc_time(30, sc_core::SC_NS) // write response delay
72 )
73 , m_initiator_1 /// Init Instance 1 of AT initiator
74 ( "m_initiator_1" // module name
75 , 101 /// 1st Initiator ID is 101
76 , 0x0000000000000100 // fitst base address
77 , 0x0000000010000100 // second base address
78 , 2 // active transactions
79 )
80 , m_initiator_2 /// Init initiator 2
81 ( "m_initiator_2" // module name
82 , 102 /// 2nd Initiator ID is 102
83 , 0x0000000000000200 // fitst base address
84 , 0x0000000010000200 // second base address
85 , 2 // active transactions
86 )
87 {
88 /// bind TLM2 initiators to TLM2 target sockets on SimpleBus
89 m_initiator_1.initiator_socket(m_bus.target_socket[0]);
90 m_initiator_2.initiator_socket(m_bus.target_socket[1]);
91
92 /// bind TLM2 targets to TLM2 initiator sockets on SimpleBus
93 m_bus.initiator_socket[0](m_at_target_1_phase_1.m_memory_socket);
94 m_bus.initiator_socket[1](m_at_target_1_phase_2.m_memory_socket);
95 }
96