1 /***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20 //===================================================================== 21 /// @file example_system_top.h 22 23 /// @brief This class instantiates components that compose TLM2 24 /// example system that demonstrates Out of Order Execution of 25 /// transactions 26 27 //===================================================================== 28 // Original Authors: 29 // Anna Keist, ESLX 30 // Bill Bunton, ESLX 31 // Jack Donovan, ESLX 32 //===================================================================== 33 34 #ifndef __EXAMPLE_SYSTEM_TOP_H__ 35 #define __EXAMPLE_SYSTEM_TOP_H__ 36 37 #include "tlm.h" // TLM header 38 #include "at_target_2_phase.h" // at memory target 39 #include "at_target_ooo_2_phase.h" // memory target 40 #include "initiator_top.h" // processor abstraction initiator 41 #include "models/SimpleBusAT.h" // Bus/Router Implementation 42 43 /// Top wrapper Module 44 class example_system_top 45 : public sc_core::sc_module // SC base class 46 { 47 public: 48 49 /// Constructor 50 51 example_system_top 52 ( sc_core::sc_module_name name); 53 54 //Member Variables =========================================================== 55 private: 56 SimpleBusAT<2, 2> m_bus; ///< simple bus 57 at_target_2_phase m_at_target_2_phase_1; ///< instance 1 target 58 at_target_ooo_2_phase m_at_target_ooo_2_phase_1; ///< instance 2 target 59 initiator_top m_initiator_1; ///< instance 1 initiator 60 initiator_top m_initiator_2; ///< instance 2 initiator 61 }; 62 #endif /* __EXAMPLE_SYSTEM_TOP_H__ */ 63