1@c Copyright 2005
2@c Free Software Foundation, Inc.
3@c This is part of the GAS manual.
4@c For copying conditions, see the file as.texinfo.
5@ifset GENERIC
6@page
7@node BFIN-Dependent
8@chapter Blackfin Dependent Features
9@end ifset
10@ifclear GENERIC
11@node Machine Dependencies
12@chapter Blackfin Dependent Features
13@end ifclear
14
15@cindex Blackfin support
16@menu
17* BFIN Syntax::			BFIN Syntax
18* BFIN Directives::		BFIN Directives
19@end menu
20
21@node BFIN Syntax
22@section Syntax
23@cindex BFIN syntax
24@cindex syntax, BFIN
25
26@table @code
27@item Special Characters
28Assembler input is free format and may appear anywhere on the line.
29One instruction may extend across multiple lines or more than one
30instruction may appear on the same line.  White space (space, tab,
31comments or newline) may appear anywhere between tokens.  A token must
32not have embedded spaces.  Tokens include numbers, register names,
33keywords, user identifiers, and also some multicharacter special
34symbols like "+=", "/*" or "||".
35
36@item Instruction Delimiting
37A semicolon must terminate every instruction.  Sometimes a complete
38instruction will consist of more than one operation.  There are two
39cases where this occurs.  The first is when two general operations
40are combined.  Normally a comma separates the different parts, as in
41
42@smallexample
43a0= r3.h * r2.l, a1 = r3.l * r2.h ;
44@end smallexample
45
46The second case occurs when a general instruction is combined with one
47or two memory references for joint issue.  The latter portions are
48set off by a "||" token.
49
50@smallexample
51a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
52@end smallexample
53
54@item Register Names
55
56The assembler treats register names and instruction keywords in a case
57insensitive manner.  User identifiers are case sensitive.  Thus, R3.l,
58R3.L, r3.l and r3.L are all equivalent input to the assembler.
59
60Register names are reserved and may not be used as program identifiers.
61
62Some operations (such as "Move Register") require a register pair.
63Register pairs are always data registers and are denoted using a colon,
64eg., R3:2.  The larger number must be written firsts.  Note that the
65hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
66
67Some instructions (such as --SP (Push Multiple)) require a group of
68adjacent registers.  Adjacent registers are denoted in the syntax by
69the range enclosed in parentheses and separated by a colon, eg., (R7:3).
70Again, the larger number appears first.
71
72Portions of a particular register may be individually specified.  This
73is written with a dot (".") following the register name and then a
74letter denoting the desired portion.  For 32-bit registers, ".H"
75denotes the most significant ("High") portion.  ".L" denotes the
76least-significant portion.  The subdivisions of the 40-bit registers
77are described later.
78
79@item Accumulators
80The set of 40-bit registers A1 and A0 that normally contain data that
81is being manipulated.  Each accumulator can be accessed in four ways.
82
83@table @code
84@item one 40-bit register
85The register will be referred to as A1 or A0.
86@item one 32-bit register
87The registers are designated as A1.W or A0.W.
88@item two 16-bit registers
89The registers are designated as A1.H, A1.L, A0.H or A0.L.
90@item one 8-bit register
91The registers are designated as A1.X or A0.X for the bits that
92extend beyond bit 31.
93@end table
94
95@item Data Registers
96The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
97normally contain data for manipulation.  These are abbreviated as
98D-register or Dreg.  Data registers can be accessed as 32-bit registers
99or as two independent 16-bit registers.  The least significant 16 bits
100of each register is called the "low" half and is desginated with ".L"
101following the register name.  The most significant 16 bits are called
102the "high" half and is designated with ".H". following the name.
103
104@smallexample
105   R7.L, r2.h, r4.L, R0.H
106@end smallexample
107
108@item Pointer Registers
109The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that
110normally contain byte addresses of data structures.  These are
111abbreviated as P-register or Preg.
112
113@smallexample
114p2, p5, fp, sp
115@end smallexample
116
117@item Stack Pointer SP
118The stack pointer contains the 32-bit address of the last occupied
119byte location in the stack.  The stack grows by decrementing the
120stack pointer.
121
122@item Frame Pointer FP
123The frame pointer contains the 32-bit address of the previous frame
124pointer in the stack.  It is located at the top of a frame.
125
126@item Loop Top
127LT0 and LT1.  These registers contain the 32-bit address of the top of
128a zero overhead loop.
129
130@item Loop Count
131LC0 and LC1.  These registers contain the 32-bit counter of the zero
132overhead loop executions.
133
134@item Loop Bottom
135LB0 and LB1.  These registers contain the 32-bit address of the bottom
136of a zero overhead loop.
137
138@item Index Registers
139The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
140addresses of data structures.  Abbreviated I-register or Ireg.
141
142@item Modify Registers
143The set of 32-bit registers (M0, M1, M2, M3) that normally contain
144offset values that are added and subracted to one of the index
145registers.  Abbreviated as Mreg.
146
147@item Length Registers
148The set of 32-bit registers (L0, L1, L2, L3) that normally contain the
149length in bytes of the circular buffer.  Abbreviated as Lreg.  Clear
150the Lreg to disable circular addressing for the corresponding Ireg.
151
152@item Base Registers
153The set of 32-bit registers (B0, B1, B2, B3) that normally contain the
154base address in bytes of the circular buffer.  Abbreviated as Breg.
155
156@item Floating Point
157The Blackfin family has no hardware floating point but the .float
158directive generates ieee floating point numbers for use with software
159floating point libraries.
160
161@item Blackfin Opcodes
162For detailed information on the Blackfin machine instruction set, see
163the Blackfin(r) Processor Instruction Set Reference.
164
165@end table
166
167@node BFIN Directives
168@section Directives
169@cindex BFIN directives
170@cindex directives, BFIN
171
172The following directives are provided for compatibility with the VDSP assembler.
173
174@table @code
175@item .byte2
176Initializes a four byte data object.
177@item .byte4
178Initializes a two byte data object.
179@item .db
180TBD
181@item .dd
182TBD
183@item .dw
184TBD
185@item .var
186Define and initialize a 32 bit data object.
187@end table
188