1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "radeon.h"
27 #include "radeon_asic.h"
28 #include "radeon_ucode.h"
29 #include "cikd.h"
30 #include "r600_dpm.h"
31 #include "ci_dpm.h"
32 #include "atom.h"
33 #include <linux/seq_file.h>
34
35 #define MC_CG_ARB_FREQ_F0 0x0a
36 #define MC_CG_ARB_FREQ_F1 0x0b
37 #define MC_CG_ARB_FREQ_F2 0x0c
38 #define MC_CG_ARB_FREQ_F3 0x0d
39
40 #define SMC_RAM_END 0x40000
41
42 #define VOLTAGE_SCALE 4
43 #define VOLTAGE_VID_OFFSET_SCALE1 625
44 #define VOLTAGE_VID_OFFSET_SCALE2 100
45
46 static const struct ci_pt_defaults defaults_hawaii_xt =
47 {
48 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
49 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
50 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
51 };
52
53 static const struct ci_pt_defaults defaults_hawaii_pro =
54 {
55 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
56 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
57 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
58 };
59
60 static const struct ci_pt_defaults defaults_bonaire_xt =
61 {
62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
63 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
64 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
65 };
66
67 #if 0 /* unused */
68 static const struct ci_pt_defaults defaults_bonaire_pro =
69 {
70 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
71 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
72 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
73 };
74 #endif
75
76 static const struct ci_pt_defaults defaults_saturn_xt =
77 {
78 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
79 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
80 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
81 };
82
83 #if 0 /* unused */
84 static const struct ci_pt_defaults defaults_saturn_pro =
85 {
86 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
87 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
88 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
89 };
90 #endif
91
92 static const struct ci_pt_config_reg didt_config_ci[] =
93 {
94 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
162 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
163 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
164 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
165 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
166 { 0xFFFFFFFF }
167 };
168
169 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
170 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
171 u32 arb_freq_src, u32 arb_freq_dest);
172
173 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
174 struct atom_voltage_table_entry *voltage_table,
175 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
176 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
177 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
178 u32 target_tdp);
179 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
180
181 static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
182 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
183 PPSMC_Msg msg, u32 parameter);
184
185 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev);
186 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev);
187
ci_get_pi(struct radeon_device * rdev)188 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
189 {
190 struct ci_power_info *pi = rdev->pm.dpm.priv;
191
192 return pi;
193 }
194
ci_get_ps(struct radeon_ps * rps)195 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
196 {
197 struct ci_ps *ps = rps->ps_priv;
198
199 return ps;
200 }
201
ci_initialize_powertune_defaults(struct radeon_device * rdev)202 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
203 {
204 struct ci_power_info *pi = ci_get_pi(rdev);
205
206 switch (rdev->pdev->device) {
207 case 0x6649:
208 case 0x6650:
209 case 0x6651:
210 case 0x6658:
211 case 0x665C:
212 case 0x665D:
213 default:
214 pi->powertune_defaults = &defaults_bonaire_xt;
215 break;
216 case 0x6640:
217 case 0x6641:
218 case 0x6646:
219 case 0x6647:
220 pi->powertune_defaults = &defaults_saturn_xt;
221 break;
222 case 0x67B8:
223 case 0x67B0:
224 pi->powertune_defaults = &defaults_hawaii_xt;
225 break;
226 case 0x67BA:
227 case 0x67B1:
228 pi->powertune_defaults = &defaults_hawaii_pro;
229 break;
230 case 0x67A0:
231 case 0x67A1:
232 case 0x67A2:
233 case 0x67A8:
234 case 0x67A9:
235 case 0x67AA:
236 case 0x67B9:
237 case 0x67BE:
238 pi->powertune_defaults = &defaults_bonaire_xt;
239 break;
240 }
241
242 pi->dte_tj_offset = 0;
243
244 pi->caps_power_containment = true;
245 pi->caps_cac = false;
246 pi->caps_sq_ramping = false;
247 pi->caps_db_ramping = false;
248 pi->caps_td_ramping = false;
249 pi->caps_tcp_ramping = false;
250
251 if (pi->caps_power_containment) {
252 pi->caps_cac = true;
253 if (rdev->family == CHIP_HAWAII)
254 pi->enable_bapm_feature = false;
255 else
256 pi->enable_bapm_feature = true;
257 pi->enable_tdc_limit_feature = true;
258 pi->enable_pkg_pwr_tracking_feature = true;
259 }
260 }
261
ci_convert_to_vid(u16 vddc)262 static u8 ci_convert_to_vid(u16 vddc)
263 {
264 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
265 }
266
ci_populate_bapm_vddc_vid_sidd(struct radeon_device * rdev)267 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
268 {
269 struct ci_power_info *pi = ci_get_pi(rdev);
270 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
271 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
272 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
273 u32 i;
274
275 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
276 return -EINVAL;
277 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
278 return -EINVAL;
279 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
280 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
281 return -EINVAL;
282
283 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
284 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
285 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
286 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
287 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
288 } else {
289 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
290 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
291 }
292 }
293 return 0;
294 }
295
ci_populate_vddc_vid(struct radeon_device * rdev)296 static int ci_populate_vddc_vid(struct radeon_device *rdev)
297 {
298 struct ci_power_info *pi = ci_get_pi(rdev);
299 u8 *vid = pi->smc_powertune_table.VddCVid;
300 u32 i;
301
302 if (pi->vddc_voltage_table.count > 8)
303 return -EINVAL;
304
305 for (i = 0; i < pi->vddc_voltage_table.count; i++)
306 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
307
308 return 0;
309 }
310
ci_populate_svi_load_line(struct radeon_device * rdev)311 static int ci_populate_svi_load_line(struct radeon_device *rdev)
312 {
313 struct ci_power_info *pi = ci_get_pi(rdev);
314 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
315
316 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
317 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
318 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
319 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
320
321 return 0;
322 }
323
ci_populate_tdc_limit(struct radeon_device * rdev)324 static int ci_populate_tdc_limit(struct radeon_device *rdev)
325 {
326 struct ci_power_info *pi = ci_get_pi(rdev);
327 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
328 u16 tdc_limit;
329
330 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
331 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
332 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
333 pt_defaults->tdc_vddc_throttle_release_limit_perc;
334 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
335
336 return 0;
337 }
338
ci_populate_dw8(struct radeon_device * rdev)339 static int ci_populate_dw8(struct radeon_device *rdev)
340 {
341 struct ci_power_info *pi = ci_get_pi(rdev);
342 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
343 int ret;
344
345 ret = ci_read_smc_sram_dword(rdev,
346 SMU7_FIRMWARE_HEADER_LOCATION +
347 offsetof(SMU7_Firmware_Header, PmFuseTable) +
348 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
349 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
350 pi->sram_end);
351 if (ret)
352 return -EINVAL;
353 else
354 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
355
356 return 0;
357 }
358
ci_populate_fuzzy_fan(struct radeon_device * rdev)359 static int ci_populate_fuzzy_fan(struct radeon_device *rdev)
360 {
361 struct ci_power_info *pi = ci_get_pi(rdev);
362
363 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
364 (rdev->pm.dpm.fan.fan_output_sensitivity == 0))
365 rdev->pm.dpm.fan.fan_output_sensitivity =
366 rdev->pm.dpm.fan.default_fan_output_sensitivity;
367
368 pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
369 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity);
370
371 return 0;
372 }
373
ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device * rdev)374 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
375 {
376 struct ci_power_info *pi = ci_get_pi(rdev);
377 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
378 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
379 int i, min, max;
380
381 min = max = hi_vid[0];
382 for (i = 0; i < 8; i++) {
383 if (0 != hi_vid[i]) {
384 if (min > hi_vid[i])
385 min = hi_vid[i];
386 if (max < hi_vid[i])
387 max = hi_vid[i];
388 }
389
390 if (0 != lo_vid[i]) {
391 if (min > lo_vid[i])
392 min = lo_vid[i];
393 if (max < lo_vid[i])
394 max = lo_vid[i];
395 }
396 }
397
398 if ((min == 0) || (max == 0))
399 return -EINVAL;
400 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
401 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
402
403 return 0;
404 }
405
ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device * rdev)406 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
407 {
408 struct ci_power_info *pi = ci_get_pi(rdev);
409 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
410 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
411 struct radeon_cac_tdp_table *cac_tdp_table =
412 rdev->pm.dpm.dyn_state.cac_tdp_table;
413
414 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
415 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
416
417 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
418 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
419
420 return 0;
421 }
422
ci_populate_bapm_parameters_in_dpm_table(struct radeon_device * rdev)423 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
424 {
425 struct ci_power_info *pi = ci_get_pi(rdev);
426 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
427 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
428 struct radeon_cac_tdp_table *cac_tdp_table =
429 rdev->pm.dpm.dyn_state.cac_tdp_table;
430 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
431 int i, j, k;
432 const u16 *def1;
433 const u16 *def2;
434
435 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
436 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
437
438 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
439 dpm_table->GpuTjMax =
440 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
441 dpm_table->GpuTjHyst = 8;
442
443 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
444
445 if (ppm) {
446 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
447 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
448 } else {
449 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
450 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
451 }
452
453 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
454 def1 = pt_defaults->bapmti_r;
455 def2 = pt_defaults->bapmti_rc;
456
457 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
458 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
459 for (k = 0; k < SMU7_DTE_SINKS; k++) {
460 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
461 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
462 def1++;
463 def2++;
464 }
465 }
466 }
467
468 return 0;
469 }
470
ci_populate_pm_base(struct radeon_device * rdev)471 static int ci_populate_pm_base(struct radeon_device *rdev)
472 {
473 struct ci_power_info *pi = ci_get_pi(rdev);
474 u32 pm_fuse_table_offset;
475 int ret;
476
477 if (pi->caps_power_containment) {
478 ret = ci_read_smc_sram_dword(rdev,
479 SMU7_FIRMWARE_HEADER_LOCATION +
480 offsetof(SMU7_Firmware_Header, PmFuseTable),
481 &pm_fuse_table_offset, pi->sram_end);
482 if (ret)
483 return ret;
484 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
485 if (ret)
486 return ret;
487 ret = ci_populate_vddc_vid(rdev);
488 if (ret)
489 return ret;
490 ret = ci_populate_svi_load_line(rdev);
491 if (ret)
492 return ret;
493 ret = ci_populate_tdc_limit(rdev);
494 if (ret)
495 return ret;
496 ret = ci_populate_dw8(rdev);
497 if (ret)
498 return ret;
499 ret = ci_populate_fuzzy_fan(rdev);
500 if (ret)
501 return ret;
502 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
503 if (ret)
504 return ret;
505 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
506 if (ret)
507 return ret;
508 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
509 (u8 *)&pi->smc_powertune_table,
510 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
511 if (ret)
512 return ret;
513 }
514
515 return 0;
516 }
517
ci_do_enable_didt(struct radeon_device * rdev,const bool enable)518 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
519 {
520 struct ci_power_info *pi = ci_get_pi(rdev);
521 u32 data;
522
523 if (pi->caps_sq_ramping) {
524 data = RREG32_DIDT(DIDT_SQ_CTRL0);
525 if (enable)
526 data |= DIDT_CTRL_EN;
527 else
528 data &= ~DIDT_CTRL_EN;
529 WREG32_DIDT(DIDT_SQ_CTRL0, data);
530 }
531
532 if (pi->caps_db_ramping) {
533 data = RREG32_DIDT(DIDT_DB_CTRL0);
534 if (enable)
535 data |= DIDT_CTRL_EN;
536 else
537 data &= ~DIDT_CTRL_EN;
538 WREG32_DIDT(DIDT_DB_CTRL0, data);
539 }
540
541 if (pi->caps_td_ramping) {
542 data = RREG32_DIDT(DIDT_TD_CTRL0);
543 if (enable)
544 data |= DIDT_CTRL_EN;
545 else
546 data &= ~DIDT_CTRL_EN;
547 WREG32_DIDT(DIDT_TD_CTRL0, data);
548 }
549
550 if (pi->caps_tcp_ramping) {
551 data = RREG32_DIDT(DIDT_TCP_CTRL0);
552 if (enable)
553 data |= DIDT_CTRL_EN;
554 else
555 data &= ~DIDT_CTRL_EN;
556 WREG32_DIDT(DIDT_TCP_CTRL0, data);
557 }
558 }
559
ci_program_pt_config_registers(struct radeon_device * rdev,const struct ci_pt_config_reg * cac_config_regs)560 static int ci_program_pt_config_registers(struct radeon_device *rdev,
561 const struct ci_pt_config_reg *cac_config_regs)
562 {
563 const struct ci_pt_config_reg *config_regs = cac_config_regs;
564 u32 data;
565 u32 cache = 0;
566
567 if (config_regs == NULL)
568 return -EINVAL;
569
570 while (config_regs->offset != 0xFFFFFFFF) {
571 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
572 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
573 } else {
574 switch (config_regs->type) {
575 case CISLANDS_CONFIGREG_SMC_IND:
576 data = RREG32_SMC(config_regs->offset);
577 break;
578 case CISLANDS_CONFIGREG_DIDT_IND:
579 data = RREG32_DIDT(config_regs->offset);
580 break;
581 default:
582 data = RREG32(config_regs->offset << 2);
583 break;
584 }
585
586 data &= ~config_regs->mask;
587 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
588 data |= cache;
589
590 switch (config_regs->type) {
591 case CISLANDS_CONFIGREG_SMC_IND:
592 WREG32_SMC(config_regs->offset, data);
593 break;
594 case CISLANDS_CONFIGREG_DIDT_IND:
595 WREG32_DIDT(config_regs->offset, data);
596 break;
597 default:
598 WREG32(config_regs->offset << 2, data);
599 break;
600 }
601 cache = 0;
602 }
603 config_regs++;
604 }
605 return 0;
606 }
607
ci_enable_didt(struct radeon_device * rdev,bool enable)608 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
609 {
610 struct ci_power_info *pi = ci_get_pi(rdev);
611 int ret;
612
613 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
614 pi->caps_td_ramping || pi->caps_tcp_ramping) {
615 cik_enter_rlc_safe_mode(rdev);
616
617 if (enable) {
618 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
619 if (ret) {
620 cik_exit_rlc_safe_mode(rdev);
621 return ret;
622 }
623 }
624
625 ci_do_enable_didt(rdev, enable);
626
627 cik_exit_rlc_safe_mode(rdev);
628 }
629
630 return 0;
631 }
632
ci_enable_power_containment(struct radeon_device * rdev,bool enable)633 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
634 {
635 struct ci_power_info *pi = ci_get_pi(rdev);
636 PPSMC_Result smc_result;
637 int ret = 0;
638
639 if (enable) {
640 pi->power_containment_features = 0;
641 if (pi->caps_power_containment) {
642 if (pi->enable_bapm_feature) {
643 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
644 if (smc_result != PPSMC_Result_OK)
645 ret = -EINVAL;
646 else
647 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
648 }
649
650 if (pi->enable_tdc_limit_feature) {
651 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
652 if (smc_result != PPSMC_Result_OK)
653 ret = -EINVAL;
654 else
655 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
656 }
657
658 if (pi->enable_pkg_pwr_tracking_feature) {
659 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
660 if (smc_result != PPSMC_Result_OK) {
661 ret = -EINVAL;
662 } else {
663 struct radeon_cac_tdp_table *cac_tdp_table =
664 rdev->pm.dpm.dyn_state.cac_tdp_table;
665 u32 default_pwr_limit =
666 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
667
668 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
669
670 ci_set_power_limit(rdev, default_pwr_limit);
671 }
672 }
673 }
674 } else {
675 if (pi->caps_power_containment && pi->power_containment_features) {
676 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
677 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
678
679 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
680 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
681
682 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
683 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
684 pi->power_containment_features = 0;
685 }
686 }
687
688 return ret;
689 }
690
ci_enable_smc_cac(struct radeon_device * rdev,bool enable)691 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
692 {
693 struct ci_power_info *pi = ci_get_pi(rdev);
694 PPSMC_Result smc_result;
695 int ret = 0;
696
697 if (pi->caps_cac) {
698 if (enable) {
699 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
700 if (smc_result != PPSMC_Result_OK) {
701 ret = -EINVAL;
702 pi->cac_enabled = false;
703 } else {
704 pi->cac_enabled = true;
705 }
706 } else if (pi->cac_enabled) {
707 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
708 pi->cac_enabled = false;
709 }
710 }
711
712 return ret;
713 }
714
ci_enable_thermal_based_sclk_dpm(struct radeon_device * rdev,bool enable)715 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev,
716 bool enable)
717 {
718 struct ci_power_info *pi = ci_get_pi(rdev);
719 PPSMC_Result smc_result = PPSMC_Result_OK;
720
721 if (pi->thermal_sclk_dpm_enabled) {
722 if (enable)
723 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM);
724 else
725 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM);
726 }
727
728 if (smc_result == PPSMC_Result_OK)
729 return 0;
730 else
731 return -EINVAL;
732 }
733
ci_power_control_set_level(struct radeon_device * rdev)734 static int ci_power_control_set_level(struct radeon_device *rdev)
735 {
736 struct ci_power_info *pi = ci_get_pi(rdev);
737 struct radeon_cac_tdp_table *cac_tdp_table =
738 rdev->pm.dpm.dyn_state.cac_tdp_table;
739 s32 adjust_percent;
740 s32 target_tdp;
741 int ret = 0;
742 bool adjust_polarity = false; /* ??? */
743
744 if (pi->caps_power_containment) {
745 adjust_percent = adjust_polarity ?
746 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
747 target_tdp = ((100 + adjust_percent) *
748 (s32)cac_tdp_table->configurable_tdp) / 100;
749
750 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
751 }
752
753 return ret;
754 }
755
ci_dpm_powergate_uvd(struct radeon_device * rdev,bool gate)756 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
757 {
758 struct ci_power_info *pi = ci_get_pi(rdev);
759
760 if (pi->uvd_power_gated == gate)
761 return;
762
763 pi->uvd_power_gated = gate;
764
765 ci_update_uvd_dpm(rdev, gate);
766 }
767
ci_dpm_vblank_too_short(struct radeon_device * rdev)768 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
769 {
770 struct ci_power_info *pi = ci_get_pi(rdev);
771 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
772 u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
773
774 /* disable mclk switching if the refresh is >120Hz, even if the
775 * blanking period would allow it
776 */
777 if (r600_dpm_get_vrefresh(rdev) > 120)
778 return true;
779
780 /* disable mclk switching if the refresh is >120Hz, even if the
781 * blanking period would allow it
782 */
783 if (r600_dpm_get_vrefresh(rdev) > 120)
784 return true;
785
786 /* disable mclk switching if the refresh is >120Hz, even if the
787 * blanking period would allow it
788 */
789 if (r600_dpm_get_vrefresh(rdev) > 120)
790 return true;
791
792 /* disable mclk switching if the refresh is >120Hz, even if the
793 * blanking period would allow it
794 */
795 if (r600_dpm_get_vrefresh(rdev) > 120)
796 return true;
797
798 /* disable mclk switching if the refresh is >120Hz, even if the
799 * blanking period would allow it
800 */
801 if (r600_dpm_get_vrefresh(rdev) > 120)
802 return true;
803
804 /* disable mclk switching if the refresh is >120Hz, even if the
805 * blanking period would allow it
806 */
807 if (r600_dpm_get_vrefresh(rdev) > 120)
808 return true;
809
810 /* disable mclk switching if the refresh is >120Hz, even if the
811 * blanking period would allow it
812 */
813 if (r600_dpm_get_vrefresh(rdev) > 120)
814 return true;
815
816 /* disable mclk switching if the refresh is >120Hz, even if the
817 * blanking period would allow it
818 */
819 if (r600_dpm_get_vrefresh(rdev) > 120)
820 return true;
821
822 if (vblank_time < switch_limit)
823 return true;
824 else
825 return false;
826
827 }
828
ci_apply_state_adjust_rules(struct radeon_device * rdev,struct radeon_ps * rps)829 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
830 struct radeon_ps *rps)
831 {
832 struct ci_ps *ps = ci_get_ps(rps);
833 struct ci_power_info *pi = ci_get_pi(rdev);
834 struct radeon_clock_and_voltage_limits *max_limits;
835 bool disable_mclk_switching;
836 u32 sclk, mclk;
837 int i;
838
839 if (rps->vce_active) {
840 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
841 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
842 } else {
843 rps->evclk = 0;
844 rps->ecclk = 0;
845 }
846
847 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
848 ci_dpm_vblank_too_short(rdev))
849 disable_mclk_switching = true;
850 else
851 disable_mclk_switching = false;
852
853 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
854 pi->battery_state = true;
855 else
856 pi->battery_state = false;
857
858 if (rdev->pm.dpm.ac_power)
859 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
860 else
861 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
862
863 if (rdev->pm.dpm.ac_power == false) {
864 for (i = 0; i < ps->performance_level_count; i++) {
865 if (ps->performance_levels[i].mclk > max_limits->mclk)
866 ps->performance_levels[i].mclk = max_limits->mclk;
867 if (ps->performance_levels[i].sclk > max_limits->sclk)
868 ps->performance_levels[i].sclk = max_limits->sclk;
869 }
870 }
871
872 /* XXX validate the min clocks required for display */
873
874 if (disable_mclk_switching) {
875 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
876 sclk = ps->performance_levels[0].sclk;
877 } else {
878 mclk = ps->performance_levels[0].mclk;
879 sclk = ps->performance_levels[0].sclk;
880 }
881
882 if (rps->vce_active) {
883 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
884 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
885 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
886 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
887 }
888
889 ps->performance_levels[0].sclk = sclk;
890 ps->performance_levels[0].mclk = mclk;
891
892 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
893 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
894
895 if (disable_mclk_switching) {
896 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
897 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
898 } else {
899 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
900 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
901 }
902 }
903
ci_thermal_set_temperature_range(struct radeon_device * rdev,int min_temp,int max_temp)904 static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
905 int min_temp, int max_temp)
906 {
907 int low_temp = 0 * 1000;
908 int high_temp = 255 * 1000;
909 u32 tmp;
910
911 if (low_temp < min_temp)
912 low_temp = min_temp;
913 if (high_temp > max_temp)
914 high_temp = max_temp;
915 if (high_temp < low_temp) {
916 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
917 return -EINVAL;
918 }
919
920 tmp = RREG32_SMC(CG_THERMAL_INT);
921 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
922 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
923 CI_DIG_THERM_INTL(low_temp / 1000);
924 WREG32_SMC(CG_THERMAL_INT, tmp);
925
926 #if 0
927 /* XXX: need to figure out how to handle this properly */
928 tmp = RREG32_SMC(CG_THERMAL_CTRL);
929 tmp &= DIG_THERM_DPM_MASK;
930 tmp |= DIG_THERM_DPM(high_temp / 1000);
931 WREG32_SMC(CG_THERMAL_CTRL, tmp);
932 #endif
933
934 rdev->pm.dpm.thermal.min_temp = low_temp;
935 rdev->pm.dpm.thermal.max_temp = high_temp;
936
937 return 0;
938 }
939
ci_thermal_enable_alert(struct radeon_device * rdev,bool enable)940 static int ci_thermal_enable_alert(struct radeon_device *rdev,
941 bool enable)
942 {
943 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
944 PPSMC_Result result;
945
946 if (enable) {
947 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
948 WREG32_SMC(CG_THERMAL_INT, thermal_int);
949 rdev->irq.dpm_thermal = false;
950 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
951 if (result != PPSMC_Result_OK) {
952 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
953 return -EINVAL;
954 }
955 } else {
956 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
957 WREG32_SMC(CG_THERMAL_INT, thermal_int);
958 rdev->irq.dpm_thermal = true;
959 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
960 if (result != PPSMC_Result_OK) {
961 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
962 return -EINVAL;
963 }
964 }
965
966 return 0;
967 }
968
ci_fan_ctrl_set_static_mode(struct radeon_device * rdev,u32 mode)969 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
970 {
971 struct ci_power_info *pi = ci_get_pi(rdev);
972 u32 tmp;
973
974 if (pi->fan_ctrl_is_in_default_mode) {
975 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
976 pi->fan_ctrl_default_mode = tmp;
977 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
978 pi->t_min = tmp;
979 pi->fan_ctrl_is_in_default_mode = false;
980 }
981
982 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
983 tmp |= TMIN(0);
984 WREG32_SMC(CG_FDO_CTRL2, tmp);
985
986 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
987 tmp |= FDO_PWM_MODE(mode);
988 WREG32_SMC(CG_FDO_CTRL2, tmp);
989 }
990
ci_thermal_setup_fan_table(struct radeon_device * rdev)991 static int ci_thermal_setup_fan_table(struct radeon_device *rdev)
992 {
993 struct ci_power_info *pi = ci_get_pi(rdev);
994 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
995 u32 duty100;
996 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
997 u16 fdo_min, slope1, slope2;
998 u32 reference_clock, tmp;
999 int ret;
1000 u64 tmp64;
1001
1002 if (!pi->fan_table_start) {
1003 rdev->pm.dpm.fan.ucode_fan_control = false;
1004 return 0;
1005 }
1006
1007 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1008
1009 if (duty100 == 0) {
1010 rdev->pm.dpm.fan.ucode_fan_control = false;
1011 return 0;
1012 }
1013
1014 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
1015 do_div(tmp64, 10000);
1016 fdo_min = (u16)tmp64;
1017
1018 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
1019 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
1020
1021 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
1022 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
1023
1024 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
1025 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
1026
1027 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
1028 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
1029 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
1030
1031 fan_table.Slope1 = cpu_to_be16(slope1);
1032 fan_table.Slope2 = cpu_to_be16(slope2);
1033
1034 fan_table.FdoMin = cpu_to_be16(fdo_min);
1035
1036 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
1037
1038 fan_table.HystUp = cpu_to_be16(1);
1039
1040 fan_table.HystSlope = cpu_to_be16(1);
1041
1042 fan_table.TempRespLim = cpu_to_be16(5);
1043
1044 reference_clock = radeon_get_xclk(rdev);
1045
1046 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
1047 reference_clock) / 1600);
1048
1049 fan_table.FdoMax = cpu_to_be16((u16)duty100);
1050
1051 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
1052 fan_table.TempSrc = (uint8_t)tmp;
1053
1054 ret = ci_copy_bytes_to_smc(rdev,
1055 pi->fan_table_start,
1056 (u8 *)(&fan_table),
1057 sizeof(fan_table),
1058 pi->sram_end);
1059
1060 if (ret) {
1061 DRM_ERROR("Failed to load fan table to the SMC.");
1062 rdev->pm.dpm.fan.ucode_fan_control = false;
1063 }
1064
1065 return 0;
1066 }
1067
ci_fan_ctrl_start_smc_fan_control(struct radeon_device * rdev)1068 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
1069 {
1070 struct ci_power_info *pi = ci_get_pi(rdev);
1071 PPSMC_Result ret;
1072
1073 if (pi->caps_od_fuzzy_fan_control_support) {
1074 ret = ci_send_msg_to_smc_with_parameter(rdev,
1075 PPSMC_StartFanControl,
1076 FAN_CONTROL_FUZZY);
1077 if (ret != PPSMC_Result_OK)
1078 return -EINVAL;
1079 ret = ci_send_msg_to_smc_with_parameter(rdev,
1080 PPSMC_MSG_SetFanPwmMax,
1081 rdev->pm.dpm.fan.default_max_fan_pwm);
1082 if (ret != PPSMC_Result_OK)
1083 return -EINVAL;
1084 } else {
1085 ret = ci_send_msg_to_smc_with_parameter(rdev,
1086 PPSMC_StartFanControl,
1087 FAN_CONTROL_TABLE);
1088 if (ret != PPSMC_Result_OK)
1089 return -EINVAL;
1090 }
1091
1092 pi->fan_is_controlled_by_smc = true;
1093 return 0;
1094 }
1095
ci_fan_ctrl_stop_smc_fan_control(struct radeon_device * rdev)1096 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
1097 {
1098 PPSMC_Result ret;
1099 struct ci_power_info *pi = ci_get_pi(rdev);
1100
1101 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl);
1102 if (ret == PPSMC_Result_OK) {
1103 pi->fan_is_controlled_by_smc = false;
1104 return 0;
1105 } else
1106 return -EINVAL;
1107 }
1108
ci_fan_ctrl_get_fan_speed_percent(struct radeon_device * rdev,u32 * speed)1109 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
1110 u32 *speed)
1111 {
1112 u32 duty, duty100;
1113 u64 tmp64;
1114
1115 if (rdev->pm.no_fan)
1116 return -ENOENT;
1117
1118 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1119 duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
1120
1121 if (duty100 == 0)
1122 return -EINVAL;
1123
1124 tmp64 = (u64)duty * 100;
1125 do_div(tmp64, duty100);
1126 *speed = (u32)tmp64;
1127
1128 if (*speed > 100)
1129 *speed = 100;
1130
1131 return 0;
1132 }
1133
ci_fan_ctrl_set_fan_speed_percent(struct radeon_device * rdev,u32 speed)1134 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
1135 u32 speed)
1136 {
1137 u32 tmp;
1138 u32 duty, duty100;
1139 u64 tmp64;
1140 struct ci_power_info *pi = ci_get_pi(rdev);
1141
1142 if (rdev->pm.no_fan)
1143 return -ENOENT;
1144
1145 if (pi->fan_is_controlled_by_smc)
1146 return -EINVAL;
1147
1148 if (speed > 100)
1149 return -EINVAL;
1150
1151 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1152
1153 if (duty100 == 0)
1154 return -EINVAL;
1155
1156 tmp64 = (u64)speed * duty100;
1157 do_div(tmp64, 100);
1158 duty = (u32)tmp64;
1159
1160 tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
1161 tmp |= FDO_STATIC_DUTY(duty);
1162 WREG32_SMC(CG_FDO_CTRL0, tmp);
1163
1164 return 0;
1165 }
1166
ci_fan_ctrl_set_mode(struct radeon_device * rdev,u32 mode)1167 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
1168 {
1169 if (mode) {
1170 /* stop auto-manage */
1171 if (rdev->pm.dpm.fan.ucode_fan_control)
1172 ci_fan_ctrl_stop_smc_fan_control(rdev);
1173 ci_fan_ctrl_set_static_mode(rdev, mode);
1174 } else {
1175 /* restart auto-manage */
1176 if (rdev->pm.dpm.fan.ucode_fan_control)
1177 ci_thermal_start_smc_fan_control(rdev);
1178 else
1179 ci_fan_ctrl_set_default_mode(rdev);
1180 }
1181 }
1182
ci_fan_ctrl_get_mode(struct radeon_device * rdev)1183 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev)
1184 {
1185 struct ci_power_info *pi = ci_get_pi(rdev);
1186 u32 tmp;
1187
1188 if (pi->fan_is_controlled_by_smc)
1189 return 0;
1190
1191 tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
1192 return (tmp >> FDO_PWM_MODE_SHIFT);
1193 }
1194
1195 #if 0
1196 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
1197 u32 *speed)
1198 {
1199 u32 tach_period;
1200 u32 xclk = radeon_get_xclk(rdev);
1201
1202 if (rdev->pm.no_fan)
1203 return -ENOENT;
1204
1205 if (rdev->pm.fan_pulses_per_revolution == 0)
1206 return -ENOENT;
1207
1208 tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
1209 if (tach_period == 0)
1210 return -ENOENT;
1211
1212 *speed = 60 * xclk * 10000 / tach_period;
1213
1214 return 0;
1215 }
1216
1217 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
1218 u32 speed)
1219 {
1220 u32 tach_period, tmp;
1221 u32 xclk = radeon_get_xclk(rdev);
1222
1223 if (rdev->pm.no_fan)
1224 return -ENOENT;
1225
1226 if (rdev->pm.fan_pulses_per_revolution == 0)
1227 return -ENOENT;
1228
1229 if ((speed < rdev->pm.fan_min_rpm) ||
1230 (speed > rdev->pm.fan_max_rpm))
1231 return -EINVAL;
1232
1233 if (rdev->pm.dpm.fan.ucode_fan_control)
1234 ci_fan_ctrl_stop_smc_fan_control(rdev);
1235
1236 tach_period = 60 * xclk * 10000 / (8 * speed);
1237 tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
1238 tmp |= TARGET_PERIOD(tach_period);
1239 WREG32_SMC(CG_TACH_CTRL, tmp);
1240
1241 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
1242
1243 return 0;
1244 }
1245 #endif
1246
ci_fan_ctrl_set_default_mode(struct radeon_device * rdev)1247 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev)
1248 {
1249 struct ci_power_info *pi = ci_get_pi(rdev);
1250 u32 tmp;
1251
1252 if (!pi->fan_ctrl_is_in_default_mode) {
1253 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
1254 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);
1255 WREG32_SMC(CG_FDO_CTRL2, tmp);
1256
1257 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
1258 tmp |= TMIN(pi->t_min);
1259 WREG32_SMC(CG_FDO_CTRL2, tmp);
1260 pi->fan_ctrl_is_in_default_mode = true;
1261 }
1262 }
1263
ci_thermal_start_smc_fan_control(struct radeon_device * rdev)1264 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev)
1265 {
1266 if (rdev->pm.dpm.fan.ucode_fan_control) {
1267 ci_fan_ctrl_start_smc_fan_control(rdev);
1268 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
1269 }
1270 }
1271
ci_thermal_initialize(struct radeon_device * rdev)1272 static void ci_thermal_initialize(struct radeon_device *rdev)
1273 {
1274 u32 tmp;
1275
1276 if (rdev->pm.fan_pulses_per_revolution) {
1277 tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
1278 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
1279 WREG32_SMC(CG_TACH_CTRL, tmp);
1280 }
1281
1282 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
1283 tmp |= TACH_PWM_RESP_RATE(0x28);
1284 WREG32_SMC(CG_FDO_CTRL2, tmp);
1285 }
1286
ci_thermal_start_thermal_controller(struct radeon_device * rdev)1287 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev)
1288 {
1289 int ret;
1290
1291 ci_thermal_initialize(rdev);
1292 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1293 if (ret)
1294 return ret;
1295 ret = ci_thermal_enable_alert(rdev, true);
1296 if (ret)
1297 return ret;
1298 if (rdev->pm.dpm.fan.ucode_fan_control) {
1299 ret = ci_thermal_setup_fan_table(rdev);
1300 if (ret)
1301 return ret;
1302 ci_thermal_start_smc_fan_control(rdev);
1303 }
1304
1305 return 0;
1306 }
1307
ci_thermal_stop_thermal_controller(struct radeon_device * rdev)1308 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev)
1309 {
1310 if (!rdev->pm.no_fan)
1311 ci_fan_ctrl_set_default_mode(rdev);
1312 }
1313
1314 #if 0
1315 static int ci_read_smc_soft_register(struct radeon_device *rdev,
1316 u16 reg_offset, u32 *value)
1317 {
1318 struct ci_power_info *pi = ci_get_pi(rdev);
1319
1320 return ci_read_smc_sram_dword(rdev,
1321 pi->soft_regs_start + reg_offset,
1322 value, pi->sram_end);
1323 }
1324 #endif
1325
ci_write_smc_soft_register(struct radeon_device * rdev,u16 reg_offset,u32 value)1326 static int ci_write_smc_soft_register(struct radeon_device *rdev,
1327 u16 reg_offset, u32 value)
1328 {
1329 struct ci_power_info *pi = ci_get_pi(rdev);
1330
1331 return ci_write_smc_sram_dword(rdev,
1332 pi->soft_regs_start + reg_offset,
1333 value, pi->sram_end);
1334 }
1335
ci_init_fps_limits(struct radeon_device * rdev)1336 static void ci_init_fps_limits(struct radeon_device *rdev)
1337 {
1338 struct ci_power_info *pi = ci_get_pi(rdev);
1339 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1340
1341 if (pi->caps_fps) {
1342 u16 tmp;
1343
1344 tmp = 45;
1345 table->FpsHighT = cpu_to_be16(tmp);
1346
1347 tmp = 30;
1348 table->FpsLowT = cpu_to_be16(tmp);
1349 }
1350 }
1351
ci_update_sclk_t(struct radeon_device * rdev)1352 static int ci_update_sclk_t(struct radeon_device *rdev)
1353 {
1354 struct ci_power_info *pi = ci_get_pi(rdev);
1355 int ret = 0;
1356 u32 low_sclk_interrupt_t = 0;
1357
1358 if (pi->caps_sclk_throttle_low_notification) {
1359 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1360
1361 ret = ci_copy_bytes_to_smc(rdev,
1362 pi->dpm_table_start +
1363 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1364 (u8 *)&low_sclk_interrupt_t,
1365 sizeof(u32), pi->sram_end);
1366
1367 }
1368
1369 return ret;
1370 }
1371
ci_get_leakage_voltages(struct radeon_device * rdev)1372 static void ci_get_leakage_voltages(struct radeon_device *rdev)
1373 {
1374 struct ci_power_info *pi = ci_get_pi(rdev);
1375 u16 leakage_id, virtual_voltage_id;
1376 u16 vddc, vddci;
1377 int i;
1378
1379 pi->vddc_leakage.count = 0;
1380 pi->vddci_leakage.count = 0;
1381
1382 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1383 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1384 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1385 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
1386 continue;
1387 if (vddc != 0 && vddc != virtual_voltage_id) {
1388 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1389 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1390 pi->vddc_leakage.count++;
1391 }
1392 }
1393 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
1394 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1395 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1396 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
1397 virtual_voltage_id,
1398 leakage_id) == 0) {
1399 if (vddc != 0 && vddc != virtual_voltage_id) {
1400 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1401 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1402 pi->vddc_leakage.count++;
1403 }
1404 if (vddci != 0 && vddci != virtual_voltage_id) {
1405 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1406 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1407 pi->vddci_leakage.count++;
1408 }
1409 }
1410 }
1411 }
1412 }
1413
ci_set_dpm_event_sources(struct radeon_device * rdev,u32 sources)1414 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1415 {
1416 struct ci_power_info *pi = ci_get_pi(rdev);
1417 bool want_thermal_protection;
1418 enum radeon_dpm_event_src dpm_event_src;
1419 u32 tmp;
1420
1421 switch (sources) {
1422 case 0:
1423 default:
1424 want_thermal_protection = false;
1425 break;
1426 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1427 want_thermal_protection = true;
1428 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1429 break;
1430 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1431 want_thermal_protection = true;
1432 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1433 break;
1434 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1435 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1436 want_thermal_protection = true;
1437 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1438 break;
1439 }
1440
1441 if (want_thermal_protection) {
1442 #if 0
1443 /* XXX: need to figure out how to handle this properly */
1444 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1445 tmp &= DPM_EVENT_SRC_MASK;
1446 tmp |= DPM_EVENT_SRC(dpm_event_src);
1447 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1448 #endif
1449
1450 tmp = RREG32_SMC(GENERAL_PWRMGT);
1451 if (pi->thermal_protection)
1452 tmp &= ~THERMAL_PROTECTION_DIS;
1453 else
1454 tmp |= THERMAL_PROTECTION_DIS;
1455 WREG32_SMC(GENERAL_PWRMGT, tmp);
1456 } else {
1457 tmp = RREG32_SMC(GENERAL_PWRMGT);
1458 tmp |= THERMAL_PROTECTION_DIS;
1459 WREG32_SMC(GENERAL_PWRMGT, tmp);
1460 }
1461 }
1462
ci_enable_auto_throttle_source(struct radeon_device * rdev,enum radeon_dpm_auto_throttle_src source,bool enable)1463 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1464 enum radeon_dpm_auto_throttle_src source,
1465 bool enable)
1466 {
1467 struct ci_power_info *pi = ci_get_pi(rdev);
1468
1469 if (enable) {
1470 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1471 pi->active_auto_throttle_sources |= 1 << source;
1472 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1473 }
1474 } else {
1475 if (pi->active_auto_throttle_sources & (1 << source)) {
1476 pi->active_auto_throttle_sources &= ~(1 << source);
1477 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1478 }
1479 }
1480 }
1481
ci_enable_vr_hot_gpio_interrupt(struct radeon_device * rdev)1482 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1483 {
1484 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1485 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1486 }
1487
ci_unfreeze_sclk_mclk_dpm(struct radeon_device * rdev)1488 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1489 {
1490 struct ci_power_info *pi = ci_get_pi(rdev);
1491 PPSMC_Result smc_result;
1492
1493 if (!pi->need_update_smu7_dpm_table)
1494 return 0;
1495
1496 if ((!pi->sclk_dpm_key_disabled) &&
1497 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1498 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1499 if (smc_result != PPSMC_Result_OK)
1500 return -EINVAL;
1501 }
1502
1503 if ((!pi->mclk_dpm_key_disabled) &&
1504 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1505 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1506 if (smc_result != PPSMC_Result_OK)
1507 return -EINVAL;
1508 }
1509
1510 pi->need_update_smu7_dpm_table = 0;
1511 return 0;
1512 }
1513
ci_enable_sclk_mclk_dpm(struct radeon_device * rdev,bool enable)1514 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1515 {
1516 struct ci_power_info *pi = ci_get_pi(rdev);
1517 PPSMC_Result smc_result;
1518
1519 if (enable) {
1520 if (!pi->sclk_dpm_key_disabled) {
1521 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1522 if (smc_result != PPSMC_Result_OK)
1523 return -EINVAL;
1524 }
1525
1526 if (!pi->mclk_dpm_key_disabled) {
1527 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1528 if (smc_result != PPSMC_Result_OK)
1529 return -EINVAL;
1530
1531 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1532
1533 WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1534 WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1535 WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1536
1537 udelay(10);
1538
1539 WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1540 WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1541 WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1542 }
1543 } else {
1544 if (!pi->sclk_dpm_key_disabled) {
1545 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1546 if (smc_result != PPSMC_Result_OK)
1547 return -EINVAL;
1548 }
1549
1550 if (!pi->mclk_dpm_key_disabled) {
1551 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1552 if (smc_result != PPSMC_Result_OK)
1553 return -EINVAL;
1554 }
1555 }
1556
1557 return 0;
1558 }
1559
ci_start_dpm(struct radeon_device * rdev)1560 static int ci_start_dpm(struct radeon_device *rdev)
1561 {
1562 struct ci_power_info *pi = ci_get_pi(rdev);
1563 PPSMC_Result smc_result;
1564 int ret;
1565 u32 tmp;
1566
1567 tmp = RREG32_SMC(GENERAL_PWRMGT);
1568 tmp |= GLOBAL_PWRMGT_EN;
1569 WREG32_SMC(GENERAL_PWRMGT, tmp);
1570
1571 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1572 tmp |= DYNAMIC_PM_EN;
1573 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1574
1575 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1576
1577 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1578
1579 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1580 if (smc_result != PPSMC_Result_OK)
1581 return -EINVAL;
1582
1583 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1584 if (ret)
1585 return ret;
1586
1587 if (!pi->pcie_dpm_key_disabled) {
1588 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1589 if (smc_result != PPSMC_Result_OK)
1590 return -EINVAL;
1591 }
1592
1593 return 0;
1594 }
1595
ci_freeze_sclk_mclk_dpm(struct radeon_device * rdev)1596 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1597 {
1598 struct ci_power_info *pi = ci_get_pi(rdev);
1599 PPSMC_Result smc_result;
1600
1601 if (!pi->need_update_smu7_dpm_table)
1602 return 0;
1603
1604 if ((!pi->sclk_dpm_key_disabled) &&
1605 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1606 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1607 if (smc_result != PPSMC_Result_OK)
1608 return -EINVAL;
1609 }
1610
1611 if ((!pi->mclk_dpm_key_disabled) &&
1612 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1613 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1614 if (smc_result != PPSMC_Result_OK)
1615 return -EINVAL;
1616 }
1617
1618 return 0;
1619 }
1620
ci_stop_dpm(struct radeon_device * rdev)1621 static int ci_stop_dpm(struct radeon_device *rdev)
1622 {
1623 struct ci_power_info *pi = ci_get_pi(rdev);
1624 PPSMC_Result smc_result;
1625 int ret;
1626 u32 tmp;
1627
1628 tmp = RREG32_SMC(GENERAL_PWRMGT);
1629 tmp &= ~GLOBAL_PWRMGT_EN;
1630 WREG32_SMC(GENERAL_PWRMGT, tmp);
1631
1632 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1633 tmp &= ~DYNAMIC_PM_EN;
1634 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1635
1636 if (!pi->pcie_dpm_key_disabled) {
1637 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1638 if (smc_result != PPSMC_Result_OK)
1639 return -EINVAL;
1640 }
1641
1642 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1643 if (ret)
1644 return ret;
1645
1646 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1647 if (smc_result != PPSMC_Result_OK)
1648 return -EINVAL;
1649
1650 return 0;
1651 }
1652
ci_enable_sclk_control(struct radeon_device * rdev,bool enable)1653 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1654 {
1655 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1656
1657 if (enable)
1658 tmp &= ~SCLK_PWRMGT_OFF;
1659 else
1660 tmp |= SCLK_PWRMGT_OFF;
1661 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1662 }
1663
1664 #if 0
1665 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1666 bool ac_power)
1667 {
1668 struct ci_power_info *pi = ci_get_pi(rdev);
1669 struct radeon_cac_tdp_table *cac_tdp_table =
1670 rdev->pm.dpm.dyn_state.cac_tdp_table;
1671 u32 power_limit;
1672
1673 if (ac_power)
1674 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1675 else
1676 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1677
1678 ci_set_power_limit(rdev, power_limit);
1679
1680 if (pi->caps_automatic_dc_transition) {
1681 if (ac_power)
1682 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1683 else
1684 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1685 }
1686
1687 return 0;
1688 }
1689 #endif
1690
ci_send_msg_to_smc(struct radeon_device * rdev,PPSMC_Msg msg)1691 static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
1692 {
1693 u32 tmp;
1694 int i;
1695
1696 if (!ci_is_smc_running(rdev))
1697 return PPSMC_Result_Failed;
1698
1699 WREG32(SMC_MESSAGE_0, msg);
1700
1701 for (i = 0; i < rdev->usec_timeout; i++) {
1702 tmp = RREG32(SMC_RESP_0);
1703 if (tmp != 0)
1704 break;
1705 udelay(1);
1706 }
1707 tmp = RREG32(SMC_RESP_0);
1708
1709 return (PPSMC_Result)tmp;
1710 }
1711
ci_send_msg_to_smc_with_parameter(struct radeon_device * rdev,PPSMC_Msg msg,u32 parameter)1712 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1713 PPSMC_Msg msg, u32 parameter)
1714 {
1715 WREG32(SMC_MSG_ARG_0, parameter);
1716 return ci_send_msg_to_smc(rdev, msg);
1717 }
1718
ci_send_msg_to_smc_return_parameter(struct radeon_device * rdev,PPSMC_Msg msg,u32 * parameter)1719 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1720 PPSMC_Msg msg, u32 *parameter)
1721 {
1722 PPSMC_Result smc_result;
1723
1724 smc_result = ci_send_msg_to_smc(rdev, msg);
1725
1726 if ((smc_result == PPSMC_Result_OK) && parameter)
1727 *parameter = RREG32(SMC_MSG_ARG_0);
1728
1729 return smc_result;
1730 }
1731
ci_dpm_force_state_sclk(struct radeon_device * rdev,u32 n)1732 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1733 {
1734 struct ci_power_info *pi = ci_get_pi(rdev);
1735
1736 if (!pi->sclk_dpm_key_disabled) {
1737 PPSMC_Result smc_result =
1738 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1739 if (smc_result != PPSMC_Result_OK)
1740 return -EINVAL;
1741 }
1742
1743 return 0;
1744 }
1745
ci_dpm_force_state_mclk(struct radeon_device * rdev,u32 n)1746 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1747 {
1748 struct ci_power_info *pi = ci_get_pi(rdev);
1749
1750 if (!pi->mclk_dpm_key_disabled) {
1751 PPSMC_Result smc_result =
1752 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1753 if (smc_result != PPSMC_Result_OK)
1754 return -EINVAL;
1755 }
1756
1757 return 0;
1758 }
1759
ci_dpm_force_state_pcie(struct radeon_device * rdev,u32 n)1760 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1761 {
1762 struct ci_power_info *pi = ci_get_pi(rdev);
1763
1764 if (!pi->pcie_dpm_key_disabled) {
1765 PPSMC_Result smc_result =
1766 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1767 if (smc_result != PPSMC_Result_OK)
1768 return -EINVAL;
1769 }
1770
1771 return 0;
1772 }
1773
ci_set_power_limit(struct radeon_device * rdev,u32 n)1774 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1775 {
1776 struct ci_power_info *pi = ci_get_pi(rdev);
1777
1778 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1779 PPSMC_Result smc_result =
1780 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1781 if (smc_result != PPSMC_Result_OK)
1782 return -EINVAL;
1783 }
1784
1785 return 0;
1786 }
1787
ci_set_overdrive_target_tdp(struct radeon_device * rdev,u32 target_tdp)1788 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1789 u32 target_tdp)
1790 {
1791 PPSMC_Result smc_result =
1792 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1793 if (smc_result != PPSMC_Result_OK)
1794 return -EINVAL;
1795 return 0;
1796 }
1797
1798 #if 0
1799 static int ci_set_boot_state(struct radeon_device *rdev)
1800 {
1801 return ci_enable_sclk_mclk_dpm(rdev, false);
1802 }
1803 #endif
1804
ci_get_average_sclk_freq(struct radeon_device * rdev)1805 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1806 {
1807 u32 sclk_freq;
1808 PPSMC_Result smc_result =
1809 ci_send_msg_to_smc_return_parameter(rdev,
1810 PPSMC_MSG_API_GetSclkFrequency,
1811 &sclk_freq);
1812 if (smc_result != PPSMC_Result_OK)
1813 sclk_freq = 0;
1814
1815 return sclk_freq;
1816 }
1817
ci_get_average_mclk_freq(struct radeon_device * rdev)1818 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1819 {
1820 u32 mclk_freq;
1821 PPSMC_Result smc_result =
1822 ci_send_msg_to_smc_return_parameter(rdev,
1823 PPSMC_MSG_API_GetMclkFrequency,
1824 &mclk_freq);
1825 if (smc_result != PPSMC_Result_OK)
1826 mclk_freq = 0;
1827
1828 return mclk_freq;
1829 }
1830
ci_dpm_start_smc(struct radeon_device * rdev)1831 static void ci_dpm_start_smc(struct radeon_device *rdev)
1832 {
1833 int i;
1834
1835 ci_program_jump_on_start(rdev);
1836 ci_start_smc_clock(rdev);
1837 ci_start_smc(rdev);
1838 for (i = 0; i < rdev->usec_timeout; i++) {
1839 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1840 break;
1841 }
1842 }
1843
ci_dpm_stop_smc(struct radeon_device * rdev)1844 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1845 {
1846 ci_reset_smc(rdev);
1847 ci_stop_smc_clock(rdev);
1848 }
1849
ci_process_firmware_header(struct radeon_device * rdev)1850 static int ci_process_firmware_header(struct radeon_device *rdev)
1851 {
1852 struct ci_power_info *pi = ci_get_pi(rdev);
1853 u32 tmp;
1854 int ret;
1855
1856 ret = ci_read_smc_sram_dword(rdev,
1857 SMU7_FIRMWARE_HEADER_LOCATION +
1858 offsetof(SMU7_Firmware_Header, DpmTable),
1859 &tmp, pi->sram_end);
1860 if (ret)
1861 return ret;
1862
1863 pi->dpm_table_start = tmp;
1864
1865 ret = ci_read_smc_sram_dword(rdev,
1866 SMU7_FIRMWARE_HEADER_LOCATION +
1867 offsetof(SMU7_Firmware_Header, SoftRegisters),
1868 &tmp, pi->sram_end);
1869 if (ret)
1870 return ret;
1871
1872 pi->soft_regs_start = tmp;
1873
1874 ret = ci_read_smc_sram_dword(rdev,
1875 SMU7_FIRMWARE_HEADER_LOCATION +
1876 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1877 &tmp, pi->sram_end);
1878 if (ret)
1879 return ret;
1880
1881 pi->mc_reg_table_start = tmp;
1882
1883 ret = ci_read_smc_sram_dword(rdev,
1884 SMU7_FIRMWARE_HEADER_LOCATION +
1885 offsetof(SMU7_Firmware_Header, FanTable),
1886 &tmp, pi->sram_end);
1887 if (ret)
1888 return ret;
1889
1890 pi->fan_table_start = tmp;
1891
1892 ret = ci_read_smc_sram_dword(rdev,
1893 SMU7_FIRMWARE_HEADER_LOCATION +
1894 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1895 &tmp, pi->sram_end);
1896 if (ret)
1897 return ret;
1898
1899 pi->arb_table_start = tmp;
1900
1901 return 0;
1902 }
1903
ci_read_clock_registers(struct radeon_device * rdev)1904 static void ci_read_clock_registers(struct radeon_device *rdev)
1905 {
1906 struct ci_power_info *pi = ci_get_pi(rdev);
1907
1908 pi->clock_registers.cg_spll_func_cntl =
1909 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1910 pi->clock_registers.cg_spll_func_cntl_2 =
1911 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1912 pi->clock_registers.cg_spll_func_cntl_3 =
1913 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1914 pi->clock_registers.cg_spll_func_cntl_4 =
1915 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1916 pi->clock_registers.cg_spll_spread_spectrum =
1917 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1918 pi->clock_registers.cg_spll_spread_spectrum_2 =
1919 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1920 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1921 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1922 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1923 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1924 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1925 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1926 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1927 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1928 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1929 }
1930
ci_init_sclk_t(struct radeon_device * rdev)1931 static void ci_init_sclk_t(struct radeon_device *rdev)
1932 {
1933 struct ci_power_info *pi = ci_get_pi(rdev);
1934
1935 pi->low_sclk_interrupt_t = 0;
1936 }
1937
ci_enable_thermal_protection(struct radeon_device * rdev,bool enable)1938 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1939 bool enable)
1940 {
1941 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1942
1943 if (enable)
1944 tmp &= ~THERMAL_PROTECTION_DIS;
1945 else
1946 tmp |= THERMAL_PROTECTION_DIS;
1947 WREG32_SMC(GENERAL_PWRMGT, tmp);
1948 }
1949
ci_enable_acpi_power_management(struct radeon_device * rdev)1950 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1951 {
1952 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1953
1954 tmp |= STATIC_PM_EN;
1955
1956 WREG32_SMC(GENERAL_PWRMGT, tmp);
1957 }
1958
1959 #if 0
1960 static int ci_enter_ulp_state(struct radeon_device *rdev)
1961 {
1962
1963 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1964
1965 udelay(25000);
1966
1967 return 0;
1968 }
1969
1970 static int ci_exit_ulp_state(struct radeon_device *rdev)
1971 {
1972 int i;
1973
1974 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1975
1976 udelay(7000);
1977
1978 for (i = 0; i < rdev->usec_timeout; i++) {
1979 if (RREG32(SMC_RESP_0) == 1)
1980 break;
1981 udelay(1000);
1982 }
1983
1984 return 0;
1985 }
1986 #endif
1987
ci_notify_smc_display_change(struct radeon_device * rdev,bool has_display)1988 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1989 bool has_display)
1990 {
1991 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1992
1993 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1994 }
1995
ci_enable_ds_master_switch(struct radeon_device * rdev,bool enable)1996 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1997 bool enable)
1998 {
1999 struct ci_power_info *pi = ci_get_pi(rdev);
2000
2001 if (enable) {
2002 if (pi->caps_sclk_ds) {
2003 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
2004 return -EINVAL;
2005 } else {
2006 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2007 return -EINVAL;
2008 }
2009 } else {
2010 if (pi->caps_sclk_ds) {
2011 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2012 return -EINVAL;
2013 }
2014 }
2015
2016 return 0;
2017 }
2018
ci_program_display_gap(struct radeon_device * rdev)2019 static void ci_program_display_gap(struct radeon_device *rdev)
2020 {
2021 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
2022 u32 pre_vbi_time_in_us;
2023 u32 frame_time_in_us;
2024 u32 ref_clock = rdev->clock.spll.reference_freq;
2025 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
2026 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
2027
2028 tmp &= ~DISP_GAP_MASK;
2029 if (rdev->pm.dpm.new_active_crtc_count > 0)
2030 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
2031 else
2032 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
2033 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
2034
2035 if (refresh_rate == 0)
2036 refresh_rate = 60;
2037 if (vblank_time == 0xffffffff)
2038 vblank_time = 500;
2039 frame_time_in_us = 1000000 / refresh_rate;
2040 pre_vbi_time_in_us =
2041 frame_time_in_us - 200 - vblank_time;
2042 tmp = pre_vbi_time_in_us * (ref_clock / 100);
2043
2044 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
2045 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2046 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2047
2048
2049 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
2050
2051 }
2052
ci_enable_spread_spectrum(struct radeon_device * rdev,bool enable)2053 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
2054 {
2055 struct ci_power_info *pi = ci_get_pi(rdev);
2056 u32 tmp;
2057
2058 if (enable) {
2059 if (pi->caps_sclk_ss_support) {
2060 tmp = RREG32_SMC(GENERAL_PWRMGT);
2061 tmp |= DYN_SPREAD_SPECTRUM_EN;
2062 WREG32_SMC(GENERAL_PWRMGT, tmp);
2063 }
2064 } else {
2065 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
2066 tmp &= ~SSEN;
2067 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
2068
2069 tmp = RREG32_SMC(GENERAL_PWRMGT);
2070 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
2071 WREG32_SMC(GENERAL_PWRMGT, tmp);
2072 }
2073 }
2074
ci_program_sstp(struct radeon_device * rdev)2075 static void ci_program_sstp(struct radeon_device *rdev)
2076 {
2077 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
2078 }
2079
ci_enable_display_gap(struct radeon_device * rdev)2080 static void ci_enable_display_gap(struct radeon_device *rdev)
2081 {
2082 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
2083
2084 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
2085 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
2086 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
2087
2088 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
2089 }
2090
ci_program_vc(struct radeon_device * rdev)2091 static void ci_program_vc(struct radeon_device *rdev)
2092 {
2093 u32 tmp;
2094
2095 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2096 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
2097 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2098
2099 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
2100 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
2101 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
2102 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
2103 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
2104 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
2105 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
2106 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
2107 }
2108
ci_clear_vc(struct radeon_device * rdev)2109 static void ci_clear_vc(struct radeon_device *rdev)
2110 {
2111 u32 tmp;
2112
2113 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2114 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
2115 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2116
2117 WREG32_SMC(CG_FTV_0, 0);
2118 WREG32_SMC(CG_FTV_1, 0);
2119 WREG32_SMC(CG_FTV_2, 0);
2120 WREG32_SMC(CG_FTV_3, 0);
2121 WREG32_SMC(CG_FTV_4, 0);
2122 WREG32_SMC(CG_FTV_5, 0);
2123 WREG32_SMC(CG_FTV_6, 0);
2124 WREG32_SMC(CG_FTV_7, 0);
2125 }
2126
ci_upload_firmware(struct radeon_device * rdev)2127 static int ci_upload_firmware(struct radeon_device *rdev)
2128 {
2129 struct ci_power_info *pi = ci_get_pi(rdev);
2130 int i, ret;
2131
2132 for (i = 0; i < rdev->usec_timeout; i++) {
2133 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
2134 break;
2135 }
2136 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
2137
2138 ci_stop_smc_clock(rdev);
2139 ci_reset_smc(rdev);
2140
2141 ret = ci_load_smc_ucode(rdev, pi->sram_end);
2142
2143 return ret;
2144
2145 }
2146
ci_get_svi2_voltage_table(struct radeon_device * rdev,struct radeon_clock_voltage_dependency_table * voltage_dependency_table,struct atom_voltage_table * voltage_table)2147 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
2148 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
2149 struct atom_voltage_table *voltage_table)
2150 {
2151 u32 i;
2152
2153 if (voltage_dependency_table == NULL)
2154 return -EINVAL;
2155
2156 voltage_table->mask_low = 0;
2157 voltage_table->phase_delay = 0;
2158
2159 voltage_table->count = voltage_dependency_table->count;
2160 for (i = 0; i < voltage_table->count; i++) {
2161 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2162 voltage_table->entries[i].smio_low = 0;
2163 }
2164
2165 return 0;
2166 }
2167
ci_construct_voltage_tables(struct radeon_device * rdev)2168 static int ci_construct_voltage_tables(struct radeon_device *rdev)
2169 {
2170 struct ci_power_info *pi = ci_get_pi(rdev);
2171 int ret;
2172
2173 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2174 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
2175 VOLTAGE_OBJ_GPIO_LUT,
2176 &pi->vddc_voltage_table);
2177 if (ret)
2178 return ret;
2179 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2180 ret = ci_get_svi2_voltage_table(rdev,
2181 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2182 &pi->vddc_voltage_table);
2183 if (ret)
2184 return ret;
2185 }
2186
2187 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2188 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
2189 &pi->vddc_voltage_table);
2190
2191 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2192 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
2193 VOLTAGE_OBJ_GPIO_LUT,
2194 &pi->vddci_voltage_table);
2195 if (ret)
2196 return ret;
2197 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2198 ret = ci_get_svi2_voltage_table(rdev,
2199 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2200 &pi->vddci_voltage_table);
2201 if (ret)
2202 return ret;
2203 }
2204
2205 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2206 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
2207 &pi->vddci_voltage_table);
2208
2209 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2210 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
2211 VOLTAGE_OBJ_GPIO_LUT,
2212 &pi->mvdd_voltage_table);
2213 if (ret)
2214 return ret;
2215 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2216 ret = ci_get_svi2_voltage_table(rdev,
2217 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2218 &pi->mvdd_voltage_table);
2219 if (ret)
2220 return ret;
2221 }
2222
2223 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2224 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
2225 &pi->mvdd_voltage_table);
2226
2227 return 0;
2228 }
2229
ci_populate_smc_voltage_table(struct radeon_device * rdev,struct atom_voltage_table_entry * voltage_table,SMU7_Discrete_VoltageLevel * smc_voltage_table)2230 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
2231 struct atom_voltage_table_entry *voltage_table,
2232 SMU7_Discrete_VoltageLevel *smc_voltage_table)
2233 {
2234 int ret;
2235
2236 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
2237 &smc_voltage_table->StdVoltageHiSidd,
2238 &smc_voltage_table->StdVoltageLoSidd);
2239
2240 if (ret) {
2241 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2242 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2243 }
2244
2245 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2246 smc_voltage_table->StdVoltageHiSidd =
2247 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2248 smc_voltage_table->StdVoltageLoSidd =
2249 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2250 }
2251
ci_populate_smc_vddc_table(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2252 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
2253 SMU7_Discrete_DpmTable *table)
2254 {
2255 struct ci_power_info *pi = ci_get_pi(rdev);
2256 unsigned int count;
2257
2258 table->VddcLevelCount = pi->vddc_voltage_table.count;
2259 for (count = 0; count < table->VddcLevelCount; count++) {
2260 ci_populate_smc_voltage_table(rdev,
2261 &pi->vddc_voltage_table.entries[count],
2262 &table->VddcLevel[count]);
2263
2264 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2265 table->VddcLevel[count].Smio |=
2266 pi->vddc_voltage_table.entries[count].smio_low;
2267 else
2268 table->VddcLevel[count].Smio = 0;
2269 }
2270 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2271
2272 return 0;
2273 }
2274
ci_populate_smc_vddci_table(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2275 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
2276 SMU7_Discrete_DpmTable *table)
2277 {
2278 unsigned int count;
2279 struct ci_power_info *pi = ci_get_pi(rdev);
2280
2281 table->VddciLevelCount = pi->vddci_voltage_table.count;
2282 for (count = 0; count < table->VddciLevelCount; count++) {
2283 ci_populate_smc_voltage_table(rdev,
2284 &pi->vddci_voltage_table.entries[count],
2285 &table->VddciLevel[count]);
2286
2287 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2288 table->VddciLevel[count].Smio |=
2289 pi->vddci_voltage_table.entries[count].smio_low;
2290 else
2291 table->VddciLevel[count].Smio = 0;
2292 }
2293 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2294
2295 return 0;
2296 }
2297
ci_populate_smc_mvdd_table(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2298 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
2299 SMU7_Discrete_DpmTable *table)
2300 {
2301 struct ci_power_info *pi = ci_get_pi(rdev);
2302 unsigned int count;
2303
2304 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2305 for (count = 0; count < table->MvddLevelCount; count++) {
2306 ci_populate_smc_voltage_table(rdev,
2307 &pi->mvdd_voltage_table.entries[count],
2308 &table->MvddLevel[count]);
2309
2310 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2311 table->MvddLevel[count].Smio |=
2312 pi->mvdd_voltage_table.entries[count].smio_low;
2313 else
2314 table->MvddLevel[count].Smio = 0;
2315 }
2316 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2317
2318 return 0;
2319 }
2320
ci_populate_smc_voltage_tables(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2321 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
2322 SMU7_Discrete_DpmTable *table)
2323 {
2324 int ret;
2325
2326 ret = ci_populate_smc_vddc_table(rdev, table);
2327 if (ret)
2328 return ret;
2329
2330 ret = ci_populate_smc_vddci_table(rdev, table);
2331 if (ret)
2332 return ret;
2333
2334 ret = ci_populate_smc_mvdd_table(rdev, table);
2335 if (ret)
2336 return ret;
2337
2338 return 0;
2339 }
2340
ci_populate_mvdd_value(struct radeon_device * rdev,u32 mclk,SMU7_Discrete_VoltageLevel * voltage)2341 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
2342 SMU7_Discrete_VoltageLevel *voltage)
2343 {
2344 struct ci_power_info *pi = ci_get_pi(rdev);
2345 u32 i = 0;
2346
2347 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2348 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2349 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2350 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2351 break;
2352 }
2353 }
2354
2355 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2356 return -EINVAL;
2357 }
2358
2359 return -EINVAL;
2360 }
2361
ci_get_std_voltage_value_sidd(struct radeon_device * rdev,struct atom_voltage_table_entry * voltage_table,u16 * std_voltage_hi_sidd,u16 * std_voltage_lo_sidd)2362 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
2363 struct atom_voltage_table_entry *voltage_table,
2364 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2365 {
2366 u16 v_index, idx;
2367 bool voltage_found = false;
2368 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2369 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2370
2371 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2372 return -EINVAL;
2373
2374 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2375 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2376 if (voltage_table->value ==
2377 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2378 voltage_found = true;
2379 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2380 idx = v_index;
2381 else
2382 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2383 *std_voltage_lo_sidd =
2384 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2385 *std_voltage_hi_sidd =
2386 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2387 break;
2388 }
2389 }
2390
2391 if (!voltage_found) {
2392 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2393 if (voltage_table->value <=
2394 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2395 voltage_found = true;
2396 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2397 idx = v_index;
2398 else
2399 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2400 *std_voltage_lo_sidd =
2401 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2402 *std_voltage_hi_sidd =
2403 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2404 break;
2405 }
2406 }
2407 }
2408 }
2409
2410 return 0;
2411 }
2412
ci_populate_phase_value_based_on_sclk(struct radeon_device * rdev,const struct radeon_phase_shedding_limits_table * limits,u32 sclk,u32 * phase_shedding)2413 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
2414 const struct radeon_phase_shedding_limits_table *limits,
2415 u32 sclk,
2416 u32 *phase_shedding)
2417 {
2418 unsigned int i;
2419
2420 *phase_shedding = 1;
2421
2422 for (i = 0; i < limits->count; i++) {
2423 if (sclk < limits->entries[i].sclk) {
2424 *phase_shedding = i;
2425 break;
2426 }
2427 }
2428 }
2429
ci_populate_phase_value_based_on_mclk(struct radeon_device * rdev,const struct radeon_phase_shedding_limits_table * limits,u32 mclk,u32 * phase_shedding)2430 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
2431 const struct radeon_phase_shedding_limits_table *limits,
2432 u32 mclk,
2433 u32 *phase_shedding)
2434 {
2435 unsigned int i;
2436
2437 *phase_shedding = 1;
2438
2439 for (i = 0; i < limits->count; i++) {
2440 if (mclk < limits->entries[i].mclk) {
2441 *phase_shedding = i;
2442 break;
2443 }
2444 }
2445 }
2446
ci_init_arb_table_index(struct radeon_device * rdev)2447 static int ci_init_arb_table_index(struct radeon_device *rdev)
2448 {
2449 struct ci_power_info *pi = ci_get_pi(rdev);
2450 u32 tmp;
2451 int ret;
2452
2453 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
2454 &tmp, pi->sram_end);
2455 if (ret)
2456 return ret;
2457
2458 tmp &= 0x00FFFFFF;
2459 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2460
2461 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2462 tmp, pi->sram_end);
2463 }
2464
ci_get_dependency_volt_by_clk(struct radeon_device * rdev,struct radeon_clock_voltage_dependency_table * allowed_clock_voltage_table,u32 clock,u32 * voltage)2465 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2466 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2467 u32 clock, u32 *voltage)
2468 {
2469 u32 i = 0;
2470
2471 if (allowed_clock_voltage_table->count == 0)
2472 return -EINVAL;
2473
2474 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2475 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2476 *voltage = allowed_clock_voltage_table->entries[i].v;
2477 return 0;
2478 }
2479 }
2480
2481 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2482
2483 return 0;
2484 }
2485
ci_get_sleep_divider_id_from_clock(struct radeon_device * rdev,u32 sclk,u32 min_sclk_in_sr)2486 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2487 u32 sclk, u32 min_sclk_in_sr)
2488 {
2489 u32 i;
2490 u32 tmp;
2491 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2492 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2493
2494 if (sclk < min)
2495 return 0;
2496
2497 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2498 tmp = sclk / (1 << i);
2499 if (tmp >= min || i == 0)
2500 break;
2501 }
2502
2503 return (u8)i;
2504 }
2505
ci_initial_switch_from_arb_f0_to_f1(struct radeon_device * rdev)2506 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2507 {
2508 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2509 }
2510
ci_reset_to_default(struct radeon_device * rdev)2511 static int ci_reset_to_default(struct radeon_device *rdev)
2512 {
2513 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2514 0 : -EINVAL;
2515 }
2516
ci_force_switch_to_arb_f0(struct radeon_device * rdev)2517 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2518 {
2519 u32 tmp;
2520
2521 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2522
2523 if (tmp == MC_CG_ARB_FREQ_F0)
2524 return 0;
2525
2526 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2527 }
2528
ci_register_patching_mc_arb(struct radeon_device * rdev,const u32 engine_clock,const u32 memory_clock,u32 * dram_timimg2)2529 static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2530 const u32 engine_clock,
2531 const u32 memory_clock,
2532 u32 *dram_timimg2)
2533 {
2534 bool patch;
2535 u32 tmp, tmp2;
2536
2537 tmp = RREG32(MC_SEQ_MISC0);
2538 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2539
2540 if (patch &&
2541 ((rdev->pdev->device == 0x67B0) ||
2542 (rdev->pdev->device == 0x67B1))) {
2543 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2544 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2545 *dram_timimg2 &= ~0x00ff0000;
2546 *dram_timimg2 |= tmp2 << 16;
2547 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2548 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2549 *dram_timimg2 &= ~0x00ff0000;
2550 *dram_timimg2 |= tmp2 << 16;
2551 }
2552 }
2553 }
2554
2555
ci_populate_memory_timing_parameters(struct radeon_device * rdev,u32 sclk,u32 mclk,SMU7_Discrete_MCArbDramTimingTableEntry * arb_regs)2556 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2557 u32 sclk,
2558 u32 mclk,
2559 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2560 {
2561 u32 dram_timing;
2562 u32 dram_timing2;
2563 u32 burst_time;
2564
2565 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2566
2567 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2568 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2569 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2570
2571 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2572
2573 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2574 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2575 arb_regs->McArbBurstTime = (u8)burst_time;
2576
2577 return 0;
2578 }
2579
ci_do_program_memory_timing_parameters(struct radeon_device * rdev)2580 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2581 {
2582 struct ci_power_info *pi = ci_get_pi(rdev);
2583 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2584 u32 i, j;
2585 int ret = 0;
2586
2587 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2588
2589 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2590 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2591 ret = ci_populate_memory_timing_parameters(rdev,
2592 pi->dpm_table.sclk_table.dpm_levels[i].value,
2593 pi->dpm_table.mclk_table.dpm_levels[j].value,
2594 &arb_regs.entries[i][j]);
2595 if (ret)
2596 break;
2597 }
2598 }
2599
2600 if (ret == 0)
2601 ret = ci_copy_bytes_to_smc(rdev,
2602 pi->arb_table_start,
2603 (u8 *)&arb_regs,
2604 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2605 pi->sram_end);
2606
2607 return ret;
2608 }
2609
ci_program_memory_timing_parameters(struct radeon_device * rdev)2610 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2611 {
2612 struct ci_power_info *pi = ci_get_pi(rdev);
2613
2614 if (pi->need_update_smu7_dpm_table == 0)
2615 return 0;
2616
2617 return ci_do_program_memory_timing_parameters(rdev);
2618 }
2619
ci_populate_smc_initial_state(struct radeon_device * rdev,struct radeon_ps * radeon_boot_state)2620 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2621 struct radeon_ps *radeon_boot_state)
2622 {
2623 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2624 struct ci_power_info *pi = ci_get_pi(rdev);
2625 u32 level = 0;
2626
2627 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2628 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2629 boot_state->performance_levels[0].sclk) {
2630 pi->smc_state_table.GraphicsBootLevel = level;
2631 break;
2632 }
2633 }
2634
2635 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2636 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2637 boot_state->performance_levels[0].mclk) {
2638 pi->smc_state_table.MemoryBootLevel = level;
2639 break;
2640 }
2641 }
2642 }
2643
ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table * dpm_table)2644 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2645 {
2646 u32 i;
2647 u32 mask_value = 0;
2648
2649 for (i = dpm_table->count; i > 0; i--) {
2650 mask_value = mask_value << 1;
2651 if (dpm_table->dpm_levels[i-1].enabled)
2652 mask_value |= 0x1;
2653 else
2654 mask_value &= 0xFFFFFFFE;
2655 }
2656
2657 return mask_value;
2658 }
2659
ci_populate_smc_link_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2660 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2661 SMU7_Discrete_DpmTable *table)
2662 {
2663 struct ci_power_info *pi = ci_get_pi(rdev);
2664 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2665 u32 i;
2666
2667 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2668 table->LinkLevel[i].PcieGenSpeed =
2669 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2670 table->LinkLevel[i].PcieLaneCount =
2671 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2672 table->LinkLevel[i].EnabledForActivity = 1;
2673 table->LinkLevel[i].DownT = cpu_to_be32(5);
2674 table->LinkLevel[i].UpT = cpu_to_be32(30);
2675 }
2676
2677 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2678 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2679 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2680 }
2681
ci_populate_smc_uvd_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2682 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2683 SMU7_Discrete_DpmTable *table)
2684 {
2685 u32 count;
2686 struct atom_clock_dividers dividers;
2687 int ret = -EINVAL;
2688
2689 table->UvdLevelCount =
2690 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2691
2692 for (count = 0; count < table->UvdLevelCount; count++) {
2693 table->UvdLevel[count].VclkFrequency =
2694 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2695 table->UvdLevel[count].DclkFrequency =
2696 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2697 table->UvdLevel[count].MinVddc =
2698 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2699 table->UvdLevel[count].MinVddcPhases = 1;
2700
2701 ret = radeon_atom_get_clock_dividers(rdev,
2702 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2703 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2704 if (ret)
2705 return ret;
2706
2707 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2708
2709 ret = radeon_atom_get_clock_dividers(rdev,
2710 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2711 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2712 if (ret)
2713 return ret;
2714
2715 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2716
2717 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2718 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2719 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2720 }
2721
2722 return ret;
2723 }
2724
ci_populate_smc_vce_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2725 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2726 SMU7_Discrete_DpmTable *table)
2727 {
2728 u32 count;
2729 struct atom_clock_dividers dividers;
2730 int ret = -EINVAL;
2731
2732 table->VceLevelCount =
2733 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2734
2735 for (count = 0; count < table->VceLevelCount; count++) {
2736 table->VceLevel[count].Frequency =
2737 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2738 table->VceLevel[count].MinVoltage =
2739 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2740 table->VceLevel[count].MinPhases = 1;
2741
2742 ret = radeon_atom_get_clock_dividers(rdev,
2743 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2744 table->VceLevel[count].Frequency, false, ÷rs);
2745 if (ret)
2746 return ret;
2747
2748 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2749
2750 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2751 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2752 }
2753
2754 return ret;
2755
2756 }
2757
ci_populate_smc_acp_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2758 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2759 SMU7_Discrete_DpmTable *table)
2760 {
2761 u32 count;
2762 struct atom_clock_dividers dividers;
2763 int ret = -EINVAL;
2764
2765 table->AcpLevelCount = (u8)
2766 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2767
2768 for (count = 0; count < table->AcpLevelCount; count++) {
2769 table->AcpLevel[count].Frequency =
2770 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2771 table->AcpLevel[count].MinVoltage =
2772 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2773 table->AcpLevel[count].MinPhases = 1;
2774
2775 ret = radeon_atom_get_clock_dividers(rdev,
2776 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2777 table->AcpLevel[count].Frequency, false, ÷rs);
2778 if (ret)
2779 return ret;
2780
2781 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2782
2783 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2784 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2785 }
2786
2787 return ret;
2788 }
2789
ci_populate_smc_samu_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2790 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2791 SMU7_Discrete_DpmTable *table)
2792 {
2793 u32 count;
2794 struct atom_clock_dividers dividers;
2795 int ret = -EINVAL;
2796
2797 table->SamuLevelCount =
2798 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2799
2800 for (count = 0; count < table->SamuLevelCount; count++) {
2801 table->SamuLevel[count].Frequency =
2802 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2803 table->SamuLevel[count].MinVoltage =
2804 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2805 table->SamuLevel[count].MinPhases = 1;
2806
2807 ret = radeon_atom_get_clock_dividers(rdev,
2808 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2809 table->SamuLevel[count].Frequency, false, ÷rs);
2810 if (ret)
2811 return ret;
2812
2813 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2814
2815 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2816 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2817 }
2818
2819 return ret;
2820 }
2821
ci_calculate_mclk_params(struct radeon_device * rdev,u32 memory_clock,SMU7_Discrete_MemoryLevel * mclk,bool strobe_mode,bool dll_state_on)2822 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2823 u32 memory_clock,
2824 SMU7_Discrete_MemoryLevel *mclk,
2825 bool strobe_mode,
2826 bool dll_state_on)
2827 {
2828 struct ci_power_info *pi = ci_get_pi(rdev);
2829 u32 dll_cntl = pi->clock_registers.dll_cntl;
2830 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2831 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2832 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2833 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2834 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2835 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2836 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2837 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2838 struct atom_mpll_param mpll_param;
2839 int ret;
2840
2841 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2842 if (ret)
2843 return ret;
2844
2845 mpll_func_cntl &= ~BWCTRL_MASK;
2846 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2847
2848 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2849 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2850 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2851
2852 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2853 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2854
2855 if (pi->mem_gddr5) {
2856 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2857 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2858 YCLK_POST_DIV(mpll_param.post_div);
2859 }
2860
2861 if (pi->caps_mclk_ss_support) {
2862 struct radeon_atom_ss ss;
2863 u32 freq_nom;
2864 u32 tmp;
2865 u32 reference_clock = rdev->clock.mpll.reference_freq;
2866
2867 if (mpll_param.qdr == 1)
2868 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2869 else
2870 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2871
2872 tmp = (freq_nom / reference_clock);
2873 tmp = tmp * tmp;
2874 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2875 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2876 u32 clks = reference_clock * 5 / ss.rate;
2877 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2878
2879 mpll_ss1 &= ~CLKV_MASK;
2880 mpll_ss1 |= CLKV(clkv);
2881
2882 mpll_ss2 &= ~CLKS_MASK;
2883 mpll_ss2 |= CLKS(clks);
2884 }
2885 }
2886
2887 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2888 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2889
2890 if (dll_state_on)
2891 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2892 else
2893 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2894
2895 mclk->MclkFrequency = memory_clock;
2896 mclk->MpllFuncCntl = mpll_func_cntl;
2897 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2898 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2899 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2900 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2901 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2902 mclk->DllCntl = dll_cntl;
2903 mclk->MpllSs1 = mpll_ss1;
2904 mclk->MpllSs2 = mpll_ss2;
2905
2906 return 0;
2907 }
2908
ci_populate_single_memory_level(struct radeon_device * rdev,u32 memory_clock,SMU7_Discrete_MemoryLevel * memory_level)2909 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2910 u32 memory_clock,
2911 SMU7_Discrete_MemoryLevel *memory_level)
2912 {
2913 struct ci_power_info *pi = ci_get_pi(rdev);
2914 int ret;
2915 bool dll_state_on;
2916
2917 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2918 ret = ci_get_dependency_volt_by_clk(rdev,
2919 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2920 memory_clock, &memory_level->MinVddc);
2921 if (ret)
2922 return ret;
2923 }
2924
2925 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2926 ret = ci_get_dependency_volt_by_clk(rdev,
2927 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2928 memory_clock, &memory_level->MinVddci);
2929 if (ret)
2930 return ret;
2931 }
2932
2933 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2934 ret = ci_get_dependency_volt_by_clk(rdev,
2935 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2936 memory_clock, &memory_level->MinMvdd);
2937 if (ret)
2938 return ret;
2939 }
2940
2941 memory_level->MinVddcPhases = 1;
2942
2943 if (pi->vddc_phase_shed_control)
2944 ci_populate_phase_value_based_on_mclk(rdev,
2945 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2946 memory_clock,
2947 &memory_level->MinVddcPhases);
2948
2949 memory_level->EnabledForThrottle = 1;
2950 memory_level->UpH = 0;
2951 memory_level->DownH = 100;
2952 memory_level->VoltageDownH = 0;
2953 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2954
2955 memory_level->StutterEnable = false;
2956 memory_level->StrobeEnable = false;
2957 memory_level->EdcReadEnable = false;
2958 memory_level->EdcWriteEnable = false;
2959 memory_level->RttEnable = false;
2960
2961 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2962
2963 if (pi->mclk_stutter_mode_threshold &&
2964 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2965 (pi->uvd_enabled == false) &&
2966 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2967 (rdev->pm.dpm.new_active_crtc_count <= 2))
2968 memory_level->StutterEnable = true;
2969
2970 if (pi->mclk_strobe_mode_threshold &&
2971 (memory_clock <= pi->mclk_strobe_mode_threshold))
2972 memory_level->StrobeEnable = 1;
2973
2974 if (pi->mem_gddr5) {
2975 memory_level->StrobeRatio =
2976 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2977 if (pi->mclk_edc_enable_threshold &&
2978 (memory_clock > pi->mclk_edc_enable_threshold))
2979 memory_level->EdcReadEnable = true;
2980
2981 if (pi->mclk_edc_wr_enable_threshold &&
2982 (memory_clock > pi->mclk_edc_wr_enable_threshold))
2983 memory_level->EdcWriteEnable = true;
2984
2985 if (memory_level->StrobeEnable) {
2986 if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2987 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2988 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2989 else
2990 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2991 } else {
2992 dll_state_on = pi->dll_default_on;
2993 }
2994 } else {
2995 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2996 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2997 }
2998
2999 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
3000 if (ret)
3001 return ret;
3002
3003 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
3004 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
3005 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
3006 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
3007
3008 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
3009 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
3010 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
3011 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
3012 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
3013 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
3014 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
3015 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
3016 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
3017 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
3018 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
3019
3020 return 0;
3021 }
3022
ci_populate_smc_acpi_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)3023 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
3024 SMU7_Discrete_DpmTable *table)
3025 {
3026 struct ci_power_info *pi = ci_get_pi(rdev);
3027 struct atom_clock_dividers dividers;
3028 SMU7_Discrete_VoltageLevel voltage_level;
3029 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
3030 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
3031 u32 dll_cntl = pi->clock_registers.dll_cntl;
3032 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
3033 int ret;
3034
3035 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3036
3037 if (pi->acpi_vddc)
3038 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3039 else
3040 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3041
3042 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3043
3044 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
3045
3046 ret = radeon_atom_get_clock_dividers(rdev,
3047 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3048 table->ACPILevel.SclkFrequency, false, ÷rs);
3049 if (ret)
3050 return ret;
3051
3052 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3053 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3054 table->ACPILevel.DeepSleepDivId = 0;
3055
3056 spll_func_cntl &= ~SPLL_PWRON;
3057 spll_func_cntl |= SPLL_RESET;
3058
3059 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
3060 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
3061
3062 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3063 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3064 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3065 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3066 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3067 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3068 table->ACPILevel.CcPwrDynRm = 0;
3069 table->ACPILevel.CcPwrDynRm1 = 0;
3070
3071 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3072 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3073 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3074 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3075 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3076 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3077 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3078 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3079 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3080 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3081 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3082
3083 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3084 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3085
3086 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3087 if (pi->acpi_vddci)
3088 table->MemoryACPILevel.MinVddci =
3089 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3090 else
3091 table->MemoryACPILevel.MinVddci =
3092 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3093 }
3094
3095 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
3096 table->MemoryACPILevel.MinMvdd = 0;
3097 else
3098 table->MemoryACPILevel.MinMvdd =
3099 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3100
3101 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
3102 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
3103
3104 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
3105
3106 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3107 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3108 table->MemoryACPILevel.MpllAdFuncCntl =
3109 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3110 table->MemoryACPILevel.MpllDqFuncCntl =
3111 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3112 table->MemoryACPILevel.MpllFuncCntl =
3113 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3114 table->MemoryACPILevel.MpllFuncCntl_1 =
3115 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3116 table->MemoryACPILevel.MpllFuncCntl_2 =
3117 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3118 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3119 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3120
3121 table->MemoryACPILevel.EnabledForThrottle = 0;
3122 table->MemoryACPILevel.EnabledForActivity = 0;
3123 table->MemoryACPILevel.UpH = 0;
3124 table->MemoryACPILevel.DownH = 100;
3125 table->MemoryACPILevel.VoltageDownH = 0;
3126 table->MemoryACPILevel.ActivityLevel =
3127 cpu_to_be16((u16)pi->mclk_activity_target);
3128
3129 table->MemoryACPILevel.StutterEnable = false;
3130 table->MemoryACPILevel.StrobeEnable = false;
3131 table->MemoryACPILevel.EdcReadEnable = false;
3132 table->MemoryACPILevel.EdcWriteEnable = false;
3133 table->MemoryACPILevel.RttEnable = false;
3134
3135 return 0;
3136 }
3137
3138
ci_enable_ulv(struct radeon_device * rdev,bool enable)3139 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
3140 {
3141 struct ci_power_info *pi = ci_get_pi(rdev);
3142 struct ci_ulv_parm *ulv = &pi->ulv;
3143
3144 if (ulv->supported) {
3145 if (enable)
3146 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3147 0 : -EINVAL;
3148 else
3149 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3150 0 : -EINVAL;
3151 }
3152
3153 return 0;
3154 }
3155
ci_populate_ulv_level(struct radeon_device * rdev,SMU7_Discrete_Ulv * state)3156 static int ci_populate_ulv_level(struct radeon_device *rdev,
3157 SMU7_Discrete_Ulv *state)
3158 {
3159 struct ci_power_info *pi = ci_get_pi(rdev);
3160 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
3161
3162 state->CcPwrDynRm = 0;
3163 state->CcPwrDynRm1 = 0;
3164
3165 if (ulv_voltage == 0) {
3166 pi->ulv.supported = false;
3167 return 0;
3168 }
3169
3170 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3171 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3172 state->VddcOffset = 0;
3173 else
3174 state->VddcOffset =
3175 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3176 } else {
3177 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3178 state->VddcOffsetVid = 0;
3179 else
3180 state->VddcOffsetVid = (u8)
3181 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3182 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3183 }
3184 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3185
3186 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3187 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3188 state->VddcOffset = cpu_to_be16(state->VddcOffset);
3189
3190 return 0;
3191 }
3192
ci_calculate_sclk_params(struct radeon_device * rdev,u32 engine_clock,SMU7_Discrete_GraphicsLevel * sclk)3193 static int ci_calculate_sclk_params(struct radeon_device *rdev,
3194 u32 engine_clock,
3195 SMU7_Discrete_GraphicsLevel *sclk)
3196 {
3197 struct ci_power_info *pi = ci_get_pi(rdev);
3198 struct atom_clock_dividers dividers;
3199 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3200 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3201 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3202 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3203 u32 reference_clock = rdev->clock.spll.reference_freq;
3204 u32 reference_divider;
3205 u32 fbdiv;
3206 int ret;
3207
3208 ret = radeon_atom_get_clock_dividers(rdev,
3209 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3210 engine_clock, false, ÷rs);
3211 if (ret)
3212 return ret;
3213
3214 reference_divider = 1 + dividers.ref_div;
3215 fbdiv = dividers.fb_div & 0x3FFFFFF;
3216
3217 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
3218 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
3219 spll_func_cntl_3 |= SPLL_DITHEN;
3220
3221 if (pi->caps_sclk_ss_support) {
3222 struct radeon_atom_ss ss;
3223 u32 vco_freq = engine_clock * dividers.post_div;
3224
3225 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
3226 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3227 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3228 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3229
3230 cg_spll_spread_spectrum &= ~CLK_S_MASK;
3231 cg_spll_spread_spectrum |= CLK_S(clk_s);
3232 cg_spll_spread_spectrum |= SSEN;
3233
3234 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
3235 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
3236 }
3237 }
3238
3239 sclk->SclkFrequency = engine_clock;
3240 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3241 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3242 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3243 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3244 sclk->SclkDid = (u8)dividers.post_divider;
3245
3246 return 0;
3247 }
3248
ci_populate_single_graphic_level(struct radeon_device * rdev,u32 engine_clock,u16 sclk_activity_level_t,SMU7_Discrete_GraphicsLevel * graphic_level)3249 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
3250 u32 engine_clock,
3251 u16 sclk_activity_level_t,
3252 SMU7_Discrete_GraphicsLevel *graphic_level)
3253 {
3254 struct ci_power_info *pi = ci_get_pi(rdev);
3255 int ret;
3256
3257 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
3258 if (ret)
3259 return ret;
3260
3261 ret = ci_get_dependency_volt_by_clk(rdev,
3262 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3263 engine_clock, &graphic_level->MinVddc);
3264 if (ret)
3265 return ret;
3266
3267 graphic_level->SclkFrequency = engine_clock;
3268
3269 graphic_level->Flags = 0;
3270 graphic_level->MinVddcPhases = 1;
3271
3272 if (pi->vddc_phase_shed_control)
3273 ci_populate_phase_value_based_on_sclk(rdev,
3274 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
3275 engine_clock,
3276 &graphic_level->MinVddcPhases);
3277
3278 graphic_level->ActivityLevel = sclk_activity_level_t;
3279
3280 graphic_level->CcPwrDynRm = 0;
3281 graphic_level->CcPwrDynRm1 = 0;
3282 graphic_level->EnabledForThrottle = 1;
3283 graphic_level->UpH = 0;
3284 graphic_level->DownH = 0;
3285 graphic_level->VoltageDownH = 0;
3286 graphic_level->PowerThrottle = 0;
3287
3288 if (pi->caps_sclk_ds)
3289 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
3290 engine_clock,
3291 CISLAND_MINIMUM_ENGINE_CLOCK);
3292
3293 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3294
3295 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3296 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3297 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3298 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3299 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3300 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3301 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3302 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3303 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3304 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3305 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3306
3307 return 0;
3308 }
3309
ci_populate_all_graphic_levels(struct radeon_device * rdev)3310 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
3311 {
3312 struct ci_power_info *pi = ci_get_pi(rdev);
3313 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3314 u32 level_array_address = pi->dpm_table_start +
3315 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3316 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3317 SMU7_MAX_LEVELS_GRAPHICS;
3318 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3319 u32 i, ret;
3320
3321 memset(levels, 0, level_array_size);
3322
3323 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3324 ret = ci_populate_single_graphic_level(rdev,
3325 dpm_table->sclk_table.dpm_levels[i].value,
3326 (u16)pi->activity_target[i],
3327 &pi->smc_state_table.GraphicsLevel[i]);
3328 if (ret)
3329 return ret;
3330 if (i > 1)
3331 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3332 if (i == (dpm_table->sclk_table.count - 1))
3333 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3334 PPSMC_DISPLAY_WATERMARK_HIGH;
3335 }
3336 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3337
3338 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3339 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3340 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3341
3342 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3343 (u8 *)levels, level_array_size,
3344 pi->sram_end);
3345 if (ret)
3346 return ret;
3347
3348 return 0;
3349 }
3350
ci_populate_ulv_state(struct radeon_device * rdev,SMU7_Discrete_Ulv * ulv_level)3351 static int ci_populate_ulv_state(struct radeon_device *rdev,
3352 SMU7_Discrete_Ulv *ulv_level)
3353 {
3354 return ci_populate_ulv_level(rdev, ulv_level);
3355 }
3356
ci_populate_all_memory_levels(struct radeon_device * rdev)3357 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
3358 {
3359 struct ci_power_info *pi = ci_get_pi(rdev);
3360 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3361 u32 level_array_address = pi->dpm_table_start +
3362 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3363 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3364 SMU7_MAX_LEVELS_MEMORY;
3365 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3366 u32 i, ret;
3367
3368 memset(levels, 0, level_array_size);
3369
3370 for (i = 0; i < dpm_table->mclk_table.count; i++) {
3371 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3372 return -EINVAL;
3373 ret = ci_populate_single_memory_level(rdev,
3374 dpm_table->mclk_table.dpm_levels[i].value,
3375 &pi->smc_state_table.MemoryLevel[i]);
3376 if (ret)
3377 return ret;
3378 }
3379
3380 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3381
3382 if ((dpm_table->mclk_table.count >= 2) &&
3383 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) {
3384 pi->smc_state_table.MemoryLevel[1].MinVddc =
3385 pi->smc_state_table.MemoryLevel[0].MinVddc;
3386 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3387 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3388 }
3389
3390 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3391
3392 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3393 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3394 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3395
3396 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3397 PPSMC_DISPLAY_WATERMARK_HIGH;
3398
3399 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3400 (u8 *)levels, level_array_size,
3401 pi->sram_end);
3402 if (ret)
3403 return ret;
3404
3405 return 0;
3406 }
3407
ci_reset_single_dpm_table(struct radeon_device * rdev,struct ci_single_dpm_table * dpm_table,u32 count)3408 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
3409 struct ci_single_dpm_table* dpm_table,
3410 u32 count)
3411 {
3412 u32 i;
3413
3414 dpm_table->count = count;
3415 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3416 dpm_table->dpm_levels[i].enabled = false;
3417 }
3418
ci_setup_pcie_table_entry(struct ci_single_dpm_table * dpm_table,u32 index,u32 pcie_gen,u32 pcie_lanes)3419 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3420 u32 index, u32 pcie_gen, u32 pcie_lanes)
3421 {
3422 dpm_table->dpm_levels[index].value = pcie_gen;
3423 dpm_table->dpm_levels[index].param1 = pcie_lanes;
3424 dpm_table->dpm_levels[index].enabled = true;
3425 }
3426
ci_setup_default_pcie_tables(struct radeon_device * rdev)3427 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
3428 {
3429 struct ci_power_info *pi = ci_get_pi(rdev);
3430
3431 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3432 return -EINVAL;
3433
3434 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3435 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3436 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3437 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3438 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3439 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3440 }
3441
3442 ci_reset_single_dpm_table(rdev,
3443 &pi->dpm_table.pcie_speed_table,
3444 SMU7_MAX_LEVELS_LINK);
3445
3446 if (rdev->family == CHIP_BONAIRE)
3447 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3448 pi->pcie_gen_powersaving.min,
3449 pi->pcie_lane_powersaving.max);
3450 else
3451 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3452 pi->pcie_gen_powersaving.min,
3453 pi->pcie_lane_powersaving.min);
3454 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3455 pi->pcie_gen_performance.min,
3456 pi->pcie_lane_performance.min);
3457 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3458 pi->pcie_gen_powersaving.min,
3459 pi->pcie_lane_powersaving.max);
3460 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3461 pi->pcie_gen_performance.min,
3462 pi->pcie_lane_performance.max);
3463 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3464 pi->pcie_gen_powersaving.max,
3465 pi->pcie_lane_powersaving.max);
3466 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3467 pi->pcie_gen_performance.max,
3468 pi->pcie_lane_performance.max);
3469
3470 pi->dpm_table.pcie_speed_table.count = 6;
3471
3472 return 0;
3473 }
3474
ci_setup_default_dpm_tables(struct radeon_device * rdev)3475 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3476 {
3477 struct ci_power_info *pi = ci_get_pi(rdev);
3478 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3479 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3480 struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
3481 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3482 struct radeon_cac_leakage_table *std_voltage_table =
3483 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3484 u32 i;
3485
3486 if (allowed_sclk_vddc_table == NULL)
3487 return -EINVAL;
3488 if (allowed_sclk_vddc_table->count < 1)
3489 return -EINVAL;
3490 if (allowed_mclk_table == NULL)
3491 return -EINVAL;
3492 if (allowed_mclk_table->count < 1)
3493 return -EINVAL;
3494
3495 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3496
3497 ci_reset_single_dpm_table(rdev,
3498 &pi->dpm_table.sclk_table,
3499 SMU7_MAX_LEVELS_GRAPHICS);
3500 ci_reset_single_dpm_table(rdev,
3501 &pi->dpm_table.mclk_table,
3502 SMU7_MAX_LEVELS_MEMORY);
3503 ci_reset_single_dpm_table(rdev,
3504 &pi->dpm_table.vddc_table,
3505 SMU7_MAX_LEVELS_VDDC);
3506 ci_reset_single_dpm_table(rdev,
3507 &pi->dpm_table.vddci_table,
3508 SMU7_MAX_LEVELS_VDDCI);
3509 ci_reset_single_dpm_table(rdev,
3510 &pi->dpm_table.mvdd_table,
3511 SMU7_MAX_LEVELS_MVDD);
3512
3513 pi->dpm_table.sclk_table.count = 0;
3514 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3515 if ((i == 0) ||
3516 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3517 allowed_sclk_vddc_table->entries[i].clk)) {
3518 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3519 allowed_sclk_vddc_table->entries[i].clk;
3520 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3521 (i == 0) ? true : false;
3522 pi->dpm_table.sclk_table.count++;
3523 }
3524 }
3525
3526 pi->dpm_table.mclk_table.count = 0;
3527 for (i = 0; i < allowed_mclk_table->count; i++) {
3528 if ((i == 0) ||
3529 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3530 allowed_mclk_table->entries[i].clk)) {
3531 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3532 allowed_mclk_table->entries[i].clk;
3533 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3534 (i == 0) ? true : false;
3535 pi->dpm_table.mclk_table.count++;
3536 }
3537 }
3538
3539 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3540 pi->dpm_table.vddc_table.dpm_levels[i].value =
3541 allowed_sclk_vddc_table->entries[i].v;
3542 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3543 std_voltage_table->entries[i].leakage;
3544 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3545 }
3546 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3547
3548 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3549 if (allowed_mclk_table) {
3550 for (i = 0; i < allowed_mclk_table->count; i++) {
3551 pi->dpm_table.vddci_table.dpm_levels[i].value =
3552 allowed_mclk_table->entries[i].v;
3553 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3554 }
3555 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3556 }
3557
3558 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3559 if (allowed_mclk_table) {
3560 for (i = 0; i < allowed_mclk_table->count; i++) {
3561 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3562 allowed_mclk_table->entries[i].v;
3563 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3564 }
3565 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3566 }
3567
3568 ci_setup_default_pcie_tables(rdev);
3569
3570 return 0;
3571 }
3572
ci_find_boot_level(struct ci_single_dpm_table * table,u32 value,u32 * boot_level)3573 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3574 u32 value, u32 *boot_level)
3575 {
3576 u32 i;
3577 int ret = -EINVAL;
3578
3579 for(i = 0; i < table->count; i++) {
3580 if (value == table->dpm_levels[i].value) {
3581 *boot_level = i;
3582 ret = 0;
3583 }
3584 }
3585
3586 return ret;
3587 }
3588
ci_init_smc_table(struct radeon_device * rdev)3589 static int ci_init_smc_table(struct radeon_device *rdev)
3590 {
3591 struct ci_power_info *pi = ci_get_pi(rdev);
3592 struct ci_ulv_parm *ulv = &pi->ulv;
3593 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3594 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3595 int ret;
3596
3597 ret = ci_setup_default_dpm_tables(rdev);
3598 if (ret)
3599 return ret;
3600
3601 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3602 ci_populate_smc_voltage_tables(rdev, table);
3603
3604 ci_init_fps_limits(rdev);
3605
3606 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3607 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3608
3609 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3610 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3611
3612 if (pi->mem_gddr5)
3613 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3614
3615 if (ulv->supported) {
3616 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3617 if (ret)
3618 return ret;
3619 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3620 }
3621
3622 ret = ci_populate_all_graphic_levels(rdev);
3623 if (ret)
3624 return ret;
3625
3626 ret = ci_populate_all_memory_levels(rdev);
3627 if (ret)
3628 return ret;
3629
3630 ci_populate_smc_link_level(rdev, table);
3631
3632 ret = ci_populate_smc_acpi_level(rdev, table);
3633 if (ret)
3634 return ret;
3635
3636 ret = ci_populate_smc_vce_level(rdev, table);
3637 if (ret)
3638 return ret;
3639
3640 ret = ci_populate_smc_acp_level(rdev, table);
3641 if (ret)
3642 return ret;
3643
3644 ret = ci_populate_smc_samu_level(rdev, table);
3645 if (ret)
3646 return ret;
3647
3648 ret = ci_do_program_memory_timing_parameters(rdev);
3649 if (ret)
3650 return ret;
3651
3652 ret = ci_populate_smc_uvd_level(rdev, table);
3653 if (ret)
3654 return ret;
3655
3656 table->UvdBootLevel = 0;
3657 table->VceBootLevel = 0;
3658 table->AcpBootLevel = 0;
3659 table->SamuBootLevel = 0;
3660 table->GraphicsBootLevel = 0;
3661 table->MemoryBootLevel = 0;
3662
3663 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3664 pi->vbios_boot_state.sclk_bootup_value,
3665 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3666
3667 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3668 pi->vbios_boot_state.mclk_bootup_value,
3669 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3670
3671 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3672 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3673 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3674
3675 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3676
3677 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3678 if (ret)
3679 return ret;
3680
3681 table->UVDInterval = 1;
3682 table->VCEInterval = 1;
3683 table->ACPInterval = 1;
3684 table->SAMUInterval = 1;
3685 table->GraphicsVoltageChangeEnable = 1;
3686 table->GraphicsThermThrottleEnable = 1;
3687 table->GraphicsInterval = 1;
3688 table->VoltageInterval = 1;
3689 table->ThermalInterval = 1;
3690 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3691 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3692 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3693 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3694 table->MemoryVoltageChangeEnable = 1;
3695 table->MemoryInterval = 1;
3696 table->VoltageResponseTime = 0;
3697 table->VddcVddciDelta = 4000;
3698 table->PhaseResponseTime = 0;
3699 table->MemoryThermThrottleEnable = 1;
3700 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3701 table->PCIeGenInterval = 1;
3702 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3703 table->SVI2Enable = 1;
3704 else
3705 table->SVI2Enable = 0;
3706
3707 table->ThermGpio = 17;
3708 table->SclkStepSize = 0x4000;
3709
3710 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3711 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3712 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3713 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3714 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3715 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3716 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3717 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3718 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3719 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3720 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3721 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3722 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3723 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3724
3725 ret = ci_copy_bytes_to_smc(rdev,
3726 pi->dpm_table_start +
3727 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3728 (u8 *)&table->SystemFlags,
3729 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3730 pi->sram_end);
3731 if (ret)
3732 return ret;
3733
3734 return 0;
3735 }
3736
ci_trim_single_dpm_states(struct radeon_device * rdev,struct ci_single_dpm_table * dpm_table,u32 low_limit,u32 high_limit)3737 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3738 struct ci_single_dpm_table *dpm_table,
3739 u32 low_limit, u32 high_limit)
3740 {
3741 u32 i;
3742
3743 for (i = 0; i < dpm_table->count; i++) {
3744 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3745 (dpm_table->dpm_levels[i].value > high_limit))
3746 dpm_table->dpm_levels[i].enabled = false;
3747 else
3748 dpm_table->dpm_levels[i].enabled = true;
3749 }
3750 }
3751
ci_trim_pcie_dpm_states(struct radeon_device * rdev,u32 speed_low,u32 lanes_low,u32 speed_high,u32 lanes_high)3752 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3753 u32 speed_low, u32 lanes_low,
3754 u32 speed_high, u32 lanes_high)
3755 {
3756 struct ci_power_info *pi = ci_get_pi(rdev);
3757 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3758 u32 i, j;
3759
3760 for (i = 0; i < pcie_table->count; i++) {
3761 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3762 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3763 (pcie_table->dpm_levels[i].value > speed_high) ||
3764 (pcie_table->dpm_levels[i].param1 > lanes_high))
3765 pcie_table->dpm_levels[i].enabled = false;
3766 else
3767 pcie_table->dpm_levels[i].enabled = true;
3768 }
3769
3770 for (i = 0; i < pcie_table->count; i++) {
3771 if (pcie_table->dpm_levels[i].enabled) {
3772 for (j = i + 1; j < pcie_table->count; j++) {
3773 if (pcie_table->dpm_levels[j].enabled) {
3774 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3775 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3776 pcie_table->dpm_levels[j].enabled = false;
3777 }
3778 }
3779 }
3780 }
3781 }
3782
ci_trim_dpm_states(struct radeon_device * rdev,struct radeon_ps * radeon_state)3783 static int ci_trim_dpm_states(struct radeon_device *rdev,
3784 struct radeon_ps *radeon_state)
3785 {
3786 struct ci_ps *state = ci_get_ps(radeon_state);
3787 struct ci_power_info *pi = ci_get_pi(rdev);
3788 u32 high_limit_count;
3789
3790 if (state->performance_level_count < 1)
3791 return -EINVAL;
3792
3793 if (state->performance_level_count == 1)
3794 high_limit_count = 0;
3795 else
3796 high_limit_count = 1;
3797
3798 ci_trim_single_dpm_states(rdev,
3799 &pi->dpm_table.sclk_table,
3800 state->performance_levels[0].sclk,
3801 state->performance_levels[high_limit_count].sclk);
3802
3803 ci_trim_single_dpm_states(rdev,
3804 &pi->dpm_table.mclk_table,
3805 state->performance_levels[0].mclk,
3806 state->performance_levels[high_limit_count].mclk);
3807
3808 ci_trim_pcie_dpm_states(rdev,
3809 state->performance_levels[0].pcie_gen,
3810 state->performance_levels[0].pcie_lane,
3811 state->performance_levels[high_limit_count].pcie_gen,
3812 state->performance_levels[high_limit_count].pcie_lane);
3813
3814 return 0;
3815 }
3816
ci_apply_disp_minimum_voltage_request(struct radeon_device * rdev)3817 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3818 {
3819 struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3820 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3821 struct radeon_clock_voltage_dependency_table *vddc_table =
3822 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3823 u32 requested_voltage = 0;
3824 u32 i;
3825
3826 if (disp_voltage_table == NULL)
3827 return -EINVAL;
3828 if (!disp_voltage_table->count)
3829 return -EINVAL;
3830
3831 for (i = 0; i < disp_voltage_table->count; i++) {
3832 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3833 requested_voltage = disp_voltage_table->entries[i].v;
3834 }
3835
3836 for (i = 0; i < vddc_table->count; i++) {
3837 if (requested_voltage <= vddc_table->entries[i].v) {
3838 requested_voltage = vddc_table->entries[i].v;
3839 return (ci_send_msg_to_smc_with_parameter(rdev,
3840 PPSMC_MSG_VddC_Request,
3841 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3842 0 : -EINVAL;
3843 }
3844 }
3845
3846 return -EINVAL;
3847 }
3848
ci_upload_dpm_level_enable_mask(struct radeon_device * rdev)3849 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3850 {
3851 struct ci_power_info *pi = ci_get_pi(rdev);
3852 PPSMC_Result result;
3853
3854 ci_apply_disp_minimum_voltage_request(rdev);
3855
3856 if (!pi->sclk_dpm_key_disabled) {
3857 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3858 result = ci_send_msg_to_smc_with_parameter(rdev,
3859 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3860 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3861 if (result != PPSMC_Result_OK)
3862 return -EINVAL;
3863 }
3864 }
3865
3866 if (!pi->mclk_dpm_key_disabled) {
3867 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3868 result = ci_send_msg_to_smc_with_parameter(rdev,
3869 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3870 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3871 if (result != PPSMC_Result_OK)
3872 return -EINVAL;
3873 }
3874 }
3875 #if 0
3876 if (!pi->pcie_dpm_key_disabled) {
3877 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3878 result = ci_send_msg_to_smc_with_parameter(rdev,
3879 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3880 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3881 if (result != PPSMC_Result_OK)
3882 return -EINVAL;
3883 }
3884 }
3885 #endif
3886 return 0;
3887 }
3888
ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device * rdev,struct radeon_ps * radeon_state)3889 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3890 struct radeon_ps *radeon_state)
3891 {
3892 struct ci_power_info *pi = ci_get_pi(rdev);
3893 struct ci_ps *state = ci_get_ps(radeon_state);
3894 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3895 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3896 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3897 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3898 u32 i;
3899
3900 pi->need_update_smu7_dpm_table = 0;
3901
3902 for (i = 0; i < sclk_table->count; i++) {
3903 if (sclk == sclk_table->dpm_levels[i].value)
3904 break;
3905 }
3906
3907 if (i >= sclk_table->count) {
3908 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3909 } else {
3910 /* XXX check display min clock requirements */
3911 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3912 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3913 }
3914
3915 for (i = 0; i < mclk_table->count; i++) {
3916 if (mclk == mclk_table->dpm_levels[i].value)
3917 break;
3918 }
3919
3920 if (i >= mclk_table->count)
3921 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3922
3923 if (rdev->pm.dpm.current_active_crtc_count !=
3924 rdev->pm.dpm.new_active_crtc_count)
3925 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3926 }
3927
ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device * rdev,struct radeon_ps * radeon_state)3928 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3929 struct radeon_ps *radeon_state)
3930 {
3931 struct ci_power_info *pi = ci_get_pi(rdev);
3932 struct ci_ps *state = ci_get_ps(radeon_state);
3933 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3934 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3935 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3936 int ret;
3937
3938 if (!pi->need_update_smu7_dpm_table)
3939 return 0;
3940
3941 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3942 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3943
3944 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3945 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3946
3947 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3948 ret = ci_populate_all_graphic_levels(rdev);
3949 if (ret)
3950 return ret;
3951 }
3952
3953 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3954 ret = ci_populate_all_memory_levels(rdev);
3955 if (ret)
3956 return ret;
3957 }
3958
3959 return 0;
3960 }
3961
ci_enable_uvd_dpm(struct radeon_device * rdev,bool enable)3962 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3963 {
3964 struct ci_power_info *pi = ci_get_pi(rdev);
3965 const struct radeon_clock_and_voltage_limits *max_limits;
3966 int i;
3967
3968 if (rdev->pm.dpm.ac_power)
3969 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3970 else
3971 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3972
3973 if (enable) {
3974 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3975
3976 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3977 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3978 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3979
3980 if (!pi->caps_uvd_dpm)
3981 break;
3982 }
3983 }
3984
3985 ci_send_msg_to_smc_with_parameter(rdev,
3986 PPSMC_MSG_UVDDPM_SetEnabledMask,
3987 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3988
3989 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3990 pi->uvd_enabled = true;
3991 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3992 ci_send_msg_to_smc_with_parameter(rdev,
3993 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3994 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3995 }
3996 } else {
3997 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3998 pi->uvd_enabled = false;
3999 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
4000 ci_send_msg_to_smc_with_parameter(rdev,
4001 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4002 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4003 }
4004 }
4005
4006 return (ci_send_msg_to_smc(rdev, enable ?
4007 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
4008 0 : -EINVAL;
4009 }
4010
ci_enable_vce_dpm(struct radeon_device * rdev,bool enable)4011 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
4012 {
4013 struct ci_power_info *pi = ci_get_pi(rdev);
4014 const struct radeon_clock_and_voltage_limits *max_limits;
4015 int i;
4016
4017 if (rdev->pm.dpm.ac_power)
4018 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4019 else
4020 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4021
4022 if (enable) {
4023 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
4024 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4025 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4026 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
4027
4028 if (!pi->caps_vce_dpm)
4029 break;
4030 }
4031 }
4032
4033 ci_send_msg_to_smc_with_parameter(rdev,
4034 PPSMC_MSG_VCEDPM_SetEnabledMask,
4035 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
4036 }
4037
4038 return (ci_send_msg_to_smc(rdev, enable ?
4039 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
4040 0 : -EINVAL;
4041 }
4042
4043 #if 0
4044 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
4045 {
4046 struct ci_power_info *pi = ci_get_pi(rdev);
4047 const struct radeon_clock_and_voltage_limits *max_limits;
4048 int i;
4049
4050 if (rdev->pm.dpm.ac_power)
4051 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4052 else
4053 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4054
4055 if (enable) {
4056 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4057 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4058 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4059 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4060
4061 if (!pi->caps_samu_dpm)
4062 break;
4063 }
4064 }
4065
4066 ci_send_msg_to_smc_with_parameter(rdev,
4067 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4068 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4069 }
4070 return (ci_send_msg_to_smc(rdev, enable ?
4071 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4072 0 : -EINVAL;
4073 }
4074
4075 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
4076 {
4077 struct ci_power_info *pi = ci_get_pi(rdev);
4078 const struct radeon_clock_and_voltage_limits *max_limits;
4079 int i;
4080
4081 if (rdev->pm.dpm.ac_power)
4082 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4083 else
4084 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4085
4086 if (enable) {
4087 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4088 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4089 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4090 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4091
4092 if (!pi->caps_acp_dpm)
4093 break;
4094 }
4095 }
4096
4097 ci_send_msg_to_smc_with_parameter(rdev,
4098 PPSMC_MSG_ACPDPM_SetEnabledMask,
4099 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4100 }
4101
4102 return (ci_send_msg_to_smc(rdev, enable ?
4103 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4104 0 : -EINVAL;
4105 }
4106 #endif
4107
ci_update_uvd_dpm(struct radeon_device * rdev,bool gate)4108 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
4109 {
4110 struct ci_power_info *pi = ci_get_pi(rdev);
4111 u32 tmp;
4112
4113 if (!gate) {
4114 if (pi->caps_uvd_dpm ||
4115 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4116 pi->smc_state_table.UvdBootLevel = 0;
4117 else
4118 pi->smc_state_table.UvdBootLevel =
4119 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4120
4121 tmp = RREG32_SMC(DPM_TABLE_475);
4122 tmp &= ~UvdBootLevel_MASK;
4123 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
4124 WREG32_SMC(DPM_TABLE_475, tmp);
4125 }
4126
4127 return ci_enable_uvd_dpm(rdev, !gate);
4128 }
4129
ci_get_vce_boot_level(struct radeon_device * rdev)4130 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
4131 {
4132 u8 i;
4133 u32 min_evclk = 30000; /* ??? */
4134 struct radeon_vce_clock_voltage_dependency_table *table =
4135 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4136
4137 for (i = 0; i < table->count; i++) {
4138 if (table->entries[i].evclk >= min_evclk)
4139 return i;
4140 }
4141
4142 return table->count - 1;
4143 }
4144
ci_update_vce_dpm(struct radeon_device * rdev,struct radeon_ps * radeon_new_state,struct radeon_ps * radeon_current_state)4145 static int ci_update_vce_dpm(struct radeon_device *rdev,
4146 struct radeon_ps *radeon_new_state,
4147 struct radeon_ps *radeon_current_state)
4148 {
4149 struct ci_power_info *pi = ci_get_pi(rdev);
4150 int ret = 0;
4151 u32 tmp;
4152
4153 if (radeon_current_state->evclk != radeon_new_state->evclk) {
4154 if (radeon_new_state->evclk) {
4155 /* turn the clocks on when encoding */
4156 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
4157
4158 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
4159 tmp = RREG32_SMC(DPM_TABLE_475);
4160 tmp &= ~VceBootLevel_MASK;
4161 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
4162 WREG32_SMC(DPM_TABLE_475, tmp);
4163
4164 ret = ci_enable_vce_dpm(rdev, true);
4165 } else {
4166 /* turn the clocks off when not encoding */
4167 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
4168
4169 ret = ci_enable_vce_dpm(rdev, false);
4170 }
4171 }
4172 return ret;
4173 }
4174
4175 #if 0
4176 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
4177 {
4178 return ci_enable_samu_dpm(rdev, gate);
4179 }
4180
4181 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
4182 {
4183 struct ci_power_info *pi = ci_get_pi(rdev);
4184 u32 tmp;
4185
4186 if (!gate) {
4187 pi->smc_state_table.AcpBootLevel = 0;
4188
4189 tmp = RREG32_SMC(DPM_TABLE_475);
4190 tmp &= ~AcpBootLevel_MASK;
4191 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4192 WREG32_SMC(DPM_TABLE_475, tmp);
4193 }
4194
4195 return ci_enable_acp_dpm(rdev, !gate);
4196 }
4197 #endif
4198
ci_generate_dpm_level_enable_mask(struct radeon_device * rdev,struct radeon_ps * radeon_state)4199 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
4200 struct radeon_ps *radeon_state)
4201 {
4202 struct ci_power_info *pi = ci_get_pi(rdev);
4203 int ret;
4204
4205 ret = ci_trim_dpm_states(rdev, radeon_state);
4206 if (ret)
4207 return ret;
4208
4209 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4210 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4211 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4212 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4213 pi->last_mclk_dpm_enable_mask =
4214 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4215 if (pi->uvd_enabled) {
4216 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4217 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4218 }
4219 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4220 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4221
4222 return 0;
4223 }
4224
ci_get_lowest_enabled_level(struct radeon_device * rdev,u32 level_mask)4225 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
4226 u32 level_mask)
4227 {
4228 u32 level = 0;
4229
4230 while ((level_mask & (1 << level)) == 0)
4231 level++;
4232
4233 return level;
4234 }
4235
4236
ci_dpm_force_performance_level(struct radeon_device * rdev,enum radeon_dpm_forced_level level)4237 int ci_dpm_force_performance_level(struct radeon_device *rdev,
4238 enum radeon_dpm_forced_level level)
4239 {
4240 struct ci_power_info *pi = ci_get_pi(rdev);
4241 u32 tmp, levels, i;
4242 int ret;
4243
4244 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
4245 if ((!pi->pcie_dpm_key_disabled) &&
4246 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4247 levels = 0;
4248 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4249 while (tmp >>= 1)
4250 levels++;
4251 if (levels) {
4252 ret = ci_dpm_force_state_pcie(rdev, level);
4253 if (ret)
4254 return ret;
4255 for (i = 0; i < rdev->usec_timeout; i++) {
4256 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4257 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4258 if (tmp == levels)
4259 break;
4260 udelay(1);
4261 }
4262 }
4263 }
4264 if ((!pi->sclk_dpm_key_disabled) &&
4265 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4266 levels = 0;
4267 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4268 while (tmp >>= 1)
4269 levels++;
4270 if (levels) {
4271 ret = ci_dpm_force_state_sclk(rdev, levels);
4272 if (ret)
4273 return ret;
4274 for (i = 0; i < rdev->usec_timeout; i++) {
4275 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4276 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4277 if (tmp == levels)
4278 break;
4279 udelay(1);
4280 }
4281 }
4282 }
4283 if ((!pi->mclk_dpm_key_disabled) &&
4284 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4285 levels = 0;
4286 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4287 while (tmp >>= 1)
4288 levels++;
4289 if (levels) {
4290 ret = ci_dpm_force_state_mclk(rdev, levels);
4291 if (ret)
4292 return ret;
4293 for (i = 0; i < rdev->usec_timeout; i++) {
4294 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4295 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4296 if (tmp == levels)
4297 break;
4298 udelay(1);
4299 }
4300 }
4301 }
4302 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
4303 if ((!pi->sclk_dpm_key_disabled) &&
4304 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4305 levels = ci_get_lowest_enabled_level(rdev,
4306 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4307 ret = ci_dpm_force_state_sclk(rdev, levels);
4308 if (ret)
4309 return ret;
4310 for (i = 0; i < rdev->usec_timeout; i++) {
4311 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4312 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4313 if (tmp == levels)
4314 break;
4315 udelay(1);
4316 }
4317 }
4318 if ((!pi->mclk_dpm_key_disabled) &&
4319 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4320 levels = ci_get_lowest_enabled_level(rdev,
4321 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4322 ret = ci_dpm_force_state_mclk(rdev, levels);
4323 if (ret)
4324 return ret;
4325 for (i = 0; i < rdev->usec_timeout; i++) {
4326 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4327 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4328 if (tmp == levels)
4329 break;
4330 udelay(1);
4331 }
4332 }
4333 if ((!pi->pcie_dpm_key_disabled) &&
4334 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4335 levels = ci_get_lowest_enabled_level(rdev,
4336 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4337 ret = ci_dpm_force_state_pcie(rdev, levels);
4338 if (ret)
4339 return ret;
4340 for (i = 0; i < rdev->usec_timeout; i++) {
4341 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4342 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4343 if (tmp == levels)
4344 break;
4345 udelay(1);
4346 }
4347 }
4348 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
4349 if (!pi->pcie_dpm_key_disabled) {
4350 PPSMC_Result smc_result;
4351
4352 smc_result = ci_send_msg_to_smc(rdev,
4353 PPSMC_MSG_PCIeDPM_UnForceLevel);
4354 if (smc_result != PPSMC_Result_OK)
4355 return -EINVAL;
4356 }
4357 ret = ci_upload_dpm_level_enable_mask(rdev);
4358 if (ret)
4359 return ret;
4360 }
4361
4362 rdev->pm.dpm.forced_level = level;
4363
4364 return 0;
4365 }
4366
ci_set_mc_special_registers(struct radeon_device * rdev,struct ci_mc_reg_table * table)4367 static int ci_set_mc_special_registers(struct radeon_device *rdev,
4368 struct ci_mc_reg_table *table)
4369 {
4370 struct ci_power_info *pi = ci_get_pi(rdev);
4371 u8 i, j, k;
4372 u32 temp_reg;
4373
4374 for (i = 0, j = table->last; i < table->last; i++) {
4375 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4376 return -EINVAL;
4377 switch(table->mc_reg_address[i].s1 << 2) {
4378 case MC_SEQ_MISC1:
4379 temp_reg = RREG32(MC_PMG_CMD_EMRS);
4380 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
4381 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4382 for (k = 0; k < table->num_entries; k++) {
4383 table->mc_reg_table_entry[k].mc_data[j] =
4384 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4385 }
4386 j++;
4387 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4388 return -EINVAL;
4389
4390 temp_reg = RREG32(MC_PMG_CMD_MRS);
4391 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
4392 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4393 for (k = 0; k < table->num_entries; k++) {
4394 table->mc_reg_table_entry[k].mc_data[j] =
4395 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4396 if (!pi->mem_gddr5)
4397 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4398 }
4399 j++;
4400 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4401 return -EINVAL;
4402
4403 if (!pi->mem_gddr5) {
4404 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
4405 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
4406 for (k = 0; k < table->num_entries; k++) {
4407 table->mc_reg_table_entry[k].mc_data[j] =
4408 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4409 }
4410 j++;
4411 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4412 return -EINVAL;
4413 }
4414 break;
4415 case MC_SEQ_RESERVE_M:
4416 temp_reg = RREG32(MC_PMG_CMD_MRS1);
4417 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
4418 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4419 for (k = 0; k < table->num_entries; k++) {
4420 table->mc_reg_table_entry[k].mc_data[j] =
4421 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4422 }
4423 j++;
4424 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4425 return -EINVAL;
4426 break;
4427 default:
4428 break;
4429 }
4430
4431 }
4432
4433 table->last = j;
4434
4435 return 0;
4436 }
4437
ci_check_s0_mc_reg_index(u16 in_reg,u16 * out_reg)4438 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4439 {
4440 bool result = true;
4441
4442 switch(in_reg) {
4443 case MC_SEQ_RAS_TIMING >> 2:
4444 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
4445 break;
4446 case MC_SEQ_DLL_STBY >> 2:
4447 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
4448 break;
4449 case MC_SEQ_G5PDX_CMD0 >> 2:
4450 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
4451 break;
4452 case MC_SEQ_G5PDX_CMD1 >> 2:
4453 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
4454 break;
4455 case MC_SEQ_G5PDX_CTRL >> 2:
4456 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
4457 break;
4458 case MC_SEQ_CAS_TIMING >> 2:
4459 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
4460 break;
4461 case MC_SEQ_MISC_TIMING >> 2:
4462 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
4463 break;
4464 case MC_SEQ_MISC_TIMING2 >> 2:
4465 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
4466 break;
4467 case MC_SEQ_PMG_DVS_CMD >> 2:
4468 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
4469 break;
4470 case MC_SEQ_PMG_DVS_CTL >> 2:
4471 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
4472 break;
4473 case MC_SEQ_RD_CTL_D0 >> 2:
4474 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
4475 break;
4476 case MC_SEQ_RD_CTL_D1 >> 2:
4477 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
4478 break;
4479 case MC_SEQ_WR_CTL_D0 >> 2:
4480 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
4481 break;
4482 case MC_SEQ_WR_CTL_D1 >> 2:
4483 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
4484 break;
4485 case MC_PMG_CMD_EMRS >> 2:
4486 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4487 break;
4488 case MC_PMG_CMD_MRS >> 2:
4489 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4490 break;
4491 case MC_PMG_CMD_MRS1 >> 2:
4492 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4493 break;
4494 case MC_SEQ_PMG_TIMING >> 2:
4495 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
4496 break;
4497 case MC_PMG_CMD_MRS2 >> 2:
4498 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
4499 break;
4500 case MC_SEQ_WR_CTL_2 >> 2:
4501 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4502 break;
4503 default:
4504 result = false;
4505 break;
4506 }
4507
4508 return result;
4509 }
4510
ci_set_valid_flag(struct ci_mc_reg_table * table)4511 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4512 {
4513 u8 i, j;
4514
4515 for (i = 0; i < table->last; i++) {
4516 for (j = 1; j < table->num_entries; j++) {
4517 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4518 table->mc_reg_table_entry[j].mc_data[i]) {
4519 table->valid_flag |= 1 << i;
4520 break;
4521 }
4522 }
4523 }
4524 }
4525
ci_set_s0_mc_reg_index(struct ci_mc_reg_table * table)4526 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4527 {
4528 u32 i;
4529 u16 address;
4530
4531 for (i = 0; i < table->last; i++) {
4532 table->mc_reg_address[i].s0 =
4533 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4534 address : table->mc_reg_address[i].s1;
4535 }
4536 }
4537
ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table * table,struct ci_mc_reg_table * ci_table)4538 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4539 struct ci_mc_reg_table *ci_table)
4540 {
4541 u8 i, j;
4542
4543 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4544 return -EINVAL;
4545 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4546 return -EINVAL;
4547
4548 for (i = 0; i < table->last; i++)
4549 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4550
4551 ci_table->last = table->last;
4552
4553 for (i = 0; i < table->num_entries; i++) {
4554 ci_table->mc_reg_table_entry[i].mclk_max =
4555 table->mc_reg_table_entry[i].mclk_max;
4556 for (j = 0; j < table->last; j++)
4557 ci_table->mc_reg_table_entry[i].mc_data[j] =
4558 table->mc_reg_table_entry[i].mc_data[j];
4559 }
4560 ci_table->num_entries = table->num_entries;
4561
4562 return 0;
4563 }
4564
ci_register_patching_mc_seq(struct radeon_device * rdev,struct ci_mc_reg_table * table)4565 static int ci_register_patching_mc_seq(struct radeon_device *rdev,
4566 struct ci_mc_reg_table *table)
4567 {
4568 u8 i, k;
4569 u32 tmp;
4570 bool patch;
4571
4572 tmp = RREG32(MC_SEQ_MISC0);
4573 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4574
4575 if (patch &&
4576 ((rdev->pdev->device == 0x67B0) ||
4577 (rdev->pdev->device == 0x67B1))) {
4578 for (i = 0; i < table->last; i++) {
4579 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4580 return -EINVAL;
4581 switch(table->mc_reg_address[i].s1 >> 2) {
4582 case MC_SEQ_MISC1:
4583 for (k = 0; k < table->num_entries; k++) {
4584 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4585 (table->mc_reg_table_entry[k].mclk_max == 137500))
4586 table->mc_reg_table_entry[k].mc_data[i] =
4587 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4588 0x00000007;
4589 }
4590 break;
4591 case MC_SEQ_WR_CTL_D0:
4592 for (k = 0; k < table->num_entries; k++) {
4593 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4594 (table->mc_reg_table_entry[k].mclk_max == 137500))
4595 table->mc_reg_table_entry[k].mc_data[i] =
4596 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4597 0x0000D0DD;
4598 }
4599 break;
4600 case MC_SEQ_WR_CTL_D1:
4601 for (k = 0; k < table->num_entries; k++) {
4602 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4603 (table->mc_reg_table_entry[k].mclk_max == 137500))
4604 table->mc_reg_table_entry[k].mc_data[i] =
4605 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4606 0x0000D0DD;
4607 }
4608 break;
4609 case MC_SEQ_WR_CTL_2:
4610 for (k = 0; k < table->num_entries; k++) {
4611 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4612 (table->mc_reg_table_entry[k].mclk_max == 137500))
4613 table->mc_reg_table_entry[k].mc_data[i] = 0;
4614 }
4615 break;
4616 case MC_SEQ_CAS_TIMING:
4617 for (k = 0; k < table->num_entries; k++) {
4618 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4619 table->mc_reg_table_entry[k].mc_data[i] =
4620 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4621 0x000C0140;
4622 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4623 table->mc_reg_table_entry[k].mc_data[i] =
4624 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4625 0x000C0150;
4626 }
4627 break;
4628 case MC_SEQ_MISC_TIMING:
4629 for (k = 0; k < table->num_entries; k++) {
4630 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4631 table->mc_reg_table_entry[k].mc_data[i] =
4632 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4633 0x00000030;
4634 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4635 table->mc_reg_table_entry[k].mc_data[i] =
4636 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4637 0x00000035;
4638 }
4639 break;
4640 default:
4641 break;
4642 }
4643 }
4644
4645 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4646 tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
4647 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4648 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4649 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
4650 }
4651
4652 return 0;
4653 }
4654
ci_initialize_mc_reg_table(struct radeon_device * rdev)4655 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4656 {
4657 struct ci_power_info *pi = ci_get_pi(rdev);
4658 struct atom_mc_reg_table *table;
4659 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4660 u8 module_index = rv770_get_memory_module_index(rdev);
4661 int ret;
4662
4663 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4664 if (!table)
4665 return -ENOMEM;
4666
4667 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4668 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4669 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4670 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4671 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4672 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4673 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4674 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4675 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4676 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4677 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4678 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4679 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4680 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4681 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4682 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4683 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4684 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4685 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4686 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4687
4688 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4689 if (ret)
4690 goto init_mc_done;
4691
4692 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4693 if (ret)
4694 goto init_mc_done;
4695
4696 ci_set_s0_mc_reg_index(ci_table);
4697
4698 ret = ci_register_patching_mc_seq(rdev, ci_table);
4699 if (ret)
4700 goto init_mc_done;
4701
4702 ret = ci_set_mc_special_registers(rdev, ci_table);
4703 if (ret)
4704 goto init_mc_done;
4705
4706 ci_set_valid_flag(ci_table);
4707
4708 init_mc_done:
4709 kfree(table);
4710
4711 return ret;
4712 }
4713
ci_populate_mc_reg_addresses(struct radeon_device * rdev,SMU7_Discrete_MCRegisters * mc_reg_table)4714 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4715 SMU7_Discrete_MCRegisters *mc_reg_table)
4716 {
4717 struct ci_power_info *pi = ci_get_pi(rdev);
4718 u32 i, j;
4719
4720 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4721 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4722 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4723 return -EINVAL;
4724 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4725 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4726 i++;
4727 }
4728 }
4729
4730 mc_reg_table->last = (u8)i;
4731
4732 return 0;
4733 }
4734
ci_convert_mc_registers(const struct ci_mc_reg_entry * entry,SMU7_Discrete_MCRegisterSet * data,u32 num_entries,u32 valid_flag)4735 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4736 SMU7_Discrete_MCRegisterSet *data,
4737 u32 num_entries, u32 valid_flag)
4738 {
4739 u32 i, j;
4740
4741 for (i = 0, j = 0; j < num_entries; j++) {
4742 if (valid_flag & (1 << j)) {
4743 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4744 i++;
4745 }
4746 }
4747 }
4748
ci_convert_mc_reg_table_entry_to_smc(struct radeon_device * rdev,const u32 memory_clock,SMU7_Discrete_MCRegisterSet * mc_reg_table_data)4749 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4750 const u32 memory_clock,
4751 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4752 {
4753 struct ci_power_info *pi = ci_get_pi(rdev);
4754 u32 i = 0;
4755
4756 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4757 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4758 break;
4759 }
4760
4761 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4762 --i;
4763
4764 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4765 mc_reg_table_data, pi->mc_reg_table.last,
4766 pi->mc_reg_table.valid_flag);
4767 }
4768
ci_convert_mc_reg_table_to_smc(struct radeon_device * rdev,SMU7_Discrete_MCRegisters * mc_reg_table)4769 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4770 SMU7_Discrete_MCRegisters *mc_reg_table)
4771 {
4772 struct ci_power_info *pi = ci_get_pi(rdev);
4773 u32 i;
4774
4775 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4776 ci_convert_mc_reg_table_entry_to_smc(rdev,
4777 pi->dpm_table.mclk_table.dpm_levels[i].value,
4778 &mc_reg_table->data[i]);
4779 }
4780
ci_populate_initial_mc_reg_table(struct radeon_device * rdev)4781 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4782 {
4783 struct ci_power_info *pi = ci_get_pi(rdev);
4784 int ret;
4785
4786 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4787
4788 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4789 if (ret)
4790 return ret;
4791 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4792
4793 return ci_copy_bytes_to_smc(rdev,
4794 pi->mc_reg_table_start,
4795 (u8 *)&pi->smc_mc_reg_table,
4796 sizeof(SMU7_Discrete_MCRegisters),
4797 pi->sram_end);
4798 }
4799
ci_update_and_upload_mc_reg_table(struct radeon_device * rdev)4800 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4801 {
4802 struct ci_power_info *pi = ci_get_pi(rdev);
4803
4804 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4805 return 0;
4806
4807 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4808
4809 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4810
4811 return ci_copy_bytes_to_smc(rdev,
4812 pi->mc_reg_table_start +
4813 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4814 (u8 *)&pi->smc_mc_reg_table.data[0],
4815 sizeof(SMU7_Discrete_MCRegisterSet) *
4816 pi->dpm_table.mclk_table.count,
4817 pi->sram_end);
4818 }
4819
ci_enable_voltage_control(struct radeon_device * rdev)4820 static void ci_enable_voltage_control(struct radeon_device *rdev)
4821 {
4822 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4823
4824 tmp |= VOLT_PWRMGT_EN;
4825 WREG32_SMC(GENERAL_PWRMGT, tmp);
4826 }
4827
ci_get_maximum_link_speed(struct radeon_device * rdev,struct radeon_ps * radeon_state)4828 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4829 struct radeon_ps *radeon_state)
4830 {
4831 struct ci_ps *state = ci_get_ps(radeon_state);
4832 int i;
4833 u16 pcie_speed, max_speed = 0;
4834
4835 for (i = 0; i < state->performance_level_count; i++) {
4836 pcie_speed = state->performance_levels[i].pcie_gen;
4837 if (max_speed < pcie_speed)
4838 max_speed = pcie_speed;
4839 }
4840
4841 return max_speed;
4842 }
4843
ci_get_current_pcie_speed(struct radeon_device * rdev)4844 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4845 {
4846 u32 speed_cntl = 0;
4847
4848 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4849 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4850
4851 return (u16)speed_cntl;
4852 }
4853
ci_get_current_pcie_lane_number(struct radeon_device * rdev)4854 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4855 {
4856 u32 link_width = 0;
4857
4858 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4859 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4860
4861 switch (link_width) {
4862 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4863 return 1;
4864 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4865 return 2;
4866 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4867 return 4;
4868 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4869 return 8;
4870 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4871 /* not actually supported */
4872 return 12;
4873 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4874 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4875 default:
4876 return 16;
4877 }
4878 }
4879
ci_request_link_speed_change_before_state_change(struct radeon_device * rdev,struct radeon_ps * radeon_new_state,struct radeon_ps * radeon_current_state)4880 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4881 struct radeon_ps *radeon_new_state,
4882 struct radeon_ps *radeon_current_state)
4883 {
4884 struct ci_power_info *pi = ci_get_pi(rdev);
4885 enum radeon_pcie_gen target_link_speed =
4886 ci_get_maximum_link_speed(rdev, radeon_new_state);
4887 enum radeon_pcie_gen current_link_speed;
4888
4889 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4890 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4891 else
4892 current_link_speed = pi->force_pcie_gen;
4893
4894 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4895 pi->pspp_notify_required = false;
4896 if (target_link_speed > current_link_speed) {
4897 switch (target_link_speed) {
4898 #ifdef CONFIG_ACPI
4899 case RADEON_PCIE_GEN3:
4900 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4901 break;
4902 pi->force_pcie_gen = RADEON_PCIE_GEN2;
4903 if (current_link_speed == RADEON_PCIE_GEN2)
4904 break;
4905 case RADEON_PCIE_GEN2:
4906 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4907 break;
4908 #endif
4909 default:
4910 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4911 break;
4912 }
4913 } else {
4914 if (target_link_speed < current_link_speed)
4915 pi->pspp_notify_required = true;
4916 }
4917 }
4918
ci_notify_link_speed_change_after_state_change(struct radeon_device * rdev,struct radeon_ps * radeon_new_state,struct radeon_ps * radeon_current_state)4919 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4920 struct radeon_ps *radeon_new_state,
4921 struct radeon_ps *radeon_current_state)
4922 {
4923 struct ci_power_info *pi = ci_get_pi(rdev);
4924 enum radeon_pcie_gen target_link_speed =
4925 ci_get_maximum_link_speed(rdev, radeon_new_state);
4926 u8 request;
4927
4928 if (pi->pspp_notify_required) {
4929 if (target_link_speed == RADEON_PCIE_GEN3)
4930 request = PCIE_PERF_REQ_PECI_GEN3;
4931 else if (target_link_speed == RADEON_PCIE_GEN2)
4932 request = PCIE_PERF_REQ_PECI_GEN2;
4933 else
4934 request = PCIE_PERF_REQ_PECI_GEN1;
4935
4936 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4937 (ci_get_current_pcie_speed(rdev) > 0))
4938 return;
4939
4940 #ifdef CONFIG_ACPI
4941 radeon_acpi_pcie_performance_request(rdev, request, false);
4942 #endif
4943 }
4944 }
4945
ci_set_private_data_variables_based_on_pptable(struct radeon_device * rdev)4946 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4947 {
4948 struct ci_power_info *pi = ci_get_pi(rdev);
4949 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4950 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4951 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4952 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4953 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4954 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4955
4956 if (allowed_sclk_vddc_table == NULL)
4957 return -EINVAL;
4958 if (allowed_sclk_vddc_table->count < 1)
4959 return -EINVAL;
4960 if (allowed_mclk_vddc_table == NULL)
4961 return -EINVAL;
4962 if (allowed_mclk_vddc_table->count < 1)
4963 return -EINVAL;
4964 if (allowed_mclk_vddci_table == NULL)
4965 return -EINVAL;
4966 if (allowed_mclk_vddci_table->count < 1)
4967 return -EINVAL;
4968
4969 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4970 pi->max_vddc_in_pp_table =
4971 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4972
4973 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4974 pi->max_vddci_in_pp_table =
4975 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4976
4977 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4978 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4979 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4980 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4981 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4982 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4983 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4984 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4985
4986 return 0;
4987 }
4988
ci_patch_with_vddc_leakage(struct radeon_device * rdev,u16 * vddc)4989 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4990 {
4991 struct ci_power_info *pi = ci_get_pi(rdev);
4992 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4993 u32 leakage_index;
4994
4995 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4996 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4997 *vddc = leakage_table->actual_voltage[leakage_index];
4998 break;
4999 }
5000 }
5001 }
5002
ci_patch_with_vddci_leakage(struct radeon_device * rdev,u16 * vddci)5003 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
5004 {
5005 struct ci_power_info *pi = ci_get_pi(rdev);
5006 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
5007 u32 leakage_index;
5008
5009 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5010 if (leakage_table->leakage_id[leakage_index] == *vddci) {
5011 *vddci = leakage_table->actual_voltage[leakage_index];
5012 break;
5013 }
5014 }
5015 }
5016
ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device * rdev,struct radeon_clock_voltage_dependency_table * table)5017 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
5018 struct radeon_clock_voltage_dependency_table *table)
5019 {
5020 u32 i;
5021
5022 if (table) {
5023 for (i = 0; i < table->count; i++)
5024 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
5025 }
5026 }
5027
ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device * rdev,struct radeon_clock_voltage_dependency_table * table)5028 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
5029 struct radeon_clock_voltage_dependency_table *table)
5030 {
5031 u32 i;
5032
5033 if (table) {
5034 for (i = 0; i < table->count; i++)
5035 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
5036 }
5037 }
5038
ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device * rdev,struct radeon_vce_clock_voltage_dependency_table * table)5039 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
5040 struct radeon_vce_clock_voltage_dependency_table *table)
5041 {
5042 u32 i;
5043
5044 if (table) {
5045 for (i = 0; i < table->count; i++)
5046 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
5047 }
5048 }
5049
ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device * rdev,struct radeon_uvd_clock_voltage_dependency_table * table)5050 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
5051 struct radeon_uvd_clock_voltage_dependency_table *table)
5052 {
5053 u32 i;
5054
5055 if (table) {
5056 for (i = 0; i < table->count; i++)
5057 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
5058 }
5059 }
5060
ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device * rdev,struct radeon_phase_shedding_limits_table * table)5061 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
5062 struct radeon_phase_shedding_limits_table *table)
5063 {
5064 u32 i;
5065
5066 if (table) {
5067 for (i = 0; i < table->count; i++)
5068 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
5069 }
5070 }
5071
ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device * rdev,struct radeon_clock_and_voltage_limits * table)5072 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
5073 struct radeon_clock_and_voltage_limits *table)
5074 {
5075 if (table) {
5076 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
5077 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
5078 }
5079 }
5080
ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device * rdev,struct radeon_cac_leakage_table * table)5081 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
5082 struct radeon_cac_leakage_table *table)
5083 {
5084 u32 i;
5085
5086 if (table) {
5087 for (i = 0; i < table->count; i++)
5088 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
5089 }
5090 }
5091
ci_patch_dependency_tables_with_leakage(struct radeon_device * rdev)5092 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
5093 {
5094
5095 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5096 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5097 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5098 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5099 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5100 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5101 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
5102 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5103 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5104 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5105 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5106 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5107 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5108 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5109 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5110 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5111 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
5112 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
5113 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5114 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5115 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5116 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5117 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
5118 &rdev->pm.dpm.dyn_state.cac_leakage_table);
5119
5120 }
5121
ci_get_memory_type(struct radeon_device * rdev)5122 static void ci_get_memory_type(struct radeon_device *rdev)
5123 {
5124 struct ci_power_info *pi = ci_get_pi(rdev);
5125 u32 tmp;
5126
5127 tmp = RREG32(MC_SEQ_MISC0);
5128
5129 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
5130 MC_SEQ_MISC0_GDDR5_VALUE)
5131 pi->mem_gddr5 = true;
5132 else
5133 pi->mem_gddr5 = false;
5134
5135 }
5136
ci_update_current_ps(struct radeon_device * rdev,struct radeon_ps * rps)5137 static void ci_update_current_ps(struct radeon_device *rdev,
5138 struct radeon_ps *rps)
5139 {
5140 struct ci_ps *new_ps = ci_get_ps(rps);
5141 struct ci_power_info *pi = ci_get_pi(rdev);
5142
5143 pi->current_rps = *rps;
5144 pi->current_ps = *new_ps;
5145 pi->current_rps.ps_priv = &pi->current_ps;
5146 }
5147
ci_update_requested_ps(struct radeon_device * rdev,struct radeon_ps * rps)5148 static void ci_update_requested_ps(struct radeon_device *rdev,
5149 struct radeon_ps *rps)
5150 {
5151 struct ci_ps *new_ps = ci_get_ps(rps);
5152 struct ci_power_info *pi = ci_get_pi(rdev);
5153
5154 pi->requested_rps = *rps;
5155 pi->requested_ps = *new_ps;
5156 pi->requested_rps.ps_priv = &pi->requested_ps;
5157 }
5158
ci_dpm_pre_set_power_state(struct radeon_device * rdev)5159 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
5160 {
5161 struct ci_power_info *pi = ci_get_pi(rdev);
5162 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5163 struct radeon_ps *new_ps = &requested_ps;
5164
5165 ci_update_requested_ps(rdev, new_ps);
5166
5167 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
5168
5169 return 0;
5170 }
5171
ci_dpm_post_set_power_state(struct radeon_device * rdev)5172 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
5173 {
5174 struct ci_power_info *pi = ci_get_pi(rdev);
5175 struct radeon_ps *new_ps = &pi->requested_rps;
5176
5177 ci_update_current_ps(rdev, new_ps);
5178 }
5179
5180
ci_dpm_setup_asic(struct radeon_device * rdev)5181 void ci_dpm_setup_asic(struct radeon_device *rdev)
5182 {
5183 int r;
5184
5185 r = ci_mc_load_microcode(rdev);
5186 if (r)
5187 DRM_ERROR("Failed to load MC firmware!\n");
5188 ci_read_clock_registers(rdev);
5189 ci_get_memory_type(rdev);
5190 ci_enable_acpi_power_management(rdev);
5191 ci_init_sclk_t(rdev);
5192 }
5193
ci_dpm_enable(struct radeon_device * rdev)5194 int ci_dpm_enable(struct radeon_device *rdev)
5195 {
5196 struct ci_power_info *pi = ci_get_pi(rdev);
5197 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5198 int ret;
5199
5200 if (ci_is_smc_running(rdev))
5201 return -EINVAL;
5202 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5203 ci_enable_voltage_control(rdev);
5204 ret = ci_construct_voltage_tables(rdev);
5205 if (ret) {
5206 DRM_ERROR("ci_construct_voltage_tables failed\n");
5207 return ret;
5208 }
5209 }
5210 if (pi->caps_dynamic_ac_timing) {
5211 ret = ci_initialize_mc_reg_table(rdev);
5212 if (ret)
5213 pi->caps_dynamic_ac_timing = false;
5214 }
5215 if (pi->dynamic_ss)
5216 ci_enable_spread_spectrum(rdev, true);
5217 if (pi->thermal_protection)
5218 ci_enable_thermal_protection(rdev, true);
5219 ci_program_sstp(rdev);
5220 ci_enable_display_gap(rdev);
5221 ci_program_vc(rdev);
5222 ret = ci_upload_firmware(rdev);
5223 if (ret) {
5224 DRM_ERROR("ci_upload_firmware failed\n");
5225 return ret;
5226 }
5227 ret = ci_process_firmware_header(rdev);
5228 if (ret) {
5229 DRM_ERROR("ci_process_firmware_header failed\n");
5230 return ret;
5231 }
5232 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
5233 if (ret) {
5234 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5235 return ret;
5236 }
5237 ret = ci_init_smc_table(rdev);
5238 if (ret) {
5239 DRM_ERROR("ci_init_smc_table failed\n");
5240 return ret;
5241 }
5242 ret = ci_init_arb_table_index(rdev);
5243 if (ret) {
5244 DRM_ERROR("ci_init_arb_table_index failed\n");
5245 return ret;
5246 }
5247 if (pi->caps_dynamic_ac_timing) {
5248 ret = ci_populate_initial_mc_reg_table(rdev);
5249 if (ret) {
5250 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5251 return ret;
5252 }
5253 }
5254 ret = ci_populate_pm_base(rdev);
5255 if (ret) {
5256 DRM_ERROR("ci_populate_pm_base failed\n");
5257 return ret;
5258 }
5259 ci_dpm_start_smc(rdev);
5260 ci_enable_vr_hot_gpio_interrupt(rdev);
5261 ret = ci_notify_smc_display_change(rdev, false);
5262 if (ret) {
5263 DRM_ERROR("ci_notify_smc_display_change failed\n");
5264 return ret;
5265 }
5266 ci_enable_sclk_control(rdev, true);
5267 ret = ci_enable_ulv(rdev, true);
5268 if (ret) {
5269 DRM_ERROR("ci_enable_ulv failed\n");
5270 return ret;
5271 }
5272 ret = ci_enable_ds_master_switch(rdev, true);
5273 if (ret) {
5274 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5275 return ret;
5276 }
5277 ret = ci_start_dpm(rdev);
5278 if (ret) {
5279 DRM_ERROR("ci_start_dpm failed\n");
5280 return ret;
5281 }
5282 ret = ci_enable_didt(rdev, true);
5283 if (ret) {
5284 DRM_ERROR("ci_enable_didt failed\n");
5285 return ret;
5286 }
5287 ret = ci_enable_smc_cac(rdev, true);
5288 if (ret) {
5289 DRM_ERROR("ci_enable_smc_cac failed\n");
5290 return ret;
5291 }
5292 ret = ci_enable_power_containment(rdev, true);
5293 if (ret) {
5294 DRM_ERROR("ci_enable_power_containment failed\n");
5295 return ret;
5296 }
5297
5298 ret = ci_power_control_set_level(rdev);
5299 if (ret) {
5300 DRM_ERROR("ci_power_control_set_level failed\n");
5301 return ret;
5302 }
5303
5304 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5305
5306 ret = ci_enable_thermal_based_sclk_dpm(rdev, true);
5307 if (ret) {
5308 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5309 return ret;
5310 }
5311
5312 ci_thermal_start_thermal_controller(rdev);
5313
5314 ci_update_current_ps(rdev, boot_ps);
5315
5316 return 0;
5317 }
5318
ci_set_temperature_range(struct radeon_device * rdev)5319 static int ci_set_temperature_range(struct radeon_device *rdev)
5320 {
5321 int ret;
5322
5323 ret = ci_thermal_enable_alert(rdev, false);
5324 if (ret)
5325 return ret;
5326 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5327 if (ret)
5328 return ret;
5329 ret = ci_thermal_enable_alert(rdev, true);
5330 if (ret)
5331 return ret;
5332
5333 return ret;
5334 }
5335
ci_dpm_late_enable(struct radeon_device * rdev)5336 int ci_dpm_late_enable(struct radeon_device *rdev)
5337 {
5338 int ret;
5339
5340 ret = ci_set_temperature_range(rdev);
5341 if (ret)
5342 return ret;
5343
5344 ci_dpm_powergate_uvd(rdev, true);
5345
5346 return 0;
5347 }
5348
ci_dpm_disable(struct radeon_device * rdev)5349 void ci_dpm_disable(struct radeon_device *rdev)
5350 {
5351 struct ci_power_info *pi = ci_get_pi(rdev);
5352 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5353
5354 ci_dpm_powergate_uvd(rdev, false);
5355
5356 if (!ci_is_smc_running(rdev))
5357 return;
5358
5359 ci_thermal_stop_thermal_controller(rdev);
5360
5361 if (pi->thermal_protection)
5362 ci_enable_thermal_protection(rdev, false);
5363 ci_enable_power_containment(rdev, false);
5364 ci_enable_smc_cac(rdev, false);
5365 ci_enable_didt(rdev, false);
5366 ci_enable_spread_spectrum(rdev, false);
5367 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5368 ci_stop_dpm(rdev);
5369 ci_enable_ds_master_switch(rdev, false);
5370 ci_enable_ulv(rdev, false);
5371 ci_clear_vc(rdev);
5372 ci_reset_to_default(rdev);
5373 ci_dpm_stop_smc(rdev);
5374 ci_force_switch_to_arb_f0(rdev);
5375 ci_enable_thermal_based_sclk_dpm(rdev, false);
5376
5377 ci_update_current_ps(rdev, boot_ps);
5378 }
5379
ci_dpm_set_power_state(struct radeon_device * rdev)5380 int ci_dpm_set_power_state(struct radeon_device *rdev)
5381 {
5382 struct ci_power_info *pi = ci_get_pi(rdev);
5383 struct radeon_ps *new_ps = &pi->requested_rps;
5384 struct radeon_ps *old_ps = &pi->current_rps;
5385 int ret;
5386
5387 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
5388 if (pi->pcie_performance_request)
5389 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5390 ret = ci_freeze_sclk_mclk_dpm(rdev);
5391 if (ret) {
5392 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5393 return ret;
5394 }
5395 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
5396 if (ret) {
5397 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5398 return ret;
5399 }
5400 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
5401 if (ret) {
5402 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5403 return ret;
5404 }
5405
5406 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
5407 if (ret) {
5408 DRM_ERROR("ci_update_vce_dpm failed\n");
5409 return ret;
5410 }
5411
5412 ret = ci_update_sclk_t(rdev);
5413 if (ret) {
5414 DRM_ERROR("ci_update_sclk_t failed\n");
5415 return ret;
5416 }
5417 if (pi->caps_dynamic_ac_timing) {
5418 ret = ci_update_and_upload_mc_reg_table(rdev);
5419 if (ret) {
5420 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5421 return ret;
5422 }
5423 }
5424 ret = ci_program_memory_timing_parameters(rdev);
5425 if (ret) {
5426 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5427 return ret;
5428 }
5429 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
5430 if (ret) {
5431 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5432 return ret;
5433 }
5434 ret = ci_upload_dpm_level_enable_mask(rdev);
5435 if (ret) {
5436 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5437 return ret;
5438 }
5439 if (pi->pcie_performance_request)
5440 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5441
5442 return 0;
5443 }
5444
5445 #if 0
5446 void ci_dpm_reset_asic(struct radeon_device *rdev)
5447 {
5448 ci_set_boot_state(rdev);
5449 }
5450 #endif
5451
ci_dpm_display_configuration_changed(struct radeon_device * rdev)5452 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
5453 {
5454 ci_program_display_gap(rdev);
5455 }
5456
5457 union power_info {
5458 struct _ATOM_POWERPLAY_INFO info;
5459 struct _ATOM_POWERPLAY_INFO_V2 info_2;
5460 struct _ATOM_POWERPLAY_INFO_V3 info_3;
5461 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5462 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5463 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5464 };
5465
5466 union pplib_clock_info {
5467 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5468 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5469 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5470 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5471 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5472 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5473 };
5474
5475 union pplib_power_state {
5476 struct _ATOM_PPLIB_STATE v1;
5477 struct _ATOM_PPLIB_STATE_V2 v2;
5478 };
5479
ci_parse_pplib_non_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info,u8 table_rev)5480 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
5481 struct radeon_ps *rps,
5482 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5483 u8 table_rev)
5484 {
5485 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5486 rps->class = le16_to_cpu(non_clock_info->usClassification);
5487 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5488
5489 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5490 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5491 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5492 } else {
5493 rps->vclk = 0;
5494 rps->dclk = 0;
5495 }
5496
5497 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5498 rdev->pm.dpm.boot_ps = rps;
5499 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5500 rdev->pm.dpm.uvd_ps = rps;
5501 }
5502
ci_parse_pplib_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,int index,union pplib_clock_info * clock_info)5503 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
5504 struct radeon_ps *rps, int index,
5505 union pplib_clock_info *clock_info)
5506 {
5507 struct ci_power_info *pi = ci_get_pi(rdev);
5508 struct ci_ps *ps = ci_get_ps(rps);
5509 struct ci_pl *pl = &ps->performance_levels[index];
5510
5511 ps->performance_level_count = index + 1;
5512
5513 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5514 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5515 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5516 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5517
5518 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
5519 pi->sys_pcie_mask,
5520 pi->vbios_boot_state.pcie_gen_bootup_value,
5521 clock_info->ci.ucPCIEGen);
5522 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
5523 pi->vbios_boot_state.pcie_lane_bootup_value,
5524 le16_to_cpu(clock_info->ci.usPCIELane));
5525
5526 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5527 pi->acpi_pcie_gen = pl->pcie_gen;
5528 }
5529
5530 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5531 pi->ulv.supported = true;
5532 pi->ulv.pl = *pl;
5533 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5534 }
5535
5536 /* patch up boot state */
5537 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5538 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5539 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5540 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5541 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5542 }
5543
5544 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5545 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5546 pi->use_pcie_powersaving_levels = true;
5547 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5548 pi->pcie_gen_powersaving.max = pl->pcie_gen;
5549 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5550 pi->pcie_gen_powersaving.min = pl->pcie_gen;
5551 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5552 pi->pcie_lane_powersaving.max = pl->pcie_lane;
5553 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5554 pi->pcie_lane_powersaving.min = pl->pcie_lane;
5555 break;
5556 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5557 pi->use_pcie_performance_levels = true;
5558 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5559 pi->pcie_gen_performance.max = pl->pcie_gen;
5560 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5561 pi->pcie_gen_performance.min = pl->pcie_gen;
5562 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5563 pi->pcie_lane_performance.max = pl->pcie_lane;
5564 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5565 pi->pcie_lane_performance.min = pl->pcie_lane;
5566 break;
5567 default:
5568 break;
5569 }
5570 }
5571
ci_parse_power_table(struct radeon_device * rdev)5572 static int ci_parse_power_table(struct radeon_device *rdev)
5573 {
5574 struct radeon_mode_info *mode_info = &rdev->mode_info;
5575 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5576 union pplib_power_state *power_state;
5577 int i, j, k, non_clock_array_index, clock_array_index;
5578 union pplib_clock_info *clock_info;
5579 struct _StateArray *state_array;
5580 struct _ClockInfoArray *clock_info_array;
5581 struct _NonClockInfoArray *non_clock_info_array;
5582 union power_info *power_info;
5583 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5584 u16 data_offset;
5585 u8 frev, crev;
5586 u8 *power_state_offset;
5587 struct ci_ps *ps;
5588
5589 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
5590 &frev, &crev, &data_offset))
5591 return -EINVAL;
5592 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5593
5594 state_array = (struct _StateArray *)
5595 (mode_info->atom_context->bios + data_offset +
5596 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5597 clock_info_array = (struct _ClockInfoArray *)
5598 (mode_info->atom_context->bios + data_offset +
5599 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5600 non_clock_info_array = (struct _NonClockInfoArray *)
5601 (mode_info->atom_context->bios + data_offset +
5602 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5603
5604 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
5605 state_array->ucNumEntries, GFP_KERNEL);
5606 if (!rdev->pm.dpm.ps)
5607 return -ENOMEM;
5608 power_state_offset = (u8 *)state_array->states;
5609 for (i = 0; i < state_array->ucNumEntries; i++) {
5610 u8 *idx;
5611 power_state = (union pplib_power_state *)power_state_offset;
5612 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5613 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5614 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5615 if (!rdev->pm.power_state[i].clock_info)
5616 return -EINVAL;
5617 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5618 if (ps == NULL) {
5619 kfree(rdev->pm.dpm.ps);
5620 return -ENOMEM;
5621 }
5622 rdev->pm.dpm.ps[i].ps_priv = ps;
5623 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5624 non_clock_info,
5625 non_clock_info_array->ucEntrySize);
5626 k = 0;
5627 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5628 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5629 clock_array_index = idx[j];
5630 if (clock_array_index >= clock_info_array->ucNumEntries)
5631 continue;
5632 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5633 break;
5634 clock_info = (union pplib_clock_info *)
5635 ((u8 *)&clock_info_array->clockInfo[0] +
5636 (clock_array_index * clock_info_array->ucEntrySize));
5637 ci_parse_pplib_clock_info(rdev,
5638 &rdev->pm.dpm.ps[i], k,
5639 clock_info);
5640 k++;
5641 }
5642 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5643 }
5644 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5645
5646 /* fill in the vce power states */
5647 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5648 u32 sclk, mclk;
5649 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5650 clock_info = (union pplib_clock_info *)
5651 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5652 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5653 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5654 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5655 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5656 rdev->pm.dpm.vce_states[i].sclk = sclk;
5657 rdev->pm.dpm.vce_states[i].mclk = mclk;
5658 }
5659
5660 return 0;
5661 }
5662
ci_get_vbios_boot_values(struct radeon_device * rdev,struct ci_vbios_boot_state * boot_state)5663 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5664 struct ci_vbios_boot_state *boot_state)
5665 {
5666 struct radeon_mode_info *mode_info = &rdev->mode_info;
5667 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5668 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5669 u8 frev, crev;
5670 u16 data_offset;
5671
5672 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5673 &frev, &crev, &data_offset)) {
5674 firmware_info =
5675 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5676 data_offset);
5677 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5678 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5679 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5680 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5681 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5682 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5683 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5684
5685 return 0;
5686 }
5687 return -EINVAL;
5688 }
5689
ci_dpm_fini(struct radeon_device * rdev)5690 void ci_dpm_fini(struct radeon_device *rdev)
5691 {
5692 int i;
5693
5694 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5695 kfree(rdev->pm.dpm.ps[i].ps_priv);
5696 }
5697 kfree(rdev->pm.dpm.ps);
5698 kfree(rdev->pm.dpm.priv);
5699 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5700 r600_free_extended_power_table(rdev);
5701 }
5702
ci_dpm_init(struct radeon_device * rdev)5703 int ci_dpm_init(struct radeon_device *rdev)
5704 {
5705 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5706 SMU7_Discrete_DpmTable *dpm_table;
5707 struct radeon_gpio_rec gpio;
5708 u16 data_offset, size;
5709 u8 frev, crev;
5710 struct ci_power_info *pi;
5711 int ret;
5712 u32 mask;
5713
5714 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5715 if (pi == NULL)
5716 return -ENOMEM;
5717 rdev->pm.dpm.priv = pi;
5718
5719 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5720 if (ret)
5721 pi->sys_pcie_mask = 0;
5722 else
5723 pi->sys_pcie_mask = mask;
5724 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5725
5726 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5727 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5728 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5729 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5730
5731 pi->pcie_lane_performance.max = 0;
5732 pi->pcie_lane_performance.min = 16;
5733 pi->pcie_lane_powersaving.max = 0;
5734 pi->pcie_lane_powersaving.min = 16;
5735
5736 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5737 if (ret) {
5738 ci_dpm_fini(rdev);
5739 return ret;
5740 }
5741
5742 ret = r600_get_platform_caps(rdev);
5743 if (ret) {
5744 ci_dpm_fini(rdev);
5745 return ret;
5746 }
5747
5748 ret = r600_parse_extended_power_table(rdev);
5749 if (ret) {
5750 ci_dpm_fini(rdev);
5751 return ret;
5752 }
5753
5754 ret = ci_parse_power_table(rdev);
5755 if (ret) {
5756 ci_dpm_fini(rdev);
5757 return ret;
5758 }
5759
5760 pi->dll_default_on = false;
5761 pi->sram_end = SMC_RAM_END;
5762
5763 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5764 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5765 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5766 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5767 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5768 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5769 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5770 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5771
5772 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5773
5774 pi->sclk_dpm_key_disabled = 0;
5775 pi->mclk_dpm_key_disabled = 0;
5776 pi->pcie_dpm_key_disabled = 0;
5777 pi->thermal_sclk_dpm_enabled = 0;
5778
5779 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5780 if ((rdev->pdev->device == 0x6658) &&
5781 (rdev->mc_fw->datasize == (BONAIRE_MC_UCODE_SIZE * 4))) {
5782 pi->mclk_dpm_key_disabled = 1;
5783 }
5784
5785 pi->caps_sclk_ds = true;
5786
5787 pi->mclk_strobe_mode_threshold = 40000;
5788 pi->mclk_stutter_mode_threshold = 40000;
5789 pi->mclk_edc_enable_threshold = 40000;
5790 pi->mclk_edc_wr_enable_threshold = 40000;
5791
5792 ci_initialize_powertune_defaults(rdev);
5793
5794 pi->caps_fps = false;
5795
5796 pi->caps_sclk_throttle_low_notification = false;
5797
5798 pi->caps_uvd_dpm = true;
5799 pi->caps_vce_dpm = true;
5800
5801 ci_get_leakage_voltages(rdev);
5802 ci_patch_dependency_tables_with_leakage(rdev);
5803 ci_set_private_data_variables_based_on_pptable(rdev);
5804
5805 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5806 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5807 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5808 ci_dpm_fini(rdev);
5809 return -ENOMEM;
5810 }
5811 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5812 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5813 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5814 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5815 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5816 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5817 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5818 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5819 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5820
5821 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5822 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5823 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5824
5825 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5826 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5827 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5828 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5829
5830 if (rdev->family == CHIP_HAWAII) {
5831 pi->thermal_temp_setting.temperature_low = 94500;
5832 pi->thermal_temp_setting.temperature_high = 95000;
5833 pi->thermal_temp_setting.temperature_shutdown = 104000;
5834 } else {
5835 pi->thermal_temp_setting.temperature_low = 99500;
5836 pi->thermal_temp_setting.temperature_high = 100000;
5837 pi->thermal_temp_setting.temperature_shutdown = 104000;
5838 }
5839
5840 pi->uvd_enabled = false;
5841
5842 dpm_table = &pi->smc_state_table;
5843
5844 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5845 if (gpio.valid) {
5846 dpm_table->VRHotGpio = gpio.shift;
5847 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5848 } else {
5849 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5850 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5851 }
5852
5853 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5854 if (gpio.valid) {
5855 dpm_table->AcDcGpio = gpio.shift;
5856 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5857 } else {
5858 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5859 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5860 }
5861
5862 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5863 if (gpio.valid) {
5864 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
5865
5866 switch (gpio.shift) {
5867 case 0:
5868 tmp &= ~GNB_SLOW_MODE_MASK;
5869 tmp |= GNB_SLOW_MODE(1);
5870 break;
5871 case 1:
5872 tmp &= ~GNB_SLOW_MODE_MASK;
5873 tmp |= GNB_SLOW_MODE(2);
5874 break;
5875 case 2:
5876 tmp |= GNB_SLOW;
5877 break;
5878 case 3:
5879 tmp |= FORCE_NB_PS1;
5880 break;
5881 case 4:
5882 tmp |= DPM_ENABLED;
5883 break;
5884 default:
5885 DRM_DEBUG("Invalid PCC GPIO: %u!\n", gpio.shift);
5886 break;
5887 }
5888 WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
5889 }
5890
5891 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5892 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5893 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5894 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5895 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5896 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5897 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5898
5899 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5900 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5901 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5902 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5903 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5904 else
5905 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5906 }
5907
5908 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5909 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5910 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5911 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5912 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5913 else
5914 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5915 }
5916
5917 pi->vddc_phase_shed_control = true;
5918
5919 #if defined(CONFIG_ACPI)
5920 pi->pcie_performance_request =
5921 radeon_acpi_is_pcie_performance_request_supported(rdev);
5922 #else
5923 pi->pcie_performance_request = false;
5924 #endif
5925
5926 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5927 &frev, &crev, &data_offset)) {
5928 pi->caps_sclk_ss_support = true;
5929 pi->caps_mclk_ss_support = true;
5930 pi->dynamic_ss = true;
5931 } else {
5932 pi->caps_sclk_ss_support = false;
5933 pi->caps_mclk_ss_support = false;
5934 pi->dynamic_ss = true;
5935 }
5936
5937 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5938 pi->thermal_protection = true;
5939 else
5940 pi->thermal_protection = false;
5941
5942 pi->caps_dynamic_ac_timing = true;
5943
5944 pi->uvd_power_gated = false;
5945
5946 /* make sure dc limits are valid */
5947 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5948 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5949 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5950 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5951
5952 pi->fan_ctrl_is_in_default_mode = true;
5953
5954 return 0;
5955 }
5956
ci_dpm_debugfs_print_current_performance_level(struct radeon_device * rdev,struct seq_file * m)5957 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5958 struct seq_file *m)
5959 {
5960 struct ci_power_info *pi = ci_get_pi(rdev);
5961 struct radeon_ps *rps = &pi->current_rps;
5962 u32 sclk = ci_get_average_sclk_freq(rdev);
5963 u32 mclk = ci_get_average_mclk_freq(rdev);
5964
5965 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
5966 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
5967 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5968 sclk, mclk);
5969 }
5970
ci_dpm_print_power_state(struct radeon_device * rdev,struct radeon_ps * rps)5971 void ci_dpm_print_power_state(struct radeon_device *rdev,
5972 struct radeon_ps *rps)
5973 {
5974 struct ci_ps *ps = ci_get_ps(rps);
5975 struct ci_pl *pl;
5976 int i;
5977
5978 r600_dpm_print_class_info(rps->class, rps->class2);
5979 r600_dpm_print_cap_info(rps->caps);
5980 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5981 for (i = 0; i < ps->performance_level_count; i++) {
5982 pl = &ps->performance_levels[i];
5983 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5984 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5985 }
5986 r600_dpm_print_ps_status(rdev, rps);
5987 }
5988
ci_dpm_get_current_sclk(struct radeon_device * rdev)5989 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev)
5990 {
5991 u32 sclk = ci_get_average_sclk_freq(rdev);
5992
5993 return sclk;
5994 }
5995
ci_dpm_get_current_mclk(struct radeon_device * rdev)5996 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev)
5997 {
5998 u32 mclk = ci_get_average_mclk_freq(rdev);
5999
6000 return mclk;
6001 }
6002
ci_dpm_get_sclk(struct radeon_device * rdev,bool low)6003 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
6004 {
6005 struct ci_power_info *pi = ci_get_pi(rdev);
6006 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6007
6008 if (low)
6009 return requested_state->performance_levels[0].sclk;
6010 else
6011 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
6012 }
6013
ci_dpm_get_mclk(struct radeon_device * rdev,bool low)6014 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
6015 {
6016 struct ci_power_info *pi = ci_get_pi(rdev);
6017 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6018
6019 if (low)
6020 return requested_state->performance_levels[0].mclk;
6021 else
6022 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
6023 }
6024