1 /* $OpenBSD: acpireg.h,v 1.60 2023/09/12 08:32:58 jmatthew Exp $ */ 2 /* 3 * Copyright (c) 2005 Thorsten Lockert <tholo@sigmasoft.com> 4 * Copyright (c) 2005 Marco Peereboom <marco@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DEV_ACPI_ACPIREG_H_ 20 #define _DEV_ACPI_ACPIREG_H_ 21 22 /* Root System Descriptor Pointer */ 23 struct acpi_rsdp1 { 24 uint8_t signature[8]; 25 #define RSDP_SIG "RSD PTR " 26 #define rsdp_signature rsdp1.signature 27 uint8_t checksum; /* make sum == 0 */ 28 #define rsdp_checksum rsdp1.checksum 29 uint8_t oemid[6]; 30 #define rsdp_oemid rsdp1.oemid 31 uint8_t revision; /* 0 for 1, 2 for 2 */ 32 #define rsdp_revision rsdp1.revision 33 uint32_t rsdt; /* physical */ 34 #define rsdp_rsdt rsdp1.rsdt 35 } __packed; 36 37 struct acpi_rsdp { 38 struct acpi_rsdp1 rsdp1; 39 /* 40 * The following values are only valid 41 * when rsdp_revision == 2 42 */ 43 uint32_t rsdp_length; /* length of rsdp */ 44 uint64_t rsdp_xsdt; /* physical */ 45 uint8_t rsdp_extchecksum; /* entire table */ 46 uint8_t rsdp_reserved[3]; /* must be zero */ 47 } __packed; 48 49 struct acpi_table_header { 50 uint8_t signature[4]; 51 #define hdr_signature hdr.signature 52 uint32_t length; 53 #define hdr_length hdr.length 54 uint8_t revision; 55 #define hdr_revision hdr.revision 56 uint8_t checksum; 57 #define hdr_checksum hdr.checksum 58 uint8_t oemid[6]; 59 #define hdr_oemid hdr.oemid 60 uint8_t oemtableid[8]; 61 #define hdr_oemtableid hdr.oemtableid 62 uint32_t oemrevision; 63 #define hdr_oemrevision hdr.oemrevision 64 uint8_t aslcompilerid[4]; 65 #define hdr_aslcompilerid hdr.aslcompilerid 66 uint32_t aslcompilerrevision; 67 #define hdr_aslcompilerrevision hdr.aslcompilerrevision 68 } __packed; 69 70 struct acpi_rsdt { 71 struct acpi_table_header hdr; 72 #define RSDT_SIG "RSDT" 73 uint32_t table_offsets[1]; 74 } __packed; 75 76 struct acpi_xsdt { 77 struct acpi_table_header hdr; 78 #define XSDT_SIG "XSDT" 79 uint64_t table_offsets[1]; 80 } __packed; 81 82 struct acpi_gas { 83 uint8_t address_space_id; 84 #define GAS_SYSTEM_MEMORY 0 85 #define GAS_SYSTEM_IOSPACE 1 86 #define GAS_PCI_CFG_SPACE 2 87 #define GAS_EMBEDDED 3 88 #define GAS_SMBUS 4 89 #define GAS_FUNCTIONAL_FIXED 127 90 uint8_t register_bit_width; 91 uint8_t register_bit_offset; 92 uint8_t access_size; 93 #define GAS_ACCESS_UNDEFINED 0 94 #define GAS_ACCESS_BYTE 1 95 #define GAS_ACCESS_WORD 2 96 #define GAS_ACCESS_DWORD 3 97 #define GAS_ACCESS_QWORD 4 98 uint64_t address; 99 } __packed; 100 101 struct acpi_fadt { 102 struct acpi_table_header hdr; 103 #define FADT_SIG "FACP" 104 uint32_t firmware_ctl; /* phys addr FACS */ 105 uint32_t dsdt; /* phys addr DSDT */ 106 uint8_t int_model; /* interrupt model (hdr_revision < 3) */ 107 #define FADT_INT_DUAL_PIC 0 108 #define FADT_INT_MULTI_APIC 1 109 uint8_t pm_profile; /* power mgmt profile */ 110 #define FADT_PM_UNSPEC 0 111 #define FADT_PM_DESKTOP 1 112 #define FADT_PM_MOBILE 2 113 #define FADT_PM_WORKSTATION 3 114 #define FADT_PM_ENT_SERVER 4 115 #define FADT_PM_SOHO_SERVER 5 116 #define FADT_PM_APPLIANCE 6 117 #define FADT_PM_PERF_SERVER 7 118 uint16_t sci_int; /* SCI interrupt */ 119 uint32_t smi_cmd; /* SMI command port */ 120 uint8_t acpi_enable; /* value to enable */ 121 uint8_t acpi_disable; /* value to disable */ 122 uint8_t s4bios_req; /* value for S4 */ 123 uint8_t pstate_cnt; /* value for performance (hdr_revision > 2) */ 124 uint32_t pm1a_evt_blk; /* power management 1a */ 125 uint32_t pm1b_evt_blk; /* power management 1b */ 126 uint32_t pm1a_cnt_blk; /* pm control 1a */ 127 uint32_t pm1b_cnt_blk; /* pm control 1b */ 128 uint32_t pm2_cnt_blk; /* pm control 2 */ 129 uint32_t pm_tmr_blk; 130 uint32_t gpe0_blk; 131 uint32_t gpe1_blk; 132 uint8_t pm1_evt_len; 133 uint8_t pm1_cnt_len; 134 uint8_t pm2_cnt_len; 135 uint8_t pm_tmr_len; 136 uint8_t gpe0_blk_len; 137 uint8_t gpe1_blk_len; 138 uint8_t gpe1_base; 139 uint8_t cst_cnt; /* (hdr_revision > 2) */ 140 uint16_t p_lvl2_lat; 141 uint16_t p_lvl3_lat; 142 uint16_t flush_size; 143 uint16_t flush_stride; 144 uint8_t duty_offset; 145 uint8_t duty_width; 146 uint8_t day_alrm; 147 uint8_t mon_alrm; 148 uint8_t century; 149 uint16_t iapc_boot_arch; /* (hdr_revision > 2) */ 150 #define FADT_LEGACY_DEVICES 0x0001 /* Legacy devices supported */ 151 #define FADT_i8042 0x0002 /* Keyboard controller present */ 152 #define FADT_NO_VGA 0x0004 /* Do not probe VGA */ 153 #define FADT_NO_MSI 0x0008 /* Do not enable MSI */ 154 uint8_t reserved1; 155 uint32_t flags; 156 #define FADT_WBINVD 0x00000001 157 #define FADT_WBINVD_FLUSH 0x00000002 158 #define FADT_PROC_C1 0x00000004 159 #define FADT_P_LVL2_UP 0x00000008 160 #define FADT_PWR_BUTTON 0x00000010 161 #define FADT_SLP_BUTTON 0x00000020 162 #define FADT_FIX_RTC 0x00000040 163 #define FADT_RTC_S4 0x00000080 164 #define FADT_TMR_VAL_EXT 0x00000100 165 #define FADT_DCK_CAP 0x00000200 166 #define FADT_RESET_REG_SUP 0x00000400 167 #define FADT_SEALED_CASE 0x00000800 168 #define FADT_HEADLESS 0x00001000 169 #define FADT_CPU_SW_SLP 0x00002000 170 #define FADT_PCI_EXP_WAK 0x00004000 171 #define FADT_USE_PLATFORM_CLOCK 0x00008000 172 #define FADT_S4_RTC_STS_VALID 0x00010000 173 #define FADT_REMOTE_POWER_ON_CAPABLE 0x00020000 174 #define FADT_FORCE_APIC_CLUSTER_MODEL 0x00040000 175 #define FADT_FORCE_APIC_PHYS_DEST_MODE 0x00080000 176 #define FADT_HW_REDUCED_ACPI 0x00100000 177 #define FADT_POWER_S0_IDLE_CAPABLE 0x00200000 178 /* 179 * Following values only exist when rev > 1 180 * If the extended addresses exists, they 181 * must be used in preference to the non- 182 * extended values above 183 */ 184 struct acpi_gas reset_reg; 185 uint8_t reset_value; 186 uint8_t reserved2a; 187 uint8_t reserved2b; 188 uint8_t fadt_minor; 189 uint64_t x_firmware_ctl; 190 uint64_t x_dsdt; 191 struct acpi_gas x_pm1a_evt_blk; 192 struct acpi_gas x_pm1b_evt_blk; 193 struct acpi_gas x_pm1a_cnt_blk; 194 struct acpi_gas x_pm1b_cnt_blk; 195 struct acpi_gas x_pm2_cnt_blk; 196 struct acpi_gas x_pm_tmr_blk; 197 struct acpi_gas x_gpe0_blk; 198 struct acpi_gas x_gpe1_blk; 199 struct acpi_gas sleep_control_reg; 200 struct acpi_gas sleep_status_reg; 201 } __packed; 202 203 struct acpi_dsdt { 204 struct acpi_table_header hdr; 205 #define DSDT_SIG "DSDT" 206 uint8_t aml[1]; 207 } __packed; 208 209 struct acpi_ssdt { 210 struct acpi_table_header hdr; 211 #define SSDT_SIG "SSDT" 212 uint8_t aml[1]; 213 } __packed; 214 215 /* 216 * Table deprecated by ACPI 2.0 217 */ 218 struct acpi_psdt { 219 struct acpi_table_header hdr; 220 #define PSDT_SIG "PSDT" 221 } __packed; 222 223 struct acpi_madt { 224 struct acpi_table_header hdr; 225 #define MADT_SIG "APIC" 226 uint32_t local_apic_address; 227 uint32_t flags; 228 #define ACPI_APIC_PCAT_COMPAT 0x00000001 229 } __packed; 230 231 struct acpi_madt_lapic { 232 uint8_t apic_type; 233 #define ACPI_MADT_LAPIC 0 234 uint8_t length; 235 uint8_t acpi_proc_id; 236 uint8_t apic_id; 237 uint32_t flags; 238 #define ACPI_PROC_ENABLE 0x00000001 239 } __packed; 240 241 struct acpi_madt_ioapic { 242 uint8_t apic_type; 243 #define ACPI_MADT_IOAPIC 1 244 uint8_t length; 245 uint8_t acpi_ioapic_id; 246 uint8_t reserved; 247 uint32_t address; 248 uint32_t global_int_base; 249 } __packed; 250 251 struct acpi_madt_override { 252 uint8_t apic_type; 253 #define ACPI_MADT_OVERRIDE 2 254 uint8_t length; 255 uint8_t bus; 256 #define ACPI_OVERRIDE_BUS_ISA 0 257 uint8_t source; 258 uint32_t global_int; 259 uint16_t flags; 260 #define ACPI_OVERRIDE_POLARITY_BITS 0x3 261 #define ACPI_OVERRIDE_POLARITY_BUS 0x0 262 #define ACPI_OVERRIDE_POLARITY_HIGH 0x1 263 #define ACPI_OVERRIDE_POLARITY_LOW 0x3 264 #define ACPI_OVERRIDE_TRIGGER_BITS 0xc 265 #define ACPI_OVERRIDE_TRIGGER_BUS 0x0 266 #define ACPI_OVERRIDE_TRIGGER_EDGE 0x4 267 #define ACPI_OVERRIDE_TRIGGER_LEVEL 0xc 268 } __packed; 269 270 struct acpi_madt_nmi { 271 uint8_t apic_type; 272 #define ACPI_MADT_NMI 3 273 uint8_t length; 274 uint16_t flags; /* Same flags as acpi_madt_override */ 275 uint32_t global_int; 276 } __packed; 277 278 struct acpi_madt_lapic_nmi { 279 uint8_t apic_type; 280 #define ACPI_MADT_LAPIC_NMI 4 281 uint8_t length; 282 uint8_t acpi_proc_id; 283 uint16_t flags; /* Same flags as acpi_madt_override */ 284 uint8_t local_apic_lint; 285 } __packed; 286 287 struct acpi_madt_lapic_override { 288 uint8_t apic_type; 289 #define ACPI_MADT_LAPIC_OVERRIDE 5 290 uint8_t length; 291 uint16_t reserved; 292 uint64_t lapic_address; 293 } __packed; 294 295 struct acpi_madt_io_sapic { 296 uint8_t apic_type; 297 #define ACPI_MADT_IO_SAPIC 6 298 uint8_t length; 299 uint8_t iosapic_id; 300 uint8_t reserved; 301 uint32_t global_int_base; 302 uint64_t iosapic_address; 303 } __packed; 304 305 struct acpi_madt_local_sapic { 306 uint8_t apic_type; 307 #define ACPI_MADT_LOCAL_SAPIC 7 308 uint8_t length; 309 uint8_t acpi_proc_id; 310 uint8_t local_sapic_id; 311 uint8_t local_sapic_eid; 312 uint8_t reserved[3]; 313 uint32_t flags; /* Same flags as acpi_madt_lapic */ 314 uint32_t acpi_proc_uid; 315 uint8_t acpi_proc_uid_string[1]; 316 } __packed; 317 318 struct acpi_madt_platform_int { 319 uint8_t apic_type; 320 #define ACPI_MADT_PLATFORM_INT 8 321 uint8_t length; 322 uint16_t flags; /* Same flags as acpi_madt_override */ 323 uint8_t int_type; 324 #define ACPI_MADT_PLATFORM_PMI 1 325 #define ACPI_MADT_PLATFORM_INIT 2 326 #define ACPI_MADT_PLATFORM_CORR_ERROR 3 327 uint8_t proc_id; 328 uint8_t proc_eid; 329 uint8_t io_sapic_vec; 330 uint32_t global_int; 331 uint32_t platform_int_flags; 332 #define ACPI_MADT_PLATFORM_CPEI 0x00000001 333 } __packed; 334 335 struct acpi_madt_x2apic { 336 uint8_t apic_type; 337 #define ACPI_MADT_X2APIC 9 338 uint8_t length; 339 uint8_t reserved[2]; 340 uint32_t apic_id; 341 uint32_t flags; /* Same flags as acpi_madt_lapic */ 342 uint32_t acpi_proc_uid; 343 } __packed; 344 345 struct acpi_madt_x2apic_nmi { 346 uint8_t apic_type; 347 #define ACPI_MADT_X2APIC_NMI 10 348 uint8_t length; 349 uint16_t flags; /* Same flags as acpi_madt_override */ 350 uint32_t apic_proc_uid; 351 uint8_t local_x2apic_lint; 352 uint8_t reserved[3]; 353 } __packed; 354 355 #define ACPI_MADT_OEM_RSVD 128 356 357 union acpi_madt_entry { 358 struct acpi_madt_lapic madt_lapic; 359 struct acpi_madt_ioapic madt_ioapic; 360 struct acpi_madt_override madt_override; 361 struct acpi_madt_nmi madt_nmi; 362 struct acpi_madt_lapic_nmi madt_lapic_nmi; 363 struct acpi_madt_lapic_override madt_lapic_override; 364 struct acpi_madt_io_sapic madt_io_sapic; 365 struct acpi_madt_local_sapic madt_local_sapic; 366 struct acpi_madt_platform_int madt_platform_int; 367 struct acpi_madt_x2apic madt_x2apic; 368 struct acpi_madt_x2apic_nmi madt_x2apic_nmi; 369 } __packed; 370 371 struct acpi_sbst { 372 struct acpi_table_header hdr; 373 #define SBST_SIG "SBST" 374 uint32_t warning_energy_level; 375 uint32_t low_energy_level; 376 uint32_t critical_energy_level; 377 } __packed; 378 379 struct acpi_ecdt { 380 struct acpi_table_header hdr; 381 #define ECDT_SIG "ECDT" 382 struct acpi_gas ec_control; 383 struct acpi_gas ec_data; 384 uint32_t uid; 385 uint8_t gpe_bit; 386 uint8_t ec_id[1]; 387 } __packed; 388 389 struct acpi_srat { 390 struct acpi_table_header hdr; 391 #define SRAT_SIG "SRAT" 392 uint32_t reserved1; 393 uint64_t reserved2; 394 } __packed; 395 396 struct acpi_slit { 397 struct acpi_table_header hdr; 398 #define SLIT_SIG "SLIT" 399 uint64_t number_of_localities; 400 } __packed; 401 402 struct acpi_hpet { 403 struct acpi_table_header hdr; 404 #define HPET_SIG "HPET" 405 uint32_t event_timer_block_id; 406 struct acpi_gas base_address; 407 uint8_t hpet_number; 408 uint16_t main_counter_min_clock_tick; 409 uint8_t page_protection; 410 } __packed; 411 412 struct acpi_mcfg { 413 struct acpi_table_header hdr; 414 #define MCFG_SIG "MCFG" 415 uint8_t reserved[8]; 416 } __packed; 417 418 struct acpi_mcfg_entry { 419 uint64_t base_address; 420 uint16_t segment; 421 uint8_t min_bus_number; 422 uint8_t max_bus_number; 423 uint32_t reserved1; 424 } __packed; 425 426 struct acpi_spcr { 427 struct acpi_table_header hdr; 428 #define SPCR_SIG "SPCR" 429 uint8_t interface_type; 430 #define SPCR_16550 0 431 #define SPCR_16450 1 432 #define SPCR_ARM_PL011 3 433 #define SPCR_ARM_SBSA 14 434 uint8_t reserved1[3]; 435 struct acpi_gas base_address; 436 uint8_t interrupt_type; 437 uint8_t irq; 438 uint32_t gsiv; 439 uint8_t baud_rate; 440 uint8_t parity; 441 uint8_t stop_bits; 442 uint8_t flow_control; 443 uint8_t terminal_type; 444 uint8_t reserved2; 445 uint16_t pci_device_id; 446 uint16_t pci_vendor_id; 447 uint8_t pci_bus; 448 uint8_t pci_device; 449 uint8_t pci_function; 450 uint32_t pci_flags; 451 uint8_t pci_segment; 452 uint32_t reserved3; 453 } __packed; 454 455 struct acpi_facs { 456 uint8_t signature[4]; 457 #define FACS_SIG "FACS" 458 uint32_t length; 459 uint32_t hardware_signature; 460 uint32_t wakeup_vector; 461 uint32_t global_lock; 462 #define FACS_LOCK_PENDING 0x00000001 463 #define FACS_LOCK_OWNED 0x00000002 464 uint32_t flags; 465 #define FACS_S4BIOS_F 0x00000001 /* S4BIOS_REQ supported */ 466 uint64_t x_wakeup_vector; 467 uint8_t version; 468 uint8_t reserved[31]; 469 } __packed; 470 471 struct acpi_tpm2 { 472 struct acpi_table_header hdr; 473 #define TPM2_SIG "TPM2" 474 uint32_t reserved; 475 uint64_t control_addr; 476 uint32_t start_method; 477 } __packed; 478 479 /* 480 * Intel ACPI DMA Remapping Entries 481 */ 482 struct acpidmar_devpath { 483 uint8_t device; 484 uint8_t function; 485 } __packed; 486 487 struct acpidmar_devscope { 488 uint8_t type; 489 #define DMAR_ENDPOINT 0x1 490 #define DMAR_BRIDGE 0x2 491 #define DMAR_IOAPIC 0x3 492 #define DMAR_HPET 0x4 493 uint8_t length; 494 uint16_t reserved; 495 uint8_t enumid; 496 uint8_t bus; 497 } __packed; 498 499 /* DMA Remapping Hardware Unit */ 500 struct acpidmar_drhd { 501 uint16_t type; 502 uint16_t length; 503 504 uint8_t flags; 505 uint8_t reserved; 506 uint16_t segment; 507 uint64_t address; 508 /* struct acpidmar_devscope[]; */ 509 } __packed; 510 511 /* Reserved Memory Region Reporting */ 512 struct acpidmar_rmrr { 513 uint16_t type; 514 uint16_t length; 515 516 uint16_t reserved; 517 uint16_t segment; 518 uint64_t base; 519 uint64_t limit; 520 /* struct acpidmar_devscope[]; */ 521 } __packed; 522 523 /* Root Port ATS Capability Reporting */ 524 struct acpidmar_atsr { 525 uint16_t type; 526 uint16_t length; 527 528 uint8_t flags; 529 uint8_t reserved; 530 uint16_t segment; 531 /* struct acpidmar_devscope[]; */ 532 } __packed; 533 534 union acpidmar_entry { 535 struct { 536 uint16_t type; 537 #define DMAR_DRHD 0x0 538 #define DMAR_RMRR 0x1 539 #define DMAR_ATSR 0x2 540 #define DMAR_RHSA 0x3 541 uint16_t length; 542 } __packed; 543 struct acpidmar_drhd drhd; 544 struct acpidmar_rmrr rmrr; 545 struct acpidmar_atsr atsr; 546 } __packed; 547 548 struct acpi_dmar { 549 struct acpi_table_header hdr; 550 #define DMAR_SIG "DMAR" 551 uint8_t haw; 552 uint8_t flags; 553 uint8_t reserved[10]; 554 /* struct acpidmar_entry[]; */ 555 } __packed; 556 557 /* 558 * AMD I/O Virtualization Remapping Entries 559 */ 560 union acpi_ivhd_entry { 561 uint8_t type; 562 #define IVHD_ALL 1 563 #define IVHD_SEL 2 564 #define IVHD_SOR 3 565 #define IVHD_EOR 4 566 #define IVHD_ALIAS_SEL 66 567 #define IVHD_ALIAS_SOR 67 568 #define IVHD_EXT_SEL 70 569 #define IVHD_EXT_SOR 71 570 #define IVHD_SPECIAL 72 571 struct { 572 uint8_t type; 573 uint16_t resvd; 574 uint8_t data; 575 } __packed all; 576 struct { 577 uint8_t type; 578 uint16_t devid; 579 uint8_t data; 580 } __packed sel; 581 struct { 582 uint8_t type; 583 uint16_t devid; 584 uint8_t data; 585 } __packed sor; 586 struct { 587 uint8_t type; 588 uint16_t devid; 589 uint8_t resvd; 590 } __packed eor; 591 struct { 592 uint8_t type; 593 uint16_t devid; 594 uint8_t data; 595 uint8_t resvd1; 596 uint16_t srcid; 597 uint8_t resvd2; 598 } __packed alias; 599 struct { 600 uint8_t type; 601 uint16_t devid; 602 uint8_t data; 603 uint32_t extdata; 604 #define IVHD_ATS_DIS (1L << 31) 605 } __packed ext; 606 struct { 607 uint8_t type; 608 uint16_t resvd; 609 uint8_t data; 610 uint8_t handle; 611 uint16_t devid; 612 uint8_t variety; 613 #define IVHD_IOAPIC 0x01 614 #define IVHD_HPET 0x02 615 } __packed special; 616 } __packed; 617 618 struct acpi_ivmd { 619 uint8_t type; 620 uint8_t flags; 621 #define IVMD_EXCLRANGE (1L << 3) 622 #define IVMD_IW (1L << 2) 623 #define IVMD_IR (1L << 1) 624 #define IVMD_UNITY (1L << 0) 625 uint16_t length; 626 uint16_t devid; 627 uint16_t auxdata; 628 uint8_t reserved[8]; 629 uint64_t base; 630 uint64_t limit; 631 } __packed; 632 633 struct acpi_ivhd { 634 uint8_t type; 635 uint8_t flags; 636 #define IVHD_PPRSUP (1L << 7) 637 #define IVHD_PREFSUP (1L << 6) 638 #define IVHD_COHERENT (1L << 5) 639 #define IVHD_IOTLB (1L << 4) 640 #define IVHD_ISOC (1L << 3) 641 #define IVHD_RESPASSPW (1L << 2) 642 #define IVHD_PASSPW (1L << 1) 643 #define IVHD_HTTUNEN (1L << 0) 644 uint16_t length; 645 uint16_t devid; 646 uint16_t cap; 647 uint64_t address; 648 uint16_t segment; 649 uint16_t info; 650 #define IVHD_UNITID_SHIFT 8 651 #define IVHD_UNITID_MASK 0x1F 652 #define IVHD_MSINUM_SHIFT 0 653 #define IVHD_MSINUM_MASK 0x1F 654 uint32_t feature; 655 } __packed; 656 657 struct acpi_ivhd_ext { 658 uint8_t type; 659 uint8_t flags; 660 uint16_t length; 661 uint16_t devid; 662 uint16_t cap; 663 uint64_t address; 664 uint16_t segment; 665 uint16_t info; 666 uint32_t attrib; 667 uint64_t efr; 668 uint8_t reserved[8]; 669 } __packed; 670 671 union acpi_ivrs_entry { 672 struct { 673 uint8_t type; 674 #define IVRS_IVHD 0x10 675 #define IVRS_IVHD_EXT 0x11 676 #define IVRS_IVMD_ALL 0x20 677 #define IVRS_IVMD_SPECIFIED 0x21 678 #define IVRS_IVMD_RANGE 0x22 679 uint8_t flags; 680 uint16_t length; 681 } __packed; 682 struct acpi_ivhd ivhd; 683 struct acpi_ivhd_ext ivhd_ext; 684 struct acpi_ivmd ivmd; 685 } __packed; 686 687 struct acpi_ivrs { 688 struct acpi_table_header hdr; 689 #define IVRS_SIG "IVRS" 690 uint32_t ivinfo; 691 #define IVRS_ATSRNG (1L << 22) 692 #define IVRS_VASIZE_SHIFT 15 693 #define IVRS_VASIZE_MASK 0x7F 694 #define IVRS_PASIZE_SHIFT 8 695 #define IVRS_PASIZE_MASK 0x7F 696 uint8_t reserved[8]; 697 } __packed; 698 699 struct acpi_iort { 700 struct acpi_table_header hdr; 701 #define IORT_SIG "IORT" 702 uint32_t number_of_nodes; 703 uint32_t offset; 704 uint32_t reserved; 705 } __packed; 706 707 struct acpi_iort_node { 708 uint8_t type; 709 #define ACPI_IORT_ITS 0 710 #define ACPI_IORT_NAMED_COMPONENT 1 711 #define ACPI_IORT_ROOT_COMPLEX 2 712 #define ACPI_IORT_SMMU 3 713 #define ACPI_IORT_SMMU_V3 4 714 uint16_t length; 715 uint8_t revision; 716 uint32_t reserved1; 717 uint32_t number_of_mappings; 718 uint32_t mapping_offset; 719 } __packed; 720 721 struct acpi_iort_its_node { 722 uint32_t number_of_itss; 723 uint32_t its_ids[]; 724 } __packed; 725 726 struct acpi_iort_nc_node { 727 uint32_t node_flags; 728 uint64_t memory_access_properties; 729 uint8_t device_memory_address_size_limit; 730 char device_object_name[]; 731 } __packed; 732 733 struct acpi_iort_rc_node { 734 uint64_t memory_access_properties; 735 uint32_t ats_attributes; 736 uint32_t segment; 737 uint8_t memory_address_size_limit; 738 uint8_t reserved2[3]; 739 } __packed; 740 741 struct acpi_iort_smmu_node { 742 uint64_t base_address; 743 uint64_t span; 744 uint32_t model; 745 #define ACPI_IORT_SMMU_V1 0 746 #define ACPI_IORT_SMMU_V2 1 747 #define ACPI_IORT_SMMU_CORELINK_MMU400 2 748 #define ACPI_IORT_SMMU_CORELINK_MMU500 3 749 #define ACPI_IORT_SMMU_CORELINK_MMU401 4 750 #define ACPI_IORT_SMMU_CAVIUM_THUNDERX 5 751 uint32_t flags; 752 #define ACPI_IORT_SMMU_DVM 0x00000001 753 #define ACPI_IORT_SMMU_COHERENT 0x00000002 754 uint32_t global_interrupt_offset; 755 uint32_t number_of_context_interrupts; 756 uint32_t context_interrupt_offset; 757 uint32_t number_of_pmu_interrupts; 758 uint32_t pmu_interrupt_offset; 759 } __packed; 760 761 struct acpi_iort_smmu_global_interrupt { 762 uint32_t nsgirpt_gsiv; 763 uint32_t nsgirpt_flags; 764 #define ACPI_IORT_SMMU_INTR_EDGE (1 << 0) 765 uint32_t nscfgirpt_gsiv; 766 uint32_t nscfgirpt_flags; 767 } __packed; 768 769 struct acpi_iort_smmu_context_interrupt { 770 uint32_t gsiv; 771 uint32_t flags; 772 } __packed; 773 774 struct acpi_iort_smmu_pmu_interrupt { 775 uint32_t gsiv; 776 uint32_t flags; 777 } __packed; 778 779 struct acpi_iort_mapping { 780 uint32_t input_base; 781 uint32_t number_of_ids; 782 uint32_t output_base; 783 uint32_t output_reference; 784 uint32_t flags; 785 #define ACPI_IORT_MAPPING_SINGLE 0x00000001 786 } __packed; 787 788 #define ACPI_FREQUENCY 3579545 /* Per ACPI spec */ 789 790 /* 791 * PCI Configuration space 792 */ 793 #define ACPI_ADR_PCIDEV(addr) (uint16_t)(addr >> 16) 794 #define ACPI_ADR_PCIFUN(addr) (uint16_t)(addr & 0xFFFF) 795 796 #define ACPI_PCI_SEG(addr) (uint16_t)((addr) >> 48) 797 #define ACPI_PCI_BUS(addr) (uint8_t)((addr) >> 40) 798 #define ACPI_PCI_DEV(addr) (uint8_t)((addr) >> 32) 799 #define ACPI_PCI_FN(addr) (uint16_t)((addr) >> 16) 800 #define ACPI_PCI_REG(addr) (uint16_t)(addr) 801 802 /* 803 * PM1 Status Registers Fixed Hardware Feature Status Bits 804 */ 805 #define ACPI_PM1_STATUS 0x00 806 #define ACPI_PM1_TMR_STS 0x0001 807 #define ACPI_PM1_BM_STS 0x0010 808 #define ACPI_PM1_GBL_STS 0x0020 809 #define ACPI_PM1_PWRBTN_STS 0x0100 810 #define ACPI_PM1_SLPBTN_STS 0x0200 811 #define ACPI_PM1_RTC_STS 0x0400 812 #define ACPI_PM1_PCIEXP_WAKE_STS 0x4000 813 #define ACPI_PM1_WAK_STS 0x8000 814 815 #define ACPI_PM1_ALL_STS (ACPI_PM1_TMR_STS | ACPI_PM1_BM_STS | \ 816 ACPI_PM1_GBL_STS | ACPI_PM1_PWRBTN_STS | \ 817 ACPI_PM1_SLPBTN_STS | ACPI_PM1_RTC_STS | \ 818 ACPI_PM1_PCIEXP_WAKE_STS | ACPI_PM1_WAK_STS ) 819 820 /* 821 * PM1 Enable Registers 822 */ 823 #define ACPI_PM1_ENABLE 0x02 824 #define ACPI_PM1_TMR_EN 0x0001 825 #define ACPI_PM1_GBL_EN 0x0020 826 #define ACPI_PM1_PWRBTN_EN 0x0100 827 #define ACPI_PM1_SLPBTN_EN 0x0200 828 #define ACPI_PM1_RTC_EN 0x0400 829 #define ACPI_PM1_PCIEXP_WAKE_DIS 0x4000 830 831 /* 832 * PM1 Control Registers 833 */ 834 #define ACPI_PM1_CONTROL 0x00 835 #define ACPI_PM1_SCI_EN 0x0001 836 #define ACPI_PM1_BM_RLD 0x0002 837 #define ACPI_PM1_GBL_RLS 0x0004 838 #define ACPI_PM1_SLP_TYPX(x) ((x) << 10) 839 #define ACPI_PM1_SLP_TYPX_MASK 0x1c00 840 #define ACPI_PM1_SLP_EN 0x2000 841 842 /* 843 * PM2 Control Registers 844 */ 845 #define ACPI_PM2_CONTROL 0x06 846 #define ACPI_PM2_ARB_DIS 0x0001 847 848 /* 849 * Operation Region Address Space Identifiers 850 */ 851 #define ACPI_OPREG_SYSMEM 0 /* SystemMemory */ 852 #define ACPI_OPREG_SYSIO 1 /* SystemIO */ 853 #define ACPI_OPREG_PCICFG 2 /* PCI_Config */ 854 #define ACPI_OPREG_EC 3 /* EmbeddedControl */ 855 #define ACPI_OPREG_SMBUS 4 /* SMBus */ 856 #define ACPI_OPREG_CMOS 5 /* CMOS */ 857 #define ACPI_OPREG_PCIBAR 6 /* PCIBARTarget */ 858 #define ACPI_OPREG_IPMI 7 /* IPMI */ 859 #define ACPI_OPREG_GPIO 8 /* GeneralPurposeIO */ 860 #define ACPI_OPREG_GSB 9 /* GenericSerialBus */ 861 862 /* 863 * Sleeping States 864 */ 865 #define ACPI_STATE_S0 0 866 #define ACPI_STATE_S1 1 867 #define ACPI_STATE_S2 2 868 #define ACPI_STATE_S3 3 869 #define ACPI_STATE_S4 4 870 #define ACPI_STATE_S5 5 871 872 /* 873 * Device Power States 874 */ 875 #define ACPI_STATE_D0 0 876 #define ACPI_STATE_D1 1 877 #define ACPI_STATE_D2 2 878 #define ACPI_STATE_D3 3 879 880 /* 881 * ACPI Device IDs 882 */ 883 #define ACPI_DEV_TIM "PNP0100" /* System timer */ 884 #define ACPI_DEV_ACPI "PNP0C08" /* ACPI device */ 885 #define ACPI_DEV_PCIB "PNP0A03" /* PCI bus */ 886 #define ACPI_DEV_GISAB "PNP0A05" /* Generic ISA Bus */ 887 #define ACPI_DEV_EIOB "PNP0A06" /* Extended I/O Bus */ 888 #define ACPI_DEV_PCIEB "PNP0A08" /* PCIe bus */ 889 #define ACPI_DEV_MR "PNP0C02" /* Motherboard resources */ 890 #define ACPI_DEV_NPROC "PNP0C04" /* Numeric data processor */ 891 #define ACPI_DEV_CS "PNP0C08" /* ACPI-Compliant System */ 892 #define ACPI_DEV_ECD "PNP0C09" /* Embedded Controller Device */ 893 #define ACPI_DEV_CMB "PNP0C0A" /* Control Method Battery */ 894 #define ACPI_DEV_FAN "PNP0C0B" /* Fan Device */ 895 #define ACPI_DEV_PBD "PNP0C0C" /* Power Button Device */ 896 #define ACPI_DEV_LD "PNP0C0D" /* Lid Device */ 897 #define ACPI_DEV_SBD "PNP0C0E" /* Sleep Button Device */ 898 #define ACPI_DEV_PILD "PNP0C0F" /* PCI Interrupt Link Device */ 899 #define ACPI_DEV_MEMD "PNP0C80" /* Memory Device */ 900 #define ACPI_DEV_MOUSE "PNP0F13" /* PS/2 Mouse */ 901 #define ACPI_DEV_SHC "ACPI0001" /* SMBus 1.0 Host Controller */ 902 #define ACPI_DEV_SBS "ACPI0002" /* Smart Battery Subsystem */ 903 #define ACPI_DEV_AC "ACPI0003" /* AC Device */ 904 #define ACPI_DEV_MD "ACPI0004" /* Module Device */ 905 #define ACPI_DEV_SMBUS "ACPI0005" /* SMBus 2.0 Host Controller */ 906 #define ACPI_DEV_GBD "ACPI0006" /* GPE Block Device */ 907 #define ACPI_DEV_PD "ACPI0007" /* Processor Device */ 908 #define ACPI_DEV_ALSD "ACPI0008" /* Ambient Light Sensor Device */ 909 #define ACPI_DEV_IOXA "ACPI0009" /* IO x APIC Device */ 910 #define ACPI_DEV_IOA "ACPI000A" /* IO APIC Device */ 911 #define ACPI_DEV_IOSA "ACPI000B" /* IO SAPIC Device */ 912 #define ACPI_DEV_THZ "THERMALZONE" /* Thermal Zone */ 913 #define ACPI_DEV_FFB "FIXEDBUTTON" /* Fixed Feature Button */ 914 #define ACPI_DEV_IPMI "IPI0001" /* IPMI */ 915 916 #endif /* !_DEV_ACPI_ACPIREG_H_ */ 917