1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org>
5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org>
6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org>
7 * All rights reserved.
8 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Driver for the AMD CPU on-die thermal sensors.
34 * Initially based on the k8temp Linux driver.
35 */
36
37 #include <sys/param.h>
38 #include <sys/bus.h>
39 #include <sys/conf.h>
40 #include <sys/kernel.h>
41 #include <sys/lock.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/sysctl.h>
45 #include <sys/systm.h>
46
47 #include <machine/cpufunc.h>
48 #include <machine/md_var.h>
49 #include <machine/specialreg.h>
50
51 #include <dev/pci/pcivar.h>
52 #include <x86/pci_cfgreg.h>
53
54 #include <dev/amdsmn/amdsmn.h>
55
56 typedef enum {
57 CORE0_SENSOR0,
58 CORE0_SENSOR1,
59 CORE1_SENSOR0,
60 CORE1_SENSOR1,
61 CORE0,
62 CORE1,
63 CCD1,
64 CCD_BASE = CCD1,
65 CCD2,
66 CCD3,
67 CCD4,
68 CCD5,
69 CCD6,
70 CCD7,
71 CCD8,
72 CCD9,
73 CCD10,
74 CCD11,
75 CCD12,
76 CCD_MAX = CCD12,
77 NUM_CCDS = CCD_MAX - CCD_BASE + 1,
78 } amdsensor_t;
79
80 struct amdtemp_softc {
81 int sc_ncores;
82 int sc_ntemps;
83 int sc_flags;
84 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */
85 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */
86 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */
87 int32_t sc_offset;
88 int32_t sc_temp_base;
89 int32_t (*sc_gettemp)(device_t, amdsensor_t);
90 struct sysctl_oid *sc_sysctl_cpu[MAXCPU];
91 struct intr_config_hook sc_ich;
92 device_t sc_smn;
93 struct mtx sc_lock;
94 };
95
96 /*
97 * N.B. The numbers in macro names below are significant and represent CPU
98 * family and model numbers. Do not make up fictitious family or model numbers
99 * when adding support for new devices.
100 */
101 #define VENDORID_AMD 0x1022
102 #define DEVICEID_AMD_MISC0F 0x1103
103 #define DEVICEID_AMD_MISC10 0x1203
104 #define DEVICEID_AMD_MISC11 0x1303
105 #define DEVICEID_AMD_MISC14 0x1703
106 #define DEVICEID_AMD_MISC15 0x1603
107 #define DEVICEID_AMD_MISC15_M10H 0x1403
108 #define DEVICEID_AMD_MISC15_M30H 0x141d
109 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576
110 #define DEVICEID_AMD_MISC16 0x1533
111 #define DEVICEID_AMD_MISC16_M30H 0x1583
112 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450
113 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0
114 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */
115 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630
116 #define DEVICEID_AMD_HOSTB19H_M10H_ROOT 0x14a4
117 #define DEVICEID_AMD_HOSTB19H_M60H_ROOT 0x14d8
118
119 static const struct amdtemp_product {
120 uint16_t amdtemp_vendorid;
121 uint16_t amdtemp_deviceid;
122 /*
123 * 0xFC register is only valid on the D18F3 PCI device; SMN temp
124 * drivers do not attach to that device.
125 */
126 bool amdtemp_has_cpuid;
127 } amdtemp_products[] = {
128 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true },
129 { VENDORID_AMD, DEVICEID_AMD_MISC10, true },
130 { VENDORID_AMD, DEVICEID_AMD_MISC11, true },
131 { VENDORID_AMD, DEVICEID_AMD_MISC14, true },
132 { VENDORID_AMD, DEVICEID_AMD_MISC15, true },
133 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true },
134 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true },
135 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false },
136 { VENDORID_AMD, DEVICEID_AMD_MISC16, true },
137 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true },
138 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false },
139 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false },
140 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false },
141 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false },
142 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M10H_ROOT, false },
143 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M60H_ROOT, false },
144 };
145
146 /*
147 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h.
148 */
149 #define AMDTEMP_REPTMP_CTRL 0xa4
150
151 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff
152 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21
153 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3
154 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16
155
156 /*
157 * Reported Temperature, Family 15h, M60+
158 *
159 * Same register bit definitions as other Family 15h CPUs, but access is
160 * indirect via SMN, like Family 17h.
161 */
162 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4
163
164 /*
165 * Reported Temperature, Family 17h
166 *
167 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
168 * provide the current temp. bit 19, when clear, means the temp is reported in
169 * a range 0.."225C" (probable typo for 255C), and when set changes the range
170 * to -49..206C.
171 */
172 #define AMDTEMP_17H_CUR_TMP 0x59800
173 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19)
174 /*
175 * Bits 16-17, when set, mean that CUR_TMP is read-write. When it is, the
176 * 49 degree offset should apply as well. This was revealed in a Linux
177 * patch from an AMD employee.
178 */
179 #define AMDTEMP_17H_CUR_TMP_TJ_SEL ((1u << 17) | (1u << 16))
180 /*
181 * The following register set was discovered experimentally by Ondrej Čerman
182 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than
183 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
184 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it.
185 */
186 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954
187 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11)
188
189 #define AMDTEMP_ZEN4_10H_CCD_TMP_BASE 0x59b00
190 #define AMDTEMP_ZEN4_CCD_TMP_BASE 0x59b08
191
192 /*
193 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius).
194 */
195 #define AMDTEMP_CURTMP_RANGE_ADJUST 490
196
197 /*
198 * Thermaltrip Status Register (Family 0Fh only)
199 */
200 #define AMDTEMP_THERMTP_STAT 0xe4
201 #define AMDTEMP_TTSR_SELCORE 0x04
202 #define AMDTEMP_TTSR_SELSENSOR 0x40
203
204 /*
205 * DRAM Configuration High Register
206 */
207 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */
208 #define AMDTEMP_DRAM_MODE_DDR3 0x0100
209
210 /*
211 * CPU Family/Model Register
212 */
213 #define AMDTEMP_CPUID 0xfc
214
215 /*
216 * Device methods.
217 */
218 static void amdtemp_identify(driver_t *driver, device_t parent);
219 static int amdtemp_probe(device_t dev);
220 static int amdtemp_attach(device_t dev);
221 static void amdtemp_intrhook(void *arg);
222 static int amdtemp_detach(device_t dev);
223 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor);
224 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor);
225 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor);
226 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor);
227 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model);
228 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model);
229 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS);
230
231 static device_method_t amdtemp_methods[] = {
232 /* Device interface */
233 DEVMETHOD(device_identify, amdtemp_identify),
234 DEVMETHOD(device_probe, amdtemp_probe),
235 DEVMETHOD(device_attach, amdtemp_attach),
236 DEVMETHOD(device_detach, amdtemp_detach),
237
238 DEVMETHOD_END
239 };
240
241 static driver_t amdtemp_driver = {
242 "amdtemp",
243 amdtemp_methods,
244 sizeof(struct amdtemp_softc),
245 };
246
247 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, NULL, NULL);
248 MODULE_VERSION(amdtemp, 1);
249 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1);
250 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products,
251 nitems(amdtemp_products));
252
253 static bool
amdtemp_match(device_t dev,const struct amdtemp_product ** product_out)254 amdtemp_match(device_t dev, const struct amdtemp_product **product_out)
255 {
256 int i;
257 uint16_t vendor, devid;
258
259 vendor = pci_get_vendor(dev);
260 devid = pci_get_device(dev);
261
262 for (i = 0; i < nitems(amdtemp_products); i++) {
263 if (vendor == amdtemp_products[i].amdtemp_vendorid &&
264 devid == amdtemp_products[i].amdtemp_deviceid) {
265 if (product_out != NULL)
266 *product_out = &amdtemp_products[i];
267 return (true);
268 }
269 }
270 return (false);
271 }
272
273 static void
amdtemp_identify(driver_t * driver,device_t parent)274 amdtemp_identify(driver_t *driver, device_t parent)
275 {
276 device_t child;
277
278 /* Make sure we're not being doubly invoked. */
279 if (device_find_child(parent, "amdtemp", -1) != NULL)
280 return;
281
282 if (amdtemp_match(parent, NULL)) {
283 child = device_add_child(parent, "amdtemp", -1);
284 if (child == NULL)
285 device_printf(parent, "add amdtemp child failed\n");
286 }
287 }
288
289 static int
amdtemp_probe(device_t dev)290 amdtemp_probe(device_t dev)
291 {
292 uint32_t family, model;
293
294 if (resource_disabled("amdtemp", 0))
295 return (ENXIO);
296 if (!amdtemp_match(device_get_parent(dev), NULL))
297 return (ENXIO);
298
299 family = CPUID_TO_FAMILY(cpu_id);
300 model = CPUID_TO_MODEL(cpu_id);
301
302 switch (family) {
303 case 0x0f:
304 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) ||
305 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1))
306 return (ENXIO);
307 break;
308 case 0x10:
309 case 0x11:
310 case 0x12:
311 case 0x14:
312 case 0x15:
313 case 0x16:
314 case 0x17:
315 case 0x19:
316 break;
317 default:
318 return (ENXIO);
319 }
320 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors");
321
322 return (BUS_PROBE_GENERIC);
323 }
324
325 static int
amdtemp_attach(device_t dev)326 amdtemp_attach(device_t dev)
327 {
328 char tn[32];
329 u_int regs[4];
330 const struct amdtemp_product *product;
331 struct amdtemp_softc *sc;
332 struct sysctl_ctx_list *sysctlctx;
333 struct sysctl_oid *sysctlnode;
334 uint32_t cpuid, family, model;
335 u_int bid;
336 int erratum319, unit;
337 bool needsmn;
338
339 sc = device_get_softc(dev);
340 erratum319 = 0;
341 needsmn = false;
342
343 if (!amdtemp_match(device_get_parent(dev), &product))
344 return (ENXIO);
345
346 cpuid = cpu_id;
347 family = CPUID_TO_FAMILY(cpuid);
348 model = CPUID_TO_MODEL(cpuid);
349
350 /*
351 * This checks for the byzantine condition of running a heterogenous
352 * revision multi-socket system where the attach thread is potentially
353 * probing a remote socket's PCI device.
354 *
355 * Currently, such scenarios are unsupported on models using the SMN
356 * (because on those models, amdtemp(4) attaches to a different PCI
357 * device than the one that contains AMDTEMP_CPUID).
358 *
359 * The ancient 0x0F family of devices only supports this register from
360 * models 40h+.
361 */
362 if (product->amdtemp_has_cpuid && (family > 0x0f ||
363 (family == 0x0f && model >= 0x40))) {
364 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID,
365 4);
366 family = CPUID_TO_FAMILY(cpuid);
367 model = CPUID_TO_MODEL(cpuid);
368 }
369
370 switch (family) {
371 case 0x0f:
372 /*
373 * Thermaltrip Status Register
374 *
375 * - ThermSenseCoreSel
376 *
377 * Revision F & G: 0 - Core1, 1 - Core0
378 * Other: 0 - Core0, 1 - Core1
379 *
380 * - CurTmp
381 *
382 * Revision G: bits 23-14
383 * Other: bits 23-16
384 *
385 * XXX According to the BKDG, CurTmp, ThermSenseSel and
386 * ThermSenseCoreSel bits were introduced in Revision F
387 * but CurTmp seems working fine as early as Revision C.
388 * However, it is not clear whether ThermSenseSel and/or
389 * ThermSenseCoreSel work in undocumented cases as well.
390 * In fact, the Linux driver suggests it may not work but
391 * we just assume it does until we find otherwise.
392 *
393 * XXX According to Linux, CurTmp starts at -28C on
394 * Socket AM2 Revision G processors, which is not
395 * documented anywhere.
396 */
397 if (model >= 0x40)
398 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP;
399 if (model >= 0x60 && model != 0xc1) {
400 do_cpuid(0x80000001, regs);
401 bid = (regs[1] >> 9) & 0x1f;
402 switch (model) {
403 case 0x68: /* Socket S1g1 */
404 case 0x6c:
405 case 0x7c:
406 break;
407 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */
408 if (bid != 0x0b && bid != 0x0c)
409 sc->sc_flags |=
410 AMDTEMP_FLAG_ALT_OFFSET;
411 break;
412 case 0x6f: /* Socket AM2 and ASB1 (1 core) */
413 case 0x7f:
414 if (bid != 0x07 && bid != 0x09 &&
415 bid != 0x0c)
416 sc->sc_flags |=
417 AMDTEMP_FLAG_ALT_OFFSET;
418 break;
419 default:
420 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET;
421 }
422 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT;
423 }
424
425 /*
426 * There are two sensors per core.
427 */
428 sc->sc_ntemps = 2;
429
430 sc->sc_gettemp = amdtemp_gettemp0f;
431 break;
432 case 0x10:
433 /*
434 * Erratum 319 Inaccurate Temperature Measurement
435 *
436 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
437 */
438 do_cpuid(0x80000001, regs);
439 switch ((regs[1] >> 28) & 0xf) {
440 case 0: /* Socket F */
441 erratum319 = 1;
442 break;
443 case 1: /* Socket AM2+ or AM3 */
444 if ((pci_cfgregread(pci_get_domain(dev),
445 pci_get_bus(dev), pci_get_slot(dev), 2,
446 AMDTEMP_DRAM_CONF_HIGH, 2) &
447 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 ||
448 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3))
449 break;
450 /* XXX 00100F42h (RB-C2) exists in both formats. */
451 erratum319 = 1;
452 break;
453 }
454 /* FALLTHROUGH */
455 case 0x11:
456 case 0x12:
457 case 0x14:
458 case 0x15:
459 case 0x16:
460 sc->sc_ntemps = 1;
461 /*
462 * Some later (60h+) models of family 15h use a similar SMN
463 * network as family 17h. (However, the register index differs
464 * from 17h and the decoding matches other 10h-15h models,
465 * which differ from 17h.)
466 */
467 if (family == 0x15 && model >= 0x60) {
468 sc->sc_gettemp = amdtemp_gettemp15hm60h;
469 needsmn = true;
470 } else
471 sc->sc_gettemp = amdtemp_gettemp;
472 break;
473 case 0x17:
474 case 0x19:
475 sc->sc_ntemps = 1;
476 sc->sc_gettemp = amdtemp_gettemp17h;
477 needsmn = true;
478 break;
479 default:
480 device_printf(dev, "Bogus family 0x%x\n", family);
481 return (ENXIO);
482 }
483
484 if (needsmn) {
485 sc->sc_smn = device_find_child(
486 device_get_parent(dev), "amdsmn", -1);
487 if (sc->sc_smn == NULL) {
488 if (bootverbose)
489 device_printf(dev, "No SMN device found\n");
490 return (ENXIO);
491 }
492 }
493
494 /* Find number of cores per package. */
495 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ?
496 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1;
497 if (sc->sc_ncores > MAXCPU)
498 return (ENXIO);
499
500 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF);
501 if (erratum319)
502 device_printf(dev,
503 "Erratum 319: temperature measurement may be inaccurate\n");
504 if (bootverbose)
505 device_printf(dev, "Found %d cores and %d sensors.\n",
506 sc->sc_ncores,
507 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1);
508
509 /*
510 * dev.amdtemp.N tree.
511 */
512 unit = device_get_unit(dev);
513 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit);
514 TUNABLE_INT_FETCH(tn, &sc->sc_offset);
515
516 sysctlctx = device_get_sysctl_ctx(dev);
517 SYSCTL_ADD_INT(sysctlctx,
518 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
519 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0,
520 "Temperature sensor offset");
521 sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
522 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
523 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0");
524
525 SYSCTL_ADD_PROC(sysctlctx,
526 SYSCTL_CHILDREN(sysctlnode),
527 OID_AUTO, "sensor0",
528 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
529 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK",
530 "Core 0 / Sensor 0 temperature");
531
532 sc->sc_temp_base = AMDTEMP_17H_CCD_TMP_BASE;
533
534 if (family == 0x17)
535 amdtemp_probe_ccd_sensors17h(dev, model);
536 else if (family == 0x19)
537 amdtemp_probe_ccd_sensors19h(dev, model);
538 else if (sc->sc_ntemps > 1) {
539 SYSCTL_ADD_PROC(sysctlctx,
540 SYSCTL_CHILDREN(sysctlnode),
541 OID_AUTO, "sensor1",
542 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
543 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK",
544 "Core 0 / Sensor 1 temperature");
545
546 if (sc->sc_ncores > 1) {
547 sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
548 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
549 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE,
550 0, "Core 1");
551
552 SYSCTL_ADD_PROC(sysctlctx,
553 SYSCTL_CHILDREN(sysctlnode),
554 OID_AUTO, "sensor0",
555 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
556 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK",
557 "Core 1 / Sensor 0 temperature");
558
559 SYSCTL_ADD_PROC(sysctlctx,
560 SYSCTL_CHILDREN(sysctlnode),
561 OID_AUTO, "sensor1",
562 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
563 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK",
564 "Core 1 / Sensor 1 temperature");
565 }
566 }
567
568 /*
569 * Try to create dev.cpu sysctl entries and setup intrhook function.
570 * This is needed because the cpu driver may be loaded late on boot,
571 * after us.
572 */
573 amdtemp_intrhook(dev);
574 sc->sc_ich.ich_func = amdtemp_intrhook;
575 sc->sc_ich.ich_arg = dev;
576 if (config_intrhook_establish(&sc->sc_ich) != 0) {
577 device_printf(dev, "config_intrhook_establish failed!\n");
578 return (ENXIO);
579 }
580
581 return (0);
582 }
583
584 void
amdtemp_intrhook(void * arg)585 amdtemp_intrhook(void *arg)
586 {
587 struct amdtemp_softc *sc;
588 struct sysctl_ctx_list *sysctlctx;
589 device_t dev = (device_t)arg;
590 device_t acpi, cpu, nexus;
591 amdsensor_t sensor;
592 int i;
593
594 sc = device_get_softc(dev);
595
596 /*
597 * dev.cpu.N.temperature.
598 */
599 nexus = device_find_child(root_bus, "nexus", 0);
600 acpi = device_find_child(nexus, "acpi", 0);
601
602 for (i = 0; i < sc->sc_ncores; i++) {
603 if (sc->sc_sysctl_cpu[i] != NULL)
604 continue;
605 cpu = device_find_child(acpi, "cpu",
606 device_get_unit(dev) * sc->sc_ncores + i);
607 if (cpu != NULL) {
608 sysctlctx = device_get_sysctl_ctx(cpu);
609
610 sensor = sc->sc_ntemps > 1 ?
611 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0;
612 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx,
613 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)),
614 OID_AUTO, "temperature",
615 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
616 dev, sensor, amdtemp_sysctl, "IK",
617 "Current temparature");
618 }
619 }
620 if (sc->sc_ich.ich_arg != NULL)
621 config_intrhook_disestablish(&sc->sc_ich);
622 }
623
624 int
amdtemp_detach(device_t dev)625 amdtemp_detach(device_t dev)
626 {
627 struct amdtemp_softc *sc = device_get_softc(dev);
628 int i;
629
630 for (i = 0; i < sc->sc_ncores; i++)
631 if (sc->sc_sysctl_cpu[i] != NULL)
632 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0);
633
634 /* NewBus removes the dev.amdtemp.N tree by itself. */
635
636 mtx_destroy(&sc->sc_lock);
637 return (0);
638 }
639
640 static int
amdtemp_sysctl(SYSCTL_HANDLER_ARGS)641 amdtemp_sysctl(SYSCTL_HANDLER_ARGS)
642 {
643 device_t dev = (device_t)arg1;
644 struct amdtemp_softc *sc = device_get_softc(dev);
645 amdsensor_t sensor = (amdsensor_t)arg2;
646 int32_t auxtemp[2], temp;
647 int error;
648
649 switch (sensor) {
650 case CORE0:
651 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0);
652 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1);
653 temp = imax(auxtemp[0], auxtemp[1]);
654 break;
655 case CORE1:
656 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0);
657 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1);
658 temp = imax(auxtemp[0], auxtemp[1]);
659 break;
660 default:
661 temp = sc->sc_gettemp(dev, sensor);
662 break;
663 }
664 error = sysctl_handle_int(oidp, &temp, 0, req);
665
666 return (error);
667 }
668
669 #define AMDTEMP_ZERO_C_TO_K 2731
670
671 static int32_t
amdtemp_gettemp0f(device_t dev,amdsensor_t sensor)672 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor)
673 {
674 struct amdtemp_softc *sc = device_get_softc(dev);
675 uint32_t mask, offset, temp;
676
677 mtx_lock(&sc->sc_lock);
678
679 /* Set Sensor/Core selector. */
680 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1);
681 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR);
682 switch (sensor) {
683 case CORE0_SENSOR1:
684 temp |= AMDTEMP_TTSR_SELSENSOR;
685 /* FALLTHROUGH */
686 case CORE0_SENSOR0:
687 case CORE0:
688 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0)
689 temp |= AMDTEMP_TTSR_SELCORE;
690 break;
691 case CORE1_SENSOR1:
692 temp |= AMDTEMP_TTSR_SELSENSOR;
693 /* FALLTHROUGH */
694 case CORE1_SENSOR0:
695 case CORE1:
696 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0)
697 temp |= AMDTEMP_TTSR_SELCORE;
698 break;
699 default:
700 __assert_unreachable();
701 }
702 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1);
703
704 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc;
705 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49;
706 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4);
707 temp = ((temp >> 14) & mask) * 5 / 2;
708 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10;
709
710 mtx_unlock(&sc->sc_lock);
711 return (temp);
712 }
713
714 static uint32_t
amdtemp_decode_fam10h_to_17h(int32_t sc_offset,uint32_t val,bool minus49)715 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49)
716 {
717 uint32_t temp;
718
719 /* Convert raw register subfield units (0.125C) to units of 0.1C. */
720 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4;
721
722 if (minus49)
723 temp -= AMDTEMP_CURTMP_RANGE_ADJUST;
724
725 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10;
726 return (temp);
727 }
728
729 static uint32_t
amdtemp_decode_fam10h_to_16h(int32_t sc_offset,uint32_t val)730 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val)
731 {
732 bool minus49;
733
734 /*
735 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is
736 * adjusted down by 49.0 degrees Celsius. (This adjustment is not
737 * documented in BKDGs prior to family 15h model 00h.)
738 */
739 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 &&
740 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) &
741 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3);
742
743 return (amdtemp_decode_fam10h_to_17h(sc_offset,
744 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
745 }
746
747 static uint32_t
amdtemp_decode_fam17h_tctl(int32_t sc_offset,uint32_t val)748 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val)
749 {
750 bool minus49;
751
752 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0)
753 || ((val & AMDTEMP_17H_CUR_TMP_TJ_SEL) == AMDTEMP_17H_CUR_TMP_TJ_SEL);
754 return (amdtemp_decode_fam10h_to_17h(sc_offset,
755 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
756 }
757
758 static int32_t
amdtemp_gettemp(device_t dev,amdsensor_t sensor)759 amdtemp_gettemp(device_t dev, amdsensor_t sensor)
760 {
761 struct amdtemp_softc *sc = device_get_softc(dev);
762 uint32_t temp;
763
764 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4);
765 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp));
766 }
767
768 static int32_t
amdtemp_gettemp15hm60h(device_t dev,amdsensor_t sensor)769 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor)
770 {
771 struct amdtemp_softc *sc = device_get_softc(dev);
772 uint32_t val;
773 int error __diagused;
774
775 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val);
776 KASSERT(error == 0, ("amdsmn_read"));
777 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val));
778 }
779
780 static int32_t
amdtemp_gettemp17h(device_t dev,amdsensor_t sensor)781 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor)
782 {
783 struct amdtemp_softc *sc = device_get_softc(dev);
784 uint32_t val;
785 int error __diagused;
786
787 switch (sensor) {
788 case CORE0_SENSOR0:
789 /* Tctl */
790 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val);
791 KASSERT(error == 0, ("amdsmn_read"));
792 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val));
793 case CCD_BASE ... CCD_MAX:
794 /* Tccd<N> */
795 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base +
796 (((int)sensor - CCD_BASE) * sizeof(val)), &val);
797 KASSERT(error == 0, ("amdsmn_read2"));
798 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0,
799 ("sensor %d: not valid", (int)sensor));
800 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true));
801 default:
802 __assert_unreachable();
803 }
804 }
805
806 static void
amdtemp_probe_ccd_sensors(device_t dev,uint32_t maxreg)807 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg)
808 {
809 char sensor_name[16], sensor_descr[32];
810 struct amdtemp_softc *sc;
811 uint32_t i, val;
812 int error;
813
814 sc = device_get_softc(dev);
815 for (i = 0; i < maxreg; i++) {
816 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base +
817 (i * sizeof(val)), &val);
818 if (error != 0)
819 continue;
820 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0)
821 continue;
822
823 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i);
824 snprintf(sensor_descr, sizeof(sensor_descr),
825 "CCD %u temperature (Tccd%u)", i, i);
826
827 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
828 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
829 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
830 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr);
831 }
832 }
833
834 static void
amdtemp_probe_ccd_sensors17h(device_t dev,uint32_t model)835 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model)
836 {
837 uint32_t maxreg;
838
839 switch (model) {
840 case 0x00 ... 0x2f: /* Zen1, Zen+ */
841 maxreg = 4;
842 break;
843 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */
844 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */
845 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */
846 maxreg = 8;
847 _Static_assert((int)NUM_CCDS >= 8, "");
848 break;
849 default:
850 device_printf(dev,
851 "Unrecognized Family 17h Model: %02xh\n", model);
852 return;
853 }
854
855 amdtemp_probe_ccd_sensors(dev, maxreg);
856 }
857
858 static void
amdtemp_probe_ccd_sensors19h(device_t dev,uint32_t model)859 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model)
860 {
861 struct amdtemp_softc *sc = device_get_softc(dev);
862 uint32_t maxreg;
863
864 switch (model) {
865 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */
866 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */
867 maxreg = 8;
868 _Static_assert((int)NUM_CCDS >= 8, "");
869 break;
870 case 0x10 ... 0x1f:
871 sc->sc_temp_base = AMDTEMP_ZEN4_10H_CCD_TMP_BASE;
872 maxreg = 12;
873 _Static_assert((int)NUM_CCDS >= 12, "");
874 break;
875 case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */
876 sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE;
877 maxreg = 8;
878 _Static_assert((int)NUM_CCDS >= 8, "");
879 break;
880 default:
881 device_printf(dev,
882 "Unrecognized Family 19h Model: %02xh\n", model);
883 return;
884 }
885
886 amdtemp_probe_ccd_sensors(dev, maxreg);
887 }
888