1 /* $NetBSD: trm.c,v 1.43 2021/08/07 16:19:14 thorpej Exp $ */
2 /*-
3 * Copyright (c) 2002 Izumi Tsutsui. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 /*
27 * Device Driver for Tekram DC395U/UW/F, DC315/U
28 * PCI SCSI Bus Master Host Adapter
29 * (SCSI chip set used Tekram ASIC TRM-S1040)
30 *
31 * Copyright (c) 2001 Rui-Xiang Guo
32 * All rights reserved.
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. The name of the author may not be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 */
56 /*
57 * Ported from
58 * dc395x_trm.c
59 *
60 * Written for NetBSD 1.4.x by
61 * Erich Chen (erich@tekram.com.tw)
62 *
63 * Provided by
64 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved.
65 */
66
67 #include <sys/cdefs.h>
68 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.43 2021/08/07 16:19:14 thorpej Exp $");
69
70 /* #define TRM_DEBUG */
71 #ifdef TRM_DEBUG
72 int trm_debug = 1;
73 #define DPRINTF(arg) if (trm_debug > 0) printf arg;
74 #else
75 #define DPRINTF(arg)
76 #endif
77
78 #include <sys/param.h>
79 #include <sys/systm.h>
80 #include <sys/malloc.h>
81 #include <sys/buf.h>
82 #include <sys/kernel.h>
83 #include <sys/device.h>
84 #include <sys/queue.h>
85
86 #include <sys/bus.h>
87 #include <sys/intr.h>
88
89 #include <dev/scsipi/scsi_spc.h>
90 #include <dev/scsipi/scsi_all.h>
91 #include <dev/scsipi/scsi_message.h>
92 #include <dev/scsipi/scsipi_all.h>
93 #include <dev/scsipi/scsiconf.h>
94
95 #include <dev/pci/pcidevs.h>
96 #include <dev/pci/pcireg.h>
97 #include <dev/pci/pcivar.h>
98 #include <dev/pci/trmreg.h>
99
100 /*
101 * feature of chip set MAX value
102 */
103 #define TRM_MAX_TARGETS 16
104 #define TRM_MAX_LUNS 8
105 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1)
106 #define TRM_MAX_SRB 32 /* XXX */
107 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */
108 #define TRM_MAX_OFFSET 15
109 #define TRM_MAX_PERIOD 125
110
111 /*
112 * Segment Entry
113 */
114 struct trm_sg_entry {
115 uint32_t address;
116 uint32_t length;
117 };
118
119 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES)
120
121 /*
122 **********************************************************************
123 * The SEEPROM structure for TRM_S1040
124 **********************************************************************
125 */
126 struct nvram_target {
127 uint8_t config0; /* Target configuration byte 0 */
128 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */
129 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */
130 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */
131 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */
132 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */
133 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */
134 uint8_t period; /* Target period */
135 uint8_t config2; /* Target configuration byte 2 */
136 uint8_t config3; /* Target configuration byte 3 */
137 };
138
139 struct trm_nvram {
140 uint8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */
141 uint8_t subsys_id[2]; /* 2,3 Sub System ID */
142 uint8_t subclass; /* 4 Sub Class */
143 uint8_t vendor_id[2]; /* 5,6 Vendor ID */
144 uint8_t device_id[2]; /* 7,8 Device ID */
145 uint8_t reserved0; /* 9 Reserved */
146 struct nvram_target target[TRM_MAX_TARGETS];
147 /* 10,11,12,13
148 * 14,15,16,17
149 * ....
150 * 70,71,72,73 */
151 uint8_t scsi_id; /* 74 Host Adapter SCSI ID */
152 uint8_t channel_cfg; /* 75 Channel configuration */
153 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */
154 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */
155 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */
156 #define NAC_GREATER_1G 0x02 /* > 1G support enable */
157 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */
158 uint8_t delay_time; /* 76 Power on delay time */
159 uint8_t max_tag; /* 77 Maximum tags */
160 uint8_t reserved1; /* 78 */
161 uint8_t boot_target; /* 79 */
162 uint8_t boot_lun; /* 80 */
163 uint8_t reserved2; /* 81 */
164 uint8_t reserved3[44]; /* 82,..125 */
165 uint8_t checksum0; /* 126 */
166 uint8_t checksum1; /* 127 */
167 #define TRM_NVRAM_CKSUM 0x1234
168 };
169
170 /* Nvram Initiater bits definition */
171 #define MORE2_DRV 0x00000001
172 #define GREATER_1G 0x00000002
173 #define RST_SCSI_BUS 0x00000004
174 #define ACTIVE_NEGATION 0x00000008
175 #define NO_SEEK 0x00000010
176 #define LUN_CHECK 0x00000020
177
178 #define trm_eeprom_wait() DELAY(30)
179
180 /*
181 *-----------------------------------------------------------------------
182 * SCSI Request Block
183 *-----------------------------------------------------------------------
184 */
185 struct trm_srb {
186 TAILQ_ENTRY(trm_srb) next;
187
188 struct trm_sg_entry *sgentry;
189 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */
190 bus_dmamap_t dmap;
191 bus_size_t sgoffset; /* Xfer buf offset */
192
193 uint32_t buflen; /* Total xfer length */
194 uint32_t sgaddr; /* SGList physical starting address */
195
196 int sgcnt;
197 int sgindex;
198
199 int hastat; /* Host Adapter Status */
200 #define H_STATUS_GOOD 0x00
201 #define H_SEL_TIMEOUT 0x11
202 #define H_OVER_UNDER_RUN 0x12
203 #define H_UNEXP_BUS_FREE 0x13
204 #define H_TARGET_PHASE_F 0x14
205 #define H_INVALID_CCB_OP 0x16
206 #define H_LINK_CCB_BAD 0x17
207 #define H_BAD_TARGET_DIR 0x18
208 #define H_DUPLICATE_CCB 0x19
209 #define H_BAD_CCB_OR_SG 0x1A
210 #define H_ABORT 0xFF
211 int tastat; /* Target SCSI Status Byte */
212 int flag; /* SRBFlag */
213 #define AUTO_REQSENSE 0x0001
214 #define PARITY_ERROR 0x0002
215 #define SRB_TIMEOUT 0x0004
216
217 int cmdlen; /* SCSI command length */
218 uint8_t cmd[12]; /* SCSI command */
219
220 uint8_t tag[2];
221 };
222
223 /*
224 * some info about each target and lun on the SCSI bus
225 */
226 struct trm_linfo {
227 int used; /* number of slots in use */
228 int avail; /* where to start scanning */
229 int busy; /* lun in use */
230 struct trm_srb *untagged;
231 struct trm_srb *queued[TRM_MAX_TAG];
232 };
233
234 struct trm_tinfo {
235 u_int flag; /* Sync mode ? (1 sync):(0 async) */
236 #define SYNC_NEGO_ENABLE 0x0001
237 #define SYNC_NEGO_DOING 0x0002
238 #define SYNC_NEGO_DONE 0x0004
239 #define WIDE_NEGO_ENABLE 0x0008
240 #define WIDE_NEGO_DOING 0x0010
241 #define WIDE_NEGO_DONE 0x0020
242 #define USE_TAG_QUEUING 0x0040
243 #define NO_RESELECT 0x0080
244 struct trm_linfo *linfo[TRM_MAX_LUNS];
245
246 uint8_t config0; /* Target Config */
247 uint8_t period; /* Max Period for nego. */
248 uint8_t synctl; /* Sync control for reg. */
249 uint8_t offset; /* Sync offset for reg. and nego.(low nibble) */
250 };
251
252 /*
253 *-----------------------------------------------------------------------
254 * Adapter Control Block
255 *-----------------------------------------------------------------------
256 */
257 struct trm_softc {
258 device_t sc_dev;
259
260 bus_space_tag_t sc_iot;
261 bus_space_handle_t sc_ioh;
262 bus_dma_tag_t sc_dmat;
263 bus_dmamap_t sc_dmamap; /* Map the control structures */
264
265 struct trm_srb *sc_actsrb;
266 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS];
267
268 TAILQ_HEAD(, trm_srb) sc_freesrb,
269 sc_readysrb;
270 struct trm_srb *sc_srb; /* SRB array */
271
272 struct trm_sg_entry *sc_sglist;
273
274 int sc_maxid;
275 /*
276 * Link to the generic SCSI driver
277 */
278 struct scsipi_channel sc_channel;
279 struct scsipi_adapter sc_adapter;
280
281 int sc_id; /* Adapter SCSI Target ID */
282
283 int sc_state; /* SRB State */
284 #define TRM_IDLE 0
285 #define TRM_WAIT 1
286 #define TRM_READY 2
287 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */
288 #define TRM_MSGIN 4
289 #define TRM_EXTEND_MSGIN 5
290 #define TRM_COMMAND 6
291 #define TRM_START 7 /* arbitration+msg_out+command_out */
292 #define TRM_DISCONNECTED 8
293 #define TRM_DATA_XFER 9
294 #define TRM_XFERPAD 10
295 #define TRM_STATUS 11
296 #define TRM_COMPLETED 12
297 #define TRM_ABORT_SENT 13
298 #define TRM_UNEXPECT_RESEL 14
299
300 int sc_phase; /* SCSI phase */
301 int sc_config;
302 #define HCC_WIDE_CARD 0x01
303 #define HCC_SCSI_RESET 0x02
304 #define HCC_PARITY 0x04
305 #define HCC_AUTOTERM 0x08
306 #define HCC_LOW8TERM 0x10
307 #define HCC_UP8TERM 0x20
308
309 int sc_flag;
310 #define RESET_DEV 0x01
311 #define RESET_DETECT 0x02
312 #define RESET_DONE 0x04
313 #define WAIT_TAGMSG 0x08 /* XXX */
314
315 int sc_msgcnt;
316
317 int resel_target; /* XXX */
318 int resel_lun; /* XXX */
319
320 uint8_t *sc_msg;
321 uint8_t sc_msgbuf[6];
322 };
323
324 /*
325 * SCSI Status codes not defined in scsi_all.h
326 */
327 #define SCSI_COND_MET 0x04 /* Condition Met */
328 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */
329 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */
330 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */
331 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */
332
333 static int trm_match(device_t, cfdata_t, void *);
334 static void trm_attach(device_t, device_t, void *);
335
336 static int trm_init(struct trm_softc *);
337
338 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t,
339 void *);
340 static void trm_update_xfer_mode(struct trm_softc *, int);
341 static void trm_sched(struct trm_softc *);
342 static int trm_select(struct trm_softc *, struct trm_srb *);
343 static void trm_reset(struct trm_softc *);
344 static void trm_timeout(void *);
345 static int trm_intr(void *);
346
347 static void trm_dataout_phase0(struct trm_softc *, int);
348 static void trm_datain_phase0(struct trm_softc *, int);
349 static void trm_status_phase0(struct trm_softc *);
350 static void trm_msgin_phase0(struct trm_softc *);
351 static void trm_command_phase1(struct trm_softc *);
352 static void trm_status_phase1(struct trm_softc *);
353 static void trm_msgout_phase1(struct trm_softc *);
354 static void trm_msgin_phase1(struct trm_softc *);
355
356 static void trm_dataio_xfer(struct trm_softc *, int);
357 static void trm_disconnect(struct trm_softc *);
358 static void trm_reselect(struct trm_softc *);
359 static void trm_done(struct trm_softc *, struct trm_srb *);
360 static int trm_request_sense(struct trm_softc *, struct trm_srb *);
361 static void trm_dequeue(struct trm_softc *, struct trm_srb *);
362
363 static void trm_scsi_reset_detect(struct trm_softc *);
364 static void trm_reset_scsi_bus(struct trm_softc *);
365
366 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *);
367 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *);
368 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *);
369 static void trm_eeprom_set_data(struct trm_softc *, uint8_t, uint8_t);
370 static void trm_eeprom_write_cmd(struct trm_softc *, uint8_t, uint8_t);
371 static uint8_t trm_eeprom_get_data(struct trm_softc *, uint8_t);
372
373 CFATTACH_DECL_NEW(trm, sizeof(struct trm_softc),
374 trm_match, trm_attach, NULL, NULL);
375
376 /* real period: */
377 static const uint8_t trm_clock_period[] = {
378 12, /* 48 ns 20.0 MB/sec */
379 18, /* 72 ns 13.3 MB/sec */
380 25, /* 100 ns 10.0 MB/sec */
381 31, /* 124 ns 8.0 MB/sec */
382 37, /* 148 ns 6.6 MB/sec */
383 43, /* 172 ns 5.7 MB/sec */
384 50, /* 200 ns 5.0 MB/sec */
385 62 /* 248 ns 4.0 MB/sec */
386 };
387 #define NPERIOD __arraycount(trm_clock_period)
388
389 static int
trm_match(device_t parent,cfdata_t cf,void * aux)390 trm_match(device_t parent, cfdata_t cf, void *aux)
391 {
392 struct pci_attach_args *pa = aux;
393
394 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2)
395 switch (PCI_PRODUCT(pa->pa_id)) {
396 case PCI_PRODUCT_TEKRAM2_DC315:
397 return 1;
398 }
399 return 0;
400 }
401
402 /*
403 * attach and init a host adapter
404 */
405 static void
trm_attach(device_t parent,device_t self,void * aux)406 trm_attach(device_t parent, device_t self, void *aux)
407 {
408 struct trm_softc *sc = device_private(self);
409 struct pci_attach_args *const pa = aux;
410 bus_space_tag_t iot;
411 bus_space_handle_t ioh;
412 pci_intr_handle_t ih;
413 pcireg_t command;
414 const char *intrstr;
415 int fl = -1;
416 char intrbuf[PCI_INTRSTR_LEN];
417
418 sc->sc_dev = self;
419
420 /*
421 * Some cards do not allow memory mapped accesses
422 * pa_pc: chipset tag
423 * pa_tag: pci tag
424 */
425 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
426 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) !=
427 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) {
428 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
429 pci_conf_write(pa->pa_pc, pa->pa_tag,
430 PCI_COMMAND_STATUS_REG, command);
431 }
432 /*
433 * mask for get correct base address of pci IO port
434 */
435 if (command & PCI_COMMAND_MEM_ENABLE) {
436 fl = pci_mapreg_map(pa, TRM_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 0, &iot,
437 &ioh, NULL, NULL);
438 }
439 if (fl != 0) {
440 aprint_verbose_dev(self, "couldn't map MMIO registers, trying PIO\n");
441 if ((fl = pci_mapreg_map(pa, TRM_BAR_PIO, PCI_MAPREG_TYPE_IO,
442 0, &iot, &ioh, NULL, NULL)) != 0) {
443 aprint_error(": unable to map registers (%d)\n", fl);
444 return;
445 }
446 }
447 /*
448 * test checksum of eeprom.. & initialize softc...
449 */
450 sc->sc_iot = iot;
451 sc->sc_ioh = ioh;
452 sc->sc_dmat = pa->pa_dmat;
453
454 if (trm_init(sc) != 0) {
455 /*
456 * Error during initialization!
457 */
458 return;
459 }
460 /*
461 * Now try to attach all the sub-devices
462 */
463 if ((sc->sc_config & HCC_WIDE_CARD) != 0)
464 aprint_normal(": Tekram DC395UW/F (TRM-S1040) Fast40 "
465 "Ultra Wide SCSI Adapter\n");
466 else
467 aprint_normal(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 "
468 "Ultra SCSI Adapter\n");
469
470 /*
471 * Now tell the generic SCSI layer about our bus.
472 * map and establish interrupt
473 */
474 if (pci_intr_map(pa, &ih)) {
475 aprint_error_dev(self, "couldn't map interrupt\n");
476 return;
477 }
478 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
479
480 if (pci_intr_establish_xname(pa->pa_pc, ih, IPL_BIO, trm_intr, sc,
481 device_xname(self)) == NULL) {
482 aprint_error_dev(self, "couldn't establish interrupt");
483 if (intrstr != NULL)
484 aprint_error(" at %s", intrstr);
485 aprint_error("\n");
486 return;
487 }
488 if (intrstr != NULL)
489 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
490
491 sc->sc_adapter.adapt_dev = self;
492 sc->sc_adapter.adapt_nchannels = 1;
493 sc->sc_adapter.adapt_openings = TRM_MAX_SRB;
494 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB;
495 sc->sc_adapter.adapt_request = trm_scsipi_request;
496 sc->sc_adapter.adapt_minphys = minphys;
497
498 sc->sc_channel.chan_adapter = &sc->sc_adapter;
499 sc->sc_channel.chan_bustype = &scsi_bustype;
500 sc->sc_channel.chan_channel = 0;
501 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1;
502 sc->sc_channel.chan_nluns = 8;
503 sc->sc_channel.chan_id = sc->sc_id;
504
505 config_found(self, &sc->sc_channel, scsiprint, CFARGS_NONE);
506 }
507
508 /*
509 * initialize the internal structures for a given SCSI host
510 */
511 static int
trm_init(struct trm_softc * sc)512 trm_init(struct trm_softc *sc)
513 {
514 bus_space_tag_t iot = sc->sc_iot;
515 bus_space_handle_t ioh = sc->sc_ioh;
516 bus_dma_segment_t seg;
517 struct trm_nvram eeprom;
518 struct trm_srb *srb;
519 struct trm_tinfo *ti;
520 struct nvram_target *tconf;
521 int error, rseg, all_sgsize;
522 int i, target;
523 uint8_t bval;
524
525 DPRINTF(("\n"));
526
527 /*
528 * allocate the space for all SCSI control blocks (SRB) for DMA memory
529 */
530 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE;
531 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE,
532 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
533 aprint_error(": unable to allocate SCSI REQUEST BLOCKS, "
534 "error = %d\n", error);
535 return 1;
536 }
537 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
538 all_sgsize, (void **) &sc->sc_sglist,
539 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
540 aprint_error(": unable to map SCSI REQUEST BLOCKS, "
541 "error = %d\n", error);
542 return 1;
543 }
544 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1,
545 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
546 aprint_error(": unable to create SRB DMA maps, "
547 "error = %d\n", error);
548 return 1;
549 }
550 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap,
551 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) {
552 aprint_error(": unable to load SRB DMA maps, "
553 "error = %d\n", error);
554 return 1;
555 }
556 DPRINTF(("all_sgsize=%x\n", all_sgsize));
557 memset(sc->sc_sglist, 0, all_sgsize);
558
559 /*
560 * EEPROM CHECKSUM
561 */
562 trm_check_eeprom(sc, &eeprom);
563
564 sc->sc_maxid = 7;
565 sc->sc_config = HCC_AUTOTERM | HCC_PARITY;
566 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) {
567 sc->sc_config |= HCC_WIDE_CARD;
568 sc->sc_maxid = 15;
569 }
570 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET)
571 sc->sc_config |= HCC_SCSI_RESET;
572
573 sc->sc_actsrb = NULL;
574 sc->sc_id = eeprom.scsi_id;
575 sc->sc_flag = 0;
576
577 /*
578 * initialize and link all device's SRB queues of this adapter
579 */
580 TAILQ_INIT(&sc->sc_freesrb);
581 TAILQ_INIT(&sc->sc_readysrb);
582
583 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB,
584 M_DEVBUF, M_WAITOK | M_ZERO);
585 DPRINTF(("all SRB size=%zx\n", sizeof(struct trm_srb) * TRM_MAX_SRB));
586
587 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) {
588 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i;
589 srb->sgoffset = TRM_SG_SIZE * i;
590 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset;
591 /*
592 * map all SRB space to SRB_array
593 */
594 if (bus_dmamap_create(sc->sc_dmat,
595 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0,
596 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) {
597 aprint_error(": unable to create DMA transfer map.\n");
598 free(sc->sc_srb, M_DEVBUF);
599 return 1;
600 }
601 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next);
602 srb++;
603 }
604
605 /*
606 * initialize all target info structures
607 */
608 for (target = 0; target < TRM_MAX_TARGETS; target++) {
609 ti = &sc->sc_tinfo[target];
610 ti->synctl = 0;
611 ti->offset = 0;
612 tconf = &eeprom.target[target];
613 ti->config0 = tconf->config0;
614 ti->period = trm_clock_period[tconf->period & 0x07];
615 ti->flag = 0;
616 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) {
617 #ifdef notyet
618 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0)
619 ti->flag |= USE_TAG_QUEUING;
620 #endif
621 } else
622 ti->flag |= NO_RESELECT;
623
624 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x",
625 target, ti->config0, ti->period));
626 DPRINTF((", flag = 0x%02x\n", ti->flag));
627 }
628
629 /* program configuration 0 */
630 bval = PHASELATCH | INITIATOR | BLOCKRST;
631 if ((sc->sc_config & HCC_PARITY) != 0)
632 bval |= PARITYCHECK;
633 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval);
634
635 /* program configuration 1 */
636 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1,
637 ACTIVE_NEG | ACTIVE_NEGPLUS);
638
639 /* 250ms selection timeout */
640 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT);
641
642 /* Mask all interrupts */
643 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0);
644 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0);
645
646 /* Reset SCSI module */
647 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE);
648
649 /* program Host ID */
650 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id);
651
652 /* set asynchronous transfer */
653 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0);
654
655 /* Turn LED control off */
656 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL,
657 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED);
658
659 /* DMA config */
660 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG,
661 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE);
662
663 /* Clear pending interrupt status */
664 (void)bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS);
665
666 /* Enable SCSI interrupt */
667 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN,
668 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED |
669 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE);
670 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR);
671
672 trm_reset(sc);
673
674 return 0;
675 }
676
677 /*
678 * enqueues a SCSI command
679 * called by the higher level SCSI driver
680 */
681 static void
trm_scsipi_request(struct scsipi_channel * chan,scsipi_adapter_req_t req,void * arg)682 trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
683 void *arg)
684 {
685 bus_space_tag_t iot;
686 bus_space_handle_t ioh;
687 struct trm_softc *sc;
688 struct trm_srb *srb;
689 struct scsipi_xfer *xs;
690 int error, i, s;
691
692 sc = device_private(chan->chan_adapter->adapt_dev);
693 iot = sc->sc_iot;
694 ioh = sc->sc_ioh;
695
696 switch (req) {
697 case ADAPTER_REQ_RUN_XFER:
698 xs = arg;
699 DPRINTF(("trm_scsipi_request.....\n"));
700 DPRINTF(("target= %d lun= %d\n", xs->xs_periph->periph_target,
701 xs->xs_periph->periph_lun));
702 if (xs->xs_control & XS_CTL_RESET) {
703 trm_reset(sc);
704 xs->error = XS_RESET;
705 return;
706 }
707 if (xs->xs_status & XS_STS_DONE) {
708 printf("%s: Is it done?\n", device_xname(sc->sc_dev));
709 xs->xs_status &= ~XS_STS_DONE;
710 }
711
712 s = splbio();
713
714 /* Get SRB */
715 srb = TAILQ_FIRST(&sc->sc_freesrb);
716 if (srb != NULL) {
717 TAILQ_REMOVE(&sc->sc_freesrb, srb, next);
718 } else {
719 xs->error = XS_RESOURCE_SHORTAGE;
720 scsipi_done(xs);
721 splx(s);
722 return;
723 }
724
725 srb->xs = xs;
726 srb->cmdlen = xs->cmdlen;
727 memcpy(srb->cmd, xs->cmd, xs->cmdlen);
728
729 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) {
730 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap,
731 xs->data, xs->datalen, NULL,
732 ((xs->xs_control & XS_CTL_NOSLEEP) ?
733 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) |
734 BUS_DMA_STREAMING |
735 ((xs->xs_control & XS_CTL_DATA_IN) ?
736 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) {
737 printf("%s: DMA transfer map unable to load, "
738 "error = %d\n", device_xname(sc->sc_dev),
739 error);
740 xs->error = XS_DRIVER_STUFFUP;
741 /*
742 * free SRB
743 */
744 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next);
745 splx(s);
746 return;
747 }
748 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0,
749 srb->dmap->dm_mapsize,
750 (xs->xs_control & XS_CTL_DATA_IN) ?
751 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
752
753 /* Set up the scatter gather list */
754 for (i = 0; i < srb->dmap->dm_nsegs; i++) {
755 srb->sgentry[i].address =
756 htole32(srb->dmap->dm_segs[i].ds_addr);
757 srb->sgentry[i].length =
758 htole32(srb->dmap->dm_segs[i].ds_len);
759 }
760 srb->buflen = xs->datalen;
761 srb->sgcnt = srb->dmap->dm_nsegs;
762 } else {
763 srb->sgentry[0].address = 0;
764 srb->sgentry[0].length = 0;
765 srb->buflen = 0;
766 srb->sgcnt = 0;
767 }
768 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
769 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE);
770
771 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */
772
773 srb->sgindex = 0;
774 srb->hastat = 0;
775 srb->tastat = 0;
776 srb->flag = 0;
777
778 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next);
779 if (sc->sc_actsrb == NULL)
780 trm_sched(sc);
781 splx(s);
782
783 if ((xs->xs_control & XS_CTL_POLL) != 0) {
784 int timeout = xs->timeout;
785
786 s = splbio();
787 do {
788 while (--timeout) {
789 DELAY(1000);
790 if (bus_space_read_2(iot, ioh,
791 TRM_SCSI_STATUS) & SCSIINTERRUPT)
792 break;
793 }
794 if (timeout == 0) {
795 trm_timeout(srb);
796 break;
797 } else
798 trm_intr(sc);
799 } while ((xs->xs_status & XS_STS_DONE) == 0);
800 splx(s);
801 }
802 return;
803
804 case ADAPTER_REQ_GROW_RESOURCES:
805 /* XXX Not supported. */
806 return;
807
808 case ADAPTER_REQ_SET_XFER_MODE:
809 {
810 struct trm_tinfo *ti;
811 struct scsipi_xfer_mode *xm;
812
813 xm = arg;
814 ti = &sc->sc_tinfo[xm->xm_target];
815 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE);
816
817 #ifdef notyet
818 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0)
819 ti->flag |= USE_TAG_QUEUING;
820 else
821 #endif
822 ti->flag &= ~USE_TAG_QUEUING;
823
824 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 &&
825 (sc->sc_config & HCC_WIDE_CARD) != 0 &&
826 (ti->config0 & NTC_DO_WIDE_NEGO) != 0) {
827 ti->flag |= WIDE_NEGO_ENABLE;
828 ti->flag &= ~WIDE_NEGO_DONE;
829 }
830
831 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 &&
832 (ti->config0 & NTC_DO_SYNC_NEGO) != 0) {
833 ti->flag |= SYNC_NEGO_ENABLE;
834 ti->flag &= ~SYNC_NEGO_DONE;
835 ti->period = trm_clock_period[0];
836 }
837
838 /*
839 * If we're not going to negotiate, send the
840 * notification now, since it won't happen later.
841 */
842 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) ==
843 (WIDE_NEGO_DONE|SYNC_NEGO_DONE))
844 trm_update_xfer_mode(sc, xm->xm_target);
845
846 return;
847 }
848 }
849 }
850
851 static void
trm_update_xfer_mode(struct trm_softc * sc,int target)852 trm_update_xfer_mode(struct trm_softc *sc, int target)
853 {
854 struct scsipi_xfer_mode xm;
855 struct trm_tinfo *ti;
856
857 ti = &sc->sc_tinfo[target];
858 xm.xm_target = target;
859 xm.xm_mode = 0;
860 xm.xm_period = 0;
861 xm.xm_offset = 0;
862
863 if ((ti->synctl & WIDE_SYNC) != 0)
864 xm.xm_mode |= PERIPH_CAP_WIDE16;
865
866 if (ti->period > 0) {
867 xm.xm_mode |= PERIPH_CAP_SYNC;
868 xm.xm_period = ti->period;
869 xm.xm_offset = ti->offset;
870 }
871
872 #ifdef notyet
873 if ((ti->flag & USE_TAG_QUEUING) != 0)
874 xm.xm_mode |= PERIPH_CAP_TQING;
875 #endif
876
877 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm);
878 }
879
880 static void
trm_sched(struct trm_softc * sc)881 trm_sched(struct trm_softc *sc)
882 {
883 struct trm_srb *srb;
884 struct scsipi_periph *periph;
885 struct trm_tinfo *ti;
886 struct trm_linfo *li;
887 int s, lun, tag;
888
889 DPRINTF(("trm_sched...\n"));
890
891 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) {
892 periph = srb->xs->xs_periph;
893 ti = &sc->sc_tinfo[periph->periph_target];
894 lun = periph->periph_lun;
895
896 /* select type of tag for this command */
897 if ((ti->flag & NO_RESELECT) != 0 ||
898 (ti->flag & USE_TAG_QUEUING) == 0 ||
899 (srb->flag & AUTO_REQSENSE) != 0 ||
900 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0)
901 tag = 0;
902 else
903 tag = srb->xs->xs_tag_type;
904 #if 0
905 /* XXX use tags for polled commands? */
906 if (srb->xs->xs_control & XS_CTL_POLL)
907 tag = 0;
908 #endif
909
910 s = splbio();
911 li = ti->linfo[lun];
912 if (li == NULL) {
913 /* initialize lun info */
914 if ((li = malloc(sizeof(*li), M_DEVBUF,
915 M_NOWAIT|M_ZERO)) == NULL) {
916 splx(s);
917 continue;
918 }
919 ti->linfo[lun] = li;
920 }
921
922 if (tag == 0) {
923 /* try to issue this srb as an un-tagged command */
924 if (li->untagged == NULL)
925 li->untagged = srb;
926 }
927 if (li->untagged != NULL) {
928 tag = 0;
929 if (li->busy != 1 && li->used == 0) {
930 /* we need to issue the untagged command now */
931 srb = li->untagged;
932 periph = srb->xs->xs_periph;
933 } else {
934 /* not ready yet */
935 splx(s);
936 continue;
937 }
938 }
939 srb->tag[0] = tag;
940 if (tag != 0) {
941 li->queued[srb->xs->xs_tag_id] = srb;
942 srb->tag[1] = srb->xs->xs_tag_id;
943 li->used++;
944 }
945
946 if (li->untagged != NULL && li->busy != 1) {
947 li->busy = 1;
948 TAILQ_REMOVE(&sc->sc_readysrb, srb, next);
949 sc->sc_actsrb = srb;
950 trm_select(sc, srb);
951 splx(s);
952 break;
953 }
954 if (li->untagged == NULL && tag != 0) {
955 TAILQ_REMOVE(&sc->sc_readysrb, srb, next);
956 sc->sc_actsrb = srb;
957 trm_select(sc, srb);
958 splx(s);
959 break;
960 } else
961 splx(s);
962 }
963 }
964
965 static int
trm_select(struct trm_softc * sc,struct trm_srb * srb)966 trm_select(struct trm_softc *sc, struct trm_srb *srb)
967 {
968 bus_space_tag_t iot = sc->sc_iot;
969 bus_space_handle_t ioh = sc->sc_ioh;
970 struct scsipi_periph *periph = srb->xs->xs_periph;
971 int target = periph->periph_target;
972 int lun = periph->periph_lun;
973 struct trm_tinfo *ti = &sc->sc_tinfo[target];
974 uint8_t scsicmd;
975
976 DPRINTF(("trm_select.....\n"));
977
978 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) {
979 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout),
980 trm_timeout, srb);
981 }
982
983 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id);
984 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target);
985 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl);
986 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset);
987 /* Flush FIFO */
988 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
989 DELAY(10);
990
991 sc->sc_phase = PH_BUS_FREE; /* initial phase */
992
993 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0]));
994
995 if (((ti->flag & WIDE_NEGO_ENABLE) &&
996 (ti->flag & WIDE_NEGO_DONE) == 0) ||
997 ((ti->flag & SYNC_NEGO_ENABLE) &&
998 (ti->flag & SYNC_NEGO_DONE) == 0)) {
999 sc->sc_state = TRM_MSGOUT;
1000 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO,
1001 MSG_IDENTIFY(lun, 0));
1002 bus_space_write_multi_1(iot, ioh,
1003 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen);
1004 /* it's important for atn stop */
1005 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
1006 DO_DATALATCH | DO_HWRESELECT);
1007 /* SCSI command */
1008 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP);
1009 DPRINTF(("select with SEL_ATNSTOP\n"));
1010 return 0;
1011 }
1012
1013 if (srb->tag[0] != 0) {
1014 /* Send identify message */
1015 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO,
1016 MSG_IDENTIFY(lun, 1));
1017 /* Send Tag id */
1018 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]);
1019 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]);
1020 scsicmd = SCMD_SEL_ATN3;
1021 DPRINTF(("select with SEL_ATN3\n"));
1022 } else {
1023 /* Send identify message */
1024 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO,
1025 MSG_IDENTIFY(lun,
1026 (ti->flag & NO_RESELECT) == 0 &&
1027 (srb->flag & AUTO_REQSENSE) == 0 &&
1028 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0));
1029 scsicmd = SCMD_SEL_ATN;
1030 DPRINTF(("select with SEL_ATN\n"));
1031 }
1032 sc->sc_state = TRM_START;
1033
1034 /*
1035 * Send CDB ..command block...
1036 */
1037 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen);
1038
1039 /*
1040 * If trm_select returns 0: current interrupt status
1041 * is interrupt enable. It's said that SCSI processor is
1042 * unoccupied.
1043 */
1044 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */
1045 /* SCSI command */
1046 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd);
1047 return 0;
1048 }
1049
1050 /*
1051 * perform a hard reset on the SCSI bus (and TRM_S1040 chip).
1052 */
1053 static void
trm_reset(struct trm_softc * sc)1054 trm_reset(struct trm_softc *sc)
1055 {
1056 bus_space_tag_t iot = sc->sc_iot;
1057 bus_space_handle_t ioh = sc->sc_ioh;
1058 int s;
1059
1060 DPRINTF(("trm_reset.........\n"));
1061
1062 s = splbio();
1063
1064 /* disable SCSI and DMA interrupt */
1065 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0);
1066 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0);
1067
1068 trm_reset_scsi_bus(sc);
1069 DELAY(100000);
1070
1071 /* Enable SCSI interrupt */
1072 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN,
1073 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED |
1074 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE);
1075
1076 /* Enable DMA interrupt */
1077 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR);
1078
1079 /* Clear DMA FIFO */
1080 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO);
1081
1082 /* Clear SCSI FIFO */
1083 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
1084
1085 sc->sc_actsrb = NULL;
1086 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */
1087
1088 splx(s);
1089 }
1090
1091 static void
trm_timeout(void * arg)1092 trm_timeout(void *arg)
1093 {
1094 struct trm_srb *srb = (struct trm_srb *)arg;
1095 struct scsipi_xfer *xs;
1096 struct scsipi_periph *periph;
1097 struct trm_softc *sc;
1098 int s;
1099
1100 if (srb == NULL) {
1101 printf("trm_timeout called with srb == NULL\n");
1102 return;
1103 }
1104
1105 xs = srb->xs;
1106 if (xs == NULL) {
1107 printf("trm_timeout called with xs == NULL\n");
1108 return;
1109 }
1110
1111 periph = xs->xs_periph;
1112 scsipi_printaddr(xs->xs_periph);
1113 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode);
1114
1115 sc = device_private(periph->periph_channel->chan_adapter->adapt_dev);
1116
1117 trm_reset_scsi_bus(sc);
1118 s = splbio();
1119 srb->flag |= SRB_TIMEOUT;
1120 trm_done(sc, srb);
1121 /* XXX needs more.. */
1122 splx(s);
1123 }
1124
1125 /*
1126 * Catch an interrupt from the adapter
1127 * Process pending device interrupts.
1128 */
1129 static int
trm_intr(void * arg)1130 trm_intr(void *arg)
1131 {
1132 bus_space_tag_t iot;
1133 bus_space_handle_t ioh;
1134 struct trm_softc *sc;
1135 int intstat, stat;
1136
1137 DPRINTF(("trm_intr......\n"));
1138 sc = arg;
1139 if (sc == NULL)
1140 return 0;
1141
1142 iot = sc->sc_iot;
1143 ioh = sc->sc_ioh;
1144
1145 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS);
1146 if ((stat & SCSIINTERRUPT) == 0)
1147 return 0;
1148
1149 DPRINTF(("stat = %04x, ", stat));
1150 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS);
1151
1152 DPRINTF(("intstat=%02x, ", intstat));
1153 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) {
1154 DPRINTF(("\n"));
1155 trm_disconnect(sc);
1156 return 1;
1157 }
1158 if (intstat & INT_RESELECTED) {
1159 DPRINTF(("\n"));
1160 trm_reselect(sc);
1161 return 1;
1162 }
1163 if (intstat & INT_SCSIRESET) {
1164 DPRINTF(("\n"));
1165 trm_scsi_reset_detect(sc);
1166 return 1;
1167 }
1168 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) {
1169 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n",
1170 sc->sc_phase, sc->sc_state));
1171 /*
1172 * software sequential machine
1173 */
1174
1175 /*
1176 * call phase0 functions... "phase entry" handle
1177 * every phase before start transfer
1178 */
1179 switch (sc->sc_phase) {
1180 case PH_DATA_OUT:
1181 trm_dataout_phase0(sc, stat);
1182 break;
1183 case PH_DATA_IN:
1184 trm_datain_phase0(sc, stat);
1185 break;
1186 case PH_COMMAND:
1187 break;
1188 case PH_STATUS:
1189 trm_status_phase0(sc);
1190 stat = PH_BUS_FREE;
1191 break;
1192 case PH_MSG_OUT:
1193 if (sc->sc_state == TRM_UNEXPECT_RESEL ||
1194 sc->sc_state == TRM_ABORT_SENT)
1195 stat = PH_BUS_FREE;
1196 break;
1197 case PH_MSG_IN:
1198 trm_msgin_phase0(sc);
1199 stat = PH_BUS_FREE;
1200 break;
1201 case PH_BUS_FREE:
1202 break;
1203 default:
1204 printf("%s: unexpected phase in trm_intr() phase0\n",
1205 device_xname(sc->sc_dev));
1206 break;
1207 }
1208
1209 sc->sc_phase = stat & PHASEMASK;
1210
1211 switch (sc->sc_phase) {
1212 case PH_DATA_OUT:
1213 trm_dataio_xfer(sc, XFERDATAOUT);
1214 break;
1215 case PH_DATA_IN:
1216 trm_dataio_xfer(sc, XFERDATAIN);
1217 break;
1218 case PH_COMMAND:
1219 trm_command_phase1(sc);
1220 break;
1221 case PH_STATUS:
1222 trm_status_phase1(sc);
1223 break;
1224 case PH_MSG_OUT:
1225 trm_msgout_phase1(sc);
1226 break;
1227 case PH_MSG_IN:
1228 trm_msgin_phase1(sc);
1229 break;
1230 case PH_BUS_FREE:
1231 break;
1232 default:
1233 printf("%s: unexpected phase in trm_intr() phase1\n",
1234 device_xname(sc->sc_dev));
1235 break;
1236 }
1237
1238 return 1;
1239 }
1240 return 0;
1241 }
1242
1243 static void
trm_msgout_phase1(struct trm_softc * sc)1244 trm_msgout_phase1(struct trm_softc *sc)
1245 {
1246 bus_space_tag_t iot = sc->sc_iot;
1247 bus_space_handle_t ioh = sc->sc_ioh;
1248 struct trm_srb *srb;
1249 struct scsipi_periph *periph;
1250 struct trm_tinfo *ti;
1251
1252 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
1253
1254 srb = sc->sc_actsrb;
1255
1256 /* message out phase */
1257 if (srb != NULL) {
1258 periph = srb->xs->xs_periph;
1259 ti = &sc->sc_tinfo[periph->periph_target];
1260
1261 if ((ti->flag & WIDE_NEGO_DOING) == 0 &&
1262 (ti->flag & WIDE_NEGO_ENABLE)) {
1263 /* send WDTR */
1264 ti->flag &= ~SYNC_NEGO_DONE;
1265
1266 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0);
1267 sc->sc_msgbuf[1] = MSG_EXTENDED;
1268 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN;
1269 sc->sc_msgbuf[3] = MSG_EXT_WDTR;
1270 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT;
1271 sc->sc_msgcnt = 5;
1272
1273 ti->flag |= WIDE_NEGO_DOING;
1274 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 &&
1275 (ti->flag & SYNC_NEGO_ENABLE)) {
1276 /* send SDTR */
1277 int cnt = 0;
1278
1279 if ((ti->flag & WIDE_NEGO_DONE) == 0)
1280 sc->sc_msgbuf[cnt++] =
1281 MSG_IDENTIFY(periph->periph_lun, 0);
1282
1283 sc->sc_msgbuf[cnt++] = MSG_EXTENDED;
1284 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN;
1285 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR;
1286 sc->sc_msgbuf[cnt++] = ti->period;
1287 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET;
1288 sc->sc_msgcnt = cnt;
1289 ti->flag |= SYNC_NEGO_DOING;
1290 }
1291 }
1292 if (sc->sc_msgcnt == 0) {
1293 sc->sc_msgbuf[0] = MSG_ABORT;
1294 sc->sc_msgcnt = 1;
1295 sc->sc_state = TRM_ABORT_SENT;
1296 }
1297
1298 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt));
1299 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n",
1300 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2],
1301 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5]));
1302
1303 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO,
1304 sc->sc_msgbuf, sc->sc_msgcnt);
1305 sc->sc_msgcnt = 0;
1306 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf));
1307
1308 /* it's important for atn stop */
1309 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1310
1311 /*
1312 * SCSI command
1313 */
1314 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT);
1315 }
1316
1317 static void
trm_command_phase1(struct trm_softc * sc)1318 trm_command_phase1(struct trm_softc *sc)
1319 {
1320 bus_space_tag_t iot = sc->sc_iot;
1321 bus_space_handle_t ioh = sc->sc_ioh;
1322 struct trm_srb *srb;
1323
1324 srb = sc->sc_actsrb;
1325 if (srb == NULL) {
1326 DPRINTF(("trm_command_phase1: no active srb\n"));
1327 return;
1328 }
1329
1330 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO);
1331 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen);
1332
1333 sc->sc_state = TRM_COMMAND;
1334 /* it's important for atn stop */
1335 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1336
1337 /*
1338 * SCSI command
1339 */
1340 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT);
1341 }
1342
1343 static void
trm_dataout_phase0(struct trm_softc * sc,int stat)1344 trm_dataout_phase0(struct trm_softc *sc, int stat)
1345 {
1346 bus_space_tag_t iot = sc->sc_iot;
1347 bus_space_handle_t ioh = sc->sc_ioh;
1348 struct trm_srb *srb;
1349 struct scsipi_periph *periph;
1350 struct trm_tinfo *ti;
1351 struct trm_sg_entry *sg;
1352 int sgindex;
1353 uint32_t xferlen, leftcnt = 0;
1354
1355 if (sc->sc_state == TRM_XFERPAD)
1356 return;
1357
1358 srb = sc->sc_actsrb;
1359 if (srb == NULL) {
1360 DPRINTF(("trm_dataout_phase0: no active srb\n"));
1361 return;
1362 }
1363 periph = srb->xs->xs_periph;
1364 ti = &sc->sc_tinfo[periph->periph_target];
1365
1366 if ((stat & PARITYERROR) != 0)
1367 srb->flag |= PARITY_ERROR;
1368
1369 if ((stat & SCSIXFERDONE) == 0) {
1370 /*
1371 * when data transfer from DMA FIFO to SCSI FIFO
1372 * if there was some data left in SCSI FIFO
1373 */
1374 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) &
1375 SCSI_FIFOCNT_MASK;
1376 if (ti->synctl & WIDE_SYNC)
1377 /*
1378 * if WIDE scsi SCSI FIFOCNT unit is word
1379 * so need to * 2
1380 */
1381 leftcnt <<= 1;
1382 }
1383 /*
1384 * calculate all the residue data that was not yet transferred
1385 * SCSI transfer counter + left in SCSI FIFO data
1386 *
1387 * .....TRM_SCSI_XCNT (24bits)
1388 * The counter always decrements by one for every SCSI
1389 * byte transfer.
1390 * .....TRM_SCSI_FIFOCNT ( 5bits)
1391 * The counter is SCSI FIFO offset counter
1392 */
1393 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT);
1394 if (leftcnt == 1) {
1395 leftcnt = 0;
1396 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
1397 }
1398 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) {
1399 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) &
1400 DMAXFERCOMP) == 0)
1401 ; /* XXX needs timeout */
1402
1403 srb->buflen = 0;
1404 } else {
1405 /* Update SG list */
1406
1407 /*
1408 * if transfer not yet complete
1409 * there were some data residue in SCSI FIFO or
1410 * SCSI transfer counter not empty
1411 */
1412 if (srb->buflen != leftcnt) {
1413 /* data that had transferred length */
1414 xferlen = srb->buflen - leftcnt;
1415
1416 /* next time to be transferred length */
1417 srb->buflen = leftcnt;
1418
1419 /*
1420 * parsing from last time disconnect sgindex
1421 */
1422 sg = srb->sgentry + srb->sgindex;
1423 for (sgindex = srb->sgindex;
1424 sgindex < srb->sgcnt;
1425 sgindex++, sg++) {
1426 /*
1427 * find last time which SG transfer
1428 * be disconnect
1429 */
1430 if (xferlen >= le32toh(sg->length))
1431 xferlen -= le32toh(sg->length);
1432 else {
1433 /*
1434 * update last time
1435 * disconnected SG list
1436 */
1437 /* residue data length */
1438 sg->length =
1439 htole32(le32toh(sg->length)
1440 - xferlen);
1441 /* residue data pointer */
1442 sg->address =
1443 htole32(le32toh(sg->address)
1444 + xferlen);
1445 srb->sgindex = sgindex;
1446 break;
1447 }
1448 }
1449 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1450 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE);
1451 }
1452 }
1453 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER);
1454 }
1455
1456 static void
trm_datain_phase0(struct trm_softc * sc,int stat)1457 trm_datain_phase0(struct trm_softc *sc, int stat)
1458 {
1459 bus_space_tag_t iot = sc->sc_iot;
1460 bus_space_handle_t ioh = sc->sc_ioh;
1461 struct trm_srb *srb;
1462 struct trm_sg_entry *sg;
1463 int sgindex;
1464 uint32_t xferlen, leftcnt = 0;
1465
1466 if (sc->sc_state == TRM_XFERPAD)
1467 return;
1468
1469 srb = sc->sc_actsrb;
1470 if (srb == NULL) {
1471 DPRINTF(("trm_datain_phase0: no active srb\n"));
1472 return;
1473 }
1474
1475 if (stat & PARITYERROR)
1476 srb->flag |= PARITY_ERROR;
1477
1478 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT);
1479 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) {
1480 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) &
1481 DMAXFERCOMP) == 0)
1482 ; /* XXX needs timeout */
1483
1484 srb->buflen = 0;
1485 } else { /* phase changed */
1486 /*
1487 * parsing the case:
1488 * when a transfer not yet complete
1489 * but be disconnected by upper layer
1490 * if transfer not yet complete
1491 * there were some data residue in SCSI FIFO or
1492 * SCSI transfer counter not empty
1493 */
1494 if (srb->buflen != leftcnt) {
1495 /*
1496 * data that had transferred length
1497 */
1498 xferlen = srb->buflen - leftcnt;
1499
1500 /*
1501 * next time to be transferred length
1502 */
1503 srb->buflen = leftcnt;
1504
1505 /*
1506 * parsing from last time disconnect sgindex
1507 */
1508 sg = srb->sgentry + srb->sgindex;
1509 for (sgindex = srb->sgindex;
1510 sgindex < srb->sgcnt;
1511 sgindex++, sg++) {
1512 /*
1513 * find last time which SG transfer
1514 * be disconnect
1515 */
1516 if (xferlen >= le32toh(sg->length))
1517 xferlen -= le32toh(sg->length);
1518 else {
1519 /*
1520 * update last time
1521 * disconnected SG list
1522 */
1523 /* residue data length */
1524 sg->length =
1525 htole32(le32toh(sg->length)
1526 - xferlen);
1527 /* residue data pointer */
1528 sg->address =
1529 htole32(le32toh(sg->address)
1530 + xferlen);
1531 srb->sgindex = sgindex;
1532 break;
1533 }
1534 }
1535 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1536 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE);
1537 }
1538 }
1539 }
1540
1541 static void
trm_dataio_xfer(struct trm_softc * sc,int iodir)1542 trm_dataio_xfer(struct trm_softc *sc, int iodir)
1543 {
1544 bus_space_tag_t iot = sc->sc_iot;
1545 bus_space_handle_t ioh = sc->sc_ioh;
1546 struct trm_srb *srb;
1547 struct scsipi_periph *periph;
1548 struct trm_tinfo *ti;
1549
1550 srb = sc->sc_actsrb;
1551 if (srb == NULL) {
1552 DPRINTF(("trm_dataio_xfer: no active srb\n"));
1553 return;
1554 }
1555 periph = srb->xs->xs_periph;
1556 ti = &sc->sc_tinfo[periph->periph_target];
1557
1558 if (srb->sgindex < srb->sgcnt) {
1559 if (srb->buflen > 0) {
1560 /*
1561 * load what physical address of Scatter/Gather
1562 * list table want to be transfer
1563 */
1564 sc->sc_state = TRM_DATA_XFER;
1565 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0);
1566 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR,
1567 srb->sgaddr +
1568 srb->sgindex * sizeof(struct trm_sg_entry));
1569 /*
1570 * load how many bytes in the Scatter/Gather list table
1571 */
1572 bus_space_write_4(iot, ioh, TRM_DMA_XCNT,
1573 (srb->sgcnt - srb->sgindex)
1574 * sizeof(struct trm_sg_entry));
1575 /*
1576 * load total xfer length (24bits) max value 16Mbyte
1577 */
1578 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen);
1579 /* Start DMA transfer */
1580 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND,
1581 iodir | SGXFER);
1582 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL,
1583 STARTDMAXFER);
1584
1585 /* Start SCSI transfer */
1586 /* it's important for atn stop */
1587 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
1588 DO_DATALATCH);
1589
1590 /*
1591 * SCSI command
1592 */
1593 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND,
1594 (iodir == XFERDATAOUT) ?
1595 SCMD_DMA_OUT : SCMD_DMA_IN);
1596 } else { /* xfer pad */
1597 if (srb->sgcnt) {
1598 srb->hastat = H_OVER_UNDER_RUN;
1599 }
1600 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT,
1601 (ti->synctl & WIDE_SYNC) ? 2 : 1);
1602
1603 if (iodir == XFERDATAOUT)
1604 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0);
1605 else
1606 (void)bus_space_read_2(iot, ioh, TRM_SCSI_FIFO);
1607
1608 sc->sc_state = TRM_XFERPAD;
1609 /* it's important for atn stop */
1610 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
1611 DO_DATALATCH);
1612
1613 /*
1614 * SCSI command
1615 */
1616 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND,
1617 (iodir == XFERDATAOUT) ?
1618 SCMD_FIFO_OUT : SCMD_FIFO_IN);
1619 }
1620 }
1621 }
1622
1623 static void
trm_status_phase0(struct trm_softc * sc)1624 trm_status_phase0(struct trm_softc *sc)
1625 {
1626 bus_space_tag_t iot = sc->sc_iot;
1627 bus_space_handle_t ioh = sc->sc_ioh;
1628 struct trm_srb *srb;
1629
1630 srb = sc->sc_actsrb;
1631 if (srb == NULL) {
1632 DPRINTF(("trm_status_phase0: no active srb\n"));
1633 return;
1634 }
1635 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO);
1636 sc->sc_state = TRM_COMPLETED;
1637 /* it's important for atn stop */
1638 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1639
1640 /*
1641 * SCSI command
1642 */
1643 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT);
1644 }
1645
1646 static void
trm_status_phase1(struct trm_softc * sc)1647 trm_status_phase1(struct trm_softc *sc)
1648 {
1649 bus_space_tag_t iot = sc->sc_iot;
1650 bus_space_handle_t ioh = sc->sc_ioh;
1651
1652 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) {
1653 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT)
1654 & SCSI_FIFO_EMPTY) == 0)
1655 bus_space_write_2(iot, ioh,
1656 TRM_SCSI_CONTROL, DO_CLRFIFO);
1657 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS)
1658 & DMA_FIFO_EMPTY) == 0)
1659 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO);
1660 } else {
1661 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS)
1662 & DMA_FIFO_EMPTY) == 0)
1663 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO);
1664 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT)
1665 & SCSI_FIFO_EMPTY) == 0)
1666 bus_space_write_2(iot, ioh,
1667 TRM_SCSI_CONTROL, DO_CLRFIFO);
1668 }
1669 sc->sc_state = TRM_STATUS;
1670 /* it's important for atn stop */
1671 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1672
1673 /*
1674 * SCSI command
1675 */
1676 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP);
1677 }
1678
1679 static void
trm_msgin_phase0(struct trm_softc * sc)1680 trm_msgin_phase0(struct trm_softc *sc)
1681 {
1682 bus_space_tag_t iot = sc->sc_iot;
1683 bus_space_handle_t ioh = sc->sc_ioh;
1684 struct trm_srb *srb;
1685 struct scsipi_periph *periph;
1686 struct trm_tinfo *ti;
1687 int index;
1688 uint8_t msgin_code;
1689
1690 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO);
1691 if (sc->sc_state != TRM_EXTEND_MSGIN) {
1692 DPRINTF(("msgin: code = %02x\n", msgin_code));
1693 switch (msgin_code) {
1694 case MSG_DISCONNECT:
1695 sc->sc_state = TRM_DISCONNECTED;
1696 break;
1697
1698 case MSG_SAVEDATAPOINTER:
1699 break;
1700
1701 case MSG_EXTENDED:
1702 case MSG_SIMPLE_Q_TAG:
1703 case MSG_HEAD_OF_Q_TAG:
1704 case MSG_ORDERED_Q_TAG:
1705 sc->sc_state = TRM_EXTEND_MSGIN;
1706 /* extended message (01h) */
1707 sc->sc_msgbuf[0] = msgin_code;
1708
1709 sc->sc_msgcnt = 1;
1710 /* extended message length (n) */
1711 sc->sc_msg = &sc->sc_msgbuf[1];
1712
1713 break;
1714 case MSG_MESSAGE_REJECT:
1715 /* Reject message */
1716 srb = sc->sc_actsrb;
1717 if (srb == NULL) {
1718 DPRINTF(("trm_msgin_phase0: "
1719 " message reject without actsrb\n"));
1720 break;
1721 }
1722 periph = srb->xs->xs_periph;
1723 ti = &sc->sc_tinfo[periph->periph_target];
1724
1725 if (ti->flag & WIDE_NEGO_ENABLE) {
1726 /* do wide nego reject */
1727 ti->flag |= WIDE_NEGO_DONE;
1728 ti->flag &=
1729 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE);
1730 if ((ti->flag & SYNC_NEGO_ENABLE) &&
1731 (ti->flag & SYNC_NEGO_DONE) == 0) {
1732 /* Set ATN, in case ATN was clear */
1733 sc->sc_state = TRM_MSGOUT;
1734 bus_space_write_2(iot, ioh,
1735 TRM_SCSI_CONTROL, DO_SETATN);
1736 } else
1737 /* Clear ATN */
1738 bus_space_write_2(iot, ioh,
1739 TRM_SCSI_CONTROL, DO_CLRATN);
1740 } else if (ti->flag & SYNC_NEGO_ENABLE) {
1741 /* do sync nego reject */
1742 bus_space_write_2(iot, ioh,
1743 TRM_SCSI_CONTROL, DO_CLRATN);
1744 if (ti->flag & SYNC_NEGO_DOING) {
1745 ti->flag &=~(SYNC_NEGO_ENABLE |
1746 SYNC_NEGO_DONE);
1747 ti->synctl = 0;
1748 ti->offset = 0;
1749 bus_space_write_1(iot, ioh,
1750 TRM_SCSI_SYNC, ti->synctl);
1751 bus_space_write_1(iot, ioh,
1752 TRM_SCSI_OFFSET, ti->offset);
1753 }
1754 }
1755 break;
1756
1757 case MSG_IGN_WIDE_RESIDUE:
1758 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1);
1759 (void)bus_space_read_1(iot, ioh, TRM_SCSI_FIFO);
1760 break;
1761
1762 default:
1763 /*
1764 * Restore data pointer message
1765 * Save data pointer message
1766 * Completion message
1767 * NOP message
1768 */
1769 break;
1770 }
1771 } else {
1772 /*
1773 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN
1774 * Parsing incoming extented messages
1775 */
1776 *sc->sc_msg++ = msgin_code;
1777 sc->sc_msgcnt++;
1778
1779 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt));
1780 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n",
1781 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2],
1782 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5]));
1783
1784 switch (sc->sc_msgbuf[0]) {
1785 case MSG_SIMPLE_Q_TAG:
1786 case MSG_HEAD_OF_Q_TAG:
1787 case MSG_ORDERED_Q_TAG:
1788 /*
1789 * is QUEUE tag message :
1790 *
1791 * byte 0:
1792 * HEAD QUEUE TAG (20h)
1793 * ORDERED QUEUE TAG (21h)
1794 * SIMPLE QUEUE TAG (22h)
1795 * byte 1:
1796 * Queue tag (00h - FFh)
1797 */
1798 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) {
1799 /* XXX XXX XXX */
1800 struct trm_linfo *li;
1801 int tagid;
1802
1803 sc->sc_flag &= ~WAIT_TAGMSG;
1804 tagid = sc->sc_msgbuf[1];
1805 ti = &sc->sc_tinfo[sc->resel_target];
1806 li = ti->linfo[sc->resel_lun];
1807 srb = li->queued[tagid];
1808 if (srb != NULL) {
1809 sc->sc_actsrb = srb;
1810 sc->sc_state = TRM_DATA_XFER;
1811 break;
1812 } else {
1813 printf("%s: invalid tag id\n",
1814 device_xname(sc->sc_dev));
1815 }
1816
1817 sc->sc_state = TRM_UNEXPECT_RESEL;
1818 sc->sc_msgbuf[0] = MSG_ABORT_TAG;
1819 sc->sc_msgcnt = 1;
1820 bus_space_write_2(iot, ioh,
1821 TRM_SCSI_CONTROL, DO_SETATN);
1822 } else
1823 sc->sc_state = TRM_IDLE;
1824 break;
1825
1826 case MSG_EXTENDED:
1827 srb = sc->sc_actsrb;
1828 if (srb == NULL) {
1829 DPRINTF(("trm_msgin_phase0: "
1830 "extended message without actsrb\n"));
1831 break;
1832 }
1833 periph = srb->xs->xs_periph;
1834 ti = &sc->sc_tinfo[periph->periph_target];
1835
1836 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR &&
1837 sc->sc_msgcnt == 4) {
1838 /*
1839 * is Wide data xfer Extended message :
1840 * ======================================
1841 * WIDE DATA TRANSFER REQUEST
1842 * ======================================
1843 * byte 0 : Extended message (01h)
1844 * byte 1 : Extended message length (02h)
1845 * byte 2 : WIDE DATA TRANSFER code (03h)
1846 * byte 3 : Transfer width exponent
1847 */
1848 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) {
1849 /* Length is wrong, reject it */
1850 ti->flag &= ~(WIDE_NEGO_ENABLE |
1851 WIDE_NEGO_DONE);
1852 sc->sc_state = TRM_MSGOUT;
1853 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT;
1854 sc->sc_msgcnt = 1;
1855 bus_space_write_2(iot, ioh,
1856 TRM_SCSI_CONTROL, DO_SETATN);
1857 break;
1858 }
1859
1860 if ((ti->flag & WIDE_NEGO_ENABLE) == 0)
1861 sc->sc_msgbuf[3] =
1862 MSG_EXT_WDTR_BUS_8_BIT;
1863
1864 if (sc->sc_msgbuf[3] >
1865 MSG_EXT_WDTR_BUS_32_BIT) {
1866 /* reject_msg: */
1867 ti->flag &= ~(WIDE_NEGO_ENABLE |
1868 WIDE_NEGO_DONE);
1869 sc->sc_state = TRM_MSGOUT;
1870 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT;
1871 sc->sc_msgcnt = 1;
1872 bus_space_write_2(iot, ioh,
1873 TRM_SCSI_CONTROL, DO_SETATN);
1874 break;
1875 }
1876 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT)
1877 /* do 16 bits */
1878 sc->sc_msgbuf[3] =
1879 MSG_EXT_WDTR_BUS_16_BIT;
1880 if ((ti->flag & WIDE_NEGO_DONE) == 0) {
1881 ti->flag |= WIDE_NEGO_DONE;
1882 ti->flag &= ~(SYNC_NEGO_DONE |
1883 WIDE_NEGO_ENABLE);
1884 if (sc->sc_msgbuf[3] !=
1885 MSG_EXT_WDTR_BUS_8_BIT)
1886 /* is Wide data xfer */
1887 ti->synctl |= WIDE_SYNC;
1888 trm_update_xfer_mode(sc,
1889 periph->periph_target);
1890 }
1891
1892 sc->sc_state = TRM_MSGOUT;
1893 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
1894 DO_SETATN);
1895 break;
1896
1897 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR &&
1898 sc->sc_msgcnt == 5) {
1899 /*
1900 * is 8bit transfer Extended message :
1901 * =================================
1902 * SYNCHRONOUS DATA TRANSFER REQUEST
1903 * =================================
1904 * byte 0 : Extended message (01h)
1905 * byte 1 : Extended message length (03)
1906 * byte 2 : SYNC DATA TRANSFER code (01h)
1907 * byte 3 : Transfer period factor
1908 * byte 4 : REQ/ACK offset
1909 */
1910 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) {
1911 /* reject_msg */
1912 sc->sc_state = TRM_MSGOUT;
1913 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT;
1914 sc->sc_msgcnt = 1;
1915 bus_space_write_2(iot, ioh,
1916 TRM_SCSI_CONTROL, DO_SETATN);
1917 break;
1918 }
1919
1920 if ((ti->flag & SYNC_NEGO_DONE) == 0) {
1921 ti->flag &=
1922 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING);
1923 ti->flag |= SYNC_NEGO_DONE;
1924 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD)
1925 sc->sc_msgbuf[3] = 0;
1926 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET)
1927 sc->sc_msgbuf[4] =
1928 TRM_MAX_OFFSET;
1929
1930 if (sc->sc_msgbuf[3] == 0 ||
1931 sc->sc_msgbuf[4] == 0) {
1932 /* set async */
1933 ti->synctl = 0;
1934 ti->offset = 0;
1935 } else {
1936 /* set sync */
1937 /* Transfer period factor */
1938 ti->period = sc->sc_msgbuf[3];
1939 /* REQ/ACK offset */
1940 ti->offset = sc->sc_msgbuf[4];
1941 for (index = 0;
1942 index < NPERIOD;
1943 index++)
1944 if (ti->period <=
1945 trm_clock_period[
1946 index])
1947 break;
1948
1949 ti->synctl |= ALT_SYNC | index;
1950 }
1951 /*
1952 * program SCSI control register
1953 */
1954 bus_space_write_1(iot, ioh,
1955 TRM_SCSI_SYNC, ti->synctl);
1956 bus_space_write_1(iot, ioh,
1957 TRM_SCSI_OFFSET, ti->offset);
1958 trm_update_xfer_mode(sc,
1959 periph->periph_target);
1960 }
1961 sc->sc_state = TRM_IDLE;
1962 }
1963 break;
1964 default:
1965 break;
1966 }
1967 }
1968
1969 /* it's important for atn stop */
1970 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1971
1972 /*
1973 * SCSI command
1974 */
1975 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT);
1976 }
1977
1978 static void
trm_msgin_phase1(struct trm_softc * sc)1979 trm_msgin_phase1(struct trm_softc *sc)
1980 {
1981 bus_space_tag_t iot = sc->sc_iot;
1982 bus_space_handle_t ioh = sc->sc_ioh;
1983
1984 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
1985 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1);
1986 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) {
1987 sc->sc_state = TRM_MSGIN;
1988 }
1989
1990 /* it's important for atn stop */
1991 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1992
1993 /*
1994 * SCSI command
1995 */
1996 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN);
1997 }
1998
1999 static void
trm_disconnect(struct trm_softc * sc)2000 trm_disconnect(struct trm_softc *sc)
2001 {
2002 bus_space_tag_t iot = sc->sc_iot;
2003 bus_space_handle_t ioh = sc->sc_ioh;
2004 struct trm_srb *srb;
2005 int s;
2006
2007 s = splbio();
2008
2009 srb = sc->sc_actsrb;
2010 DPRINTF(("trm_disconnect...............\n"));
2011
2012 if (srb == NULL) {
2013 DPRINTF(("trm_disconnect: no active srb\n"));
2014 DELAY(1000); /* 1 msec */
2015
2016 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
2017 DO_CLRFIFO | DO_HWRESELECT);
2018 return;
2019 }
2020 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */
2021 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
2022 DO_CLRFIFO | DO_HWRESELECT);
2023 DELAY(100);
2024
2025 switch (sc->sc_state) {
2026 case TRM_UNEXPECT_RESEL:
2027 sc->sc_state = TRM_IDLE;
2028 break;
2029
2030 case TRM_ABORT_SENT:
2031 goto finish;
2032
2033 case TRM_START:
2034 case TRM_MSGOUT:
2035 {
2036 /* Selection time out - discard all LUNs if empty */
2037 struct scsipi_periph *periph;
2038 struct trm_tinfo *ti;
2039 struct trm_linfo *li;
2040 int lun;
2041
2042 DPRINTF(("selection timeout\n"));
2043
2044 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */
2045
2046 periph = srb->xs->xs_periph;
2047 ti = &sc->sc_tinfo[periph->periph_target];
2048 for (lun = 0; lun < TRM_MAX_LUNS; lun++) {
2049 li = ti->linfo[lun];
2050 if (li != NULL &&
2051 li->untagged == NULL && li->used == 0) {
2052 ti->linfo[lun] = NULL;
2053 free(li, M_DEVBUF);
2054 }
2055 }
2056 }
2057 goto finish;
2058
2059 case TRM_DISCONNECTED:
2060 sc->sc_actsrb = NULL;
2061 sc->sc_state = TRM_IDLE;
2062 goto sched;
2063
2064 case TRM_COMPLETED:
2065 goto finish;
2066 }
2067
2068 out:
2069 splx(s);
2070 return;
2071
2072 finish:
2073 sc->sc_state = TRM_IDLE;
2074 trm_done(sc, srb);
2075 goto out;
2076
2077 sched:
2078 trm_sched(sc);
2079 goto out;
2080 }
2081
2082 static void
trm_reselect(struct trm_softc * sc)2083 trm_reselect(struct trm_softc *sc)
2084 {
2085 bus_space_tag_t iot = sc->sc_iot;
2086 bus_space_handle_t ioh = sc->sc_ioh;
2087 struct trm_tinfo *ti;
2088 struct trm_linfo *li;
2089 int target, lun;
2090
2091 DPRINTF(("trm_reselect.................\n"));
2092
2093 if (sc->sc_actsrb != NULL) {
2094 /* arbitration lost but reselection win */
2095 sc->sc_state = TRM_READY;
2096 target = sc->sc_actsrb->xs->xs_periph->periph_target;
2097 ti = &sc->sc_tinfo[target];
2098 } else {
2099 /* Read Reselected Target Id and LUN */
2100 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID);
2101 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07;
2102 ti = &sc->sc_tinfo[target];
2103 li = ti->linfo[lun];
2104 DPRINTF(("target = %d, lun = %d\n", target, lun));
2105
2106 /*
2107 * Check to see if we are running an un-tagged command.
2108 * Otherwise ack the IDENTIFY and wait for a tag message.
2109 */
2110 if (li != NULL) {
2111 if (li->untagged != NULL && li->busy) {
2112 sc->sc_actsrb = li->untagged;
2113 sc->sc_state = TRM_DATA_XFER;
2114 } else {
2115 sc->resel_target = target;
2116 sc->resel_lun = lun;
2117 /* XXX XXX XXX */
2118 sc->sc_flag |= WAIT_TAGMSG;
2119 }
2120 }
2121
2122 if ((ti->flag & USE_TAG_QUEUING) == 0 &&
2123 sc->sc_actsrb == NULL) {
2124 printf("%s: reselect from target %d lun %d "
2125 "without nexus; sending abort\n",
2126 device_xname(sc->sc_dev), target, lun);
2127 sc->sc_state = TRM_UNEXPECT_RESEL;
2128 sc->sc_msgbuf[0] = MSG_ABORT_TAG;
2129 sc->sc_msgcnt = 1;
2130 bus_space_write_2(iot, ioh,
2131 TRM_SCSI_CONTROL, DO_SETATN);
2132 }
2133 }
2134 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */
2135 /*
2136 * Program HA ID, target ID, period and offset
2137 */
2138 /* target ID */
2139 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target);
2140
2141 /* host ID */
2142 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id);
2143
2144 /* period */
2145 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl);
2146
2147 /* offset */
2148 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset);
2149
2150 /* it's important for atn stop */
2151 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
2152 /*
2153 * SCSI command
2154 */
2155 /* to rls the /ACK signal */
2156 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT);
2157 }
2158
2159 /*
2160 * Complete execution of a SCSI command
2161 * Signal completion to the generic SCSI driver
2162 */
2163 static void
trm_done(struct trm_softc * sc,struct trm_srb * srb)2164 trm_done(struct trm_softc *sc, struct trm_srb *srb)
2165 {
2166 struct scsipi_xfer *xs = srb->xs;
2167
2168 DPRINTF(("trm_done..................\n"));
2169
2170 if (xs == NULL)
2171 return;
2172
2173 if ((xs->xs_control & XS_CTL_POLL) == 0)
2174 callout_stop(&xs->xs_callout);
2175
2176 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) ||
2177 srb->flag & AUTO_REQSENSE) {
2178 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0,
2179 srb->dmap->dm_mapsize,
2180 ((xs->xs_control & XS_CTL_DATA_IN) ||
2181 (srb->flag & AUTO_REQSENSE)) ?
2182 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2183 bus_dmamap_unload(sc->sc_dmat, srb->dmap);
2184 }
2185
2186 /*
2187 * target status
2188 */
2189 xs->status = srb->tastat;
2190
2191 DPRINTF(("xs->status = 0x%02x\n", xs->status));
2192
2193 switch (xs->status) {
2194 case SCSI_OK:
2195 /*
2196 * process initiator status......
2197 * Adapter (initiator) status
2198 */
2199 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) {
2200 printf("%s: over/under run error\n",
2201 device_xname(sc->sc_dev));
2202 srb->tastat = 0;
2203 /* Illegal length (over/under run) */
2204 xs->error = XS_DRIVER_STUFFUP;
2205 } else if ((srb->flag & PARITY_ERROR) != 0) {
2206 printf("%s: parity error\n", device_xname(sc->sc_dev));
2207 /* Driver failed to perform operation */
2208 xs->error = XS_DRIVER_STUFFUP; /* XXX */
2209 } else if ((srb->flag & SRB_TIMEOUT) != 0) {
2210 xs->resid = srb->buflen;
2211 xs->error = XS_TIMEOUT;
2212 } else {
2213 /* No error */
2214 xs->resid = srb->buflen;
2215 srb->hastat = 0;
2216 if (srb->flag & AUTO_REQSENSE) {
2217 /* there is no error, (sense is invalid) */
2218 xs->error = XS_SENSE;
2219 } else {
2220 srb->tastat = 0;
2221 xs->error = XS_NOERROR;
2222 }
2223 }
2224 break;
2225
2226 case SCSI_CHECK:
2227 if ((srb->flag & AUTO_REQSENSE) != 0 ||
2228 trm_request_sense(sc, srb) != 0) {
2229 printf("%s: request sense failed\n",
2230 device_xname(sc->sc_dev));
2231 xs->error = XS_DRIVER_STUFFUP;
2232 break;
2233 }
2234 xs->error = XS_SENSE;
2235 return;
2236
2237 case SCSI_SEL_TIMEOUT:
2238 srb->hastat = H_SEL_TIMEOUT;
2239 srb->tastat = 0;
2240 xs->error = XS_SELTIMEOUT;
2241 break;
2242
2243 case SCSI_QUEUE_FULL:
2244 case SCSI_BUSY:
2245 xs->error = XS_BUSY;
2246 break;
2247
2248 case SCSI_RESV_CONFLICT:
2249 DPRINTF(("%s: target reserved at ", device_xname(sc->sc_dev)));
2250 DPRINTF(("%s %d\n", __FILE__, __LINE__));
2251 xs->error = XS_BUSY;
2252 break;
2253
2254 default:
2255 srb->hastat = 0;
2256 printf("%s: trm_done(): unknown status = %02x\n",
2257 device_xname(sc->sc_dev), xs->status);
2258 xs->error = XS_DRIVER_STUFFUP;
2259 break;
2260 }
2261
2262 trm_dequeue(sc, srb);
2263 if (srb == sc->sc_actsrb) {
2264 sc->sc_actsrb = NULL;
2265 trm_sched(sc);
2266 }
2267
2268 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next);
2269
2270 /* Notify cmd done */
2271 scsipi_done(xs);
2272 }
2273
2274 static int
trm_request_sense(struct trm_softc * sc,struct trm_srb * srb)2275 trm_request_sense(struct trm_softc *sc, struct trm_srb *srb)
2276 {
2277 struct scsipi_xfer *xs;
2278 struct scsipi_periph *periph;
2279 struct trm_tinfo *ti;
2280 struct trm_linfo *li;
2281 struct scsi_request_sense *ss = (struct scsi_request_sense *)srb->cmd;
2282 int error;
2283
2284 DPRINTF(("trm_request_sense...\n"));
2285
2286 xs = srb->xs;
2287 periph = xs->xs_periph;
2288
2289 srb->flag |= AUTO_REQSENSE;
2290
2291 /* Status of initiator/target */
2292 srb->hastat = 0;
2293 srb->tastat = 0;
2294
2295 memset(ss, 0, sizeof(*ss));
2296 ss->opcode = SCSI_REQUEST_SENSE;
2297 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT;
2298 ss->length = sizeof(struct scsi_sense_data);
2299
2300 srb->buflen = sizeof(struct scsi_sense_data);
2301 srb->sgcnt = 1;
2302 srb->sgindex = 0;
2303 srb->cmdlen = sizeof(struct scsi_request_sense);
2304
2305 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap,
2306 &xs->sense.scsi_sense, srb->buflen, NULL,
2307 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) {
2308 return error;
2309 }
2310 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0,
2311 srb->buflen, BUS_DMASYNC_PREREAD);
2312
2313 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr);
2314 srb->sgentry[0].length = htole32(sizeof(struct scsi_sense_data));
2315 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset,
2316 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE);
2317
2318 ti = &sc->sc_tinfo[periph->periph_target];
2319 li = ti->linfo[periph->periph_lun];
2320 if (li->busy > 0)
2321 li->busy = 0;
2322 trm_dequeue(sc, srb);
2323 li->untagged = srb; /* must be executed first to fix C/A */
2324 li->busy = 2;
2325
2326 if (srb == sc->sc_actsrb)
2327 trm_select(sc, srb);
2328 else {
2329 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next);
2330 if (sc->sc_actsrb == NULL)
2331 trm_sched(sc);
2332 }
2333 return 0;
2334 }
2335
2336 static void
trm_dequeue(struct trm_softc * sc,struct trm_srb * srb)2337 trm_dequeue(struct trm_softc *sc, struct trm_srb *srb)
2338 {
2339 struct scsipi_periph *periph;
2340 struct trm_tinfo *ti;
2341 struct trm_linfo *li;
2342
2343 periph = srb->xs->xs_periph;
2344 ti = &sc->sc_tinfo[periph->periph_target];
2345 li = ti->linfo[periph->periph_lun];
2346
2347 if (li->untagged == srb) {
2348 li->busy = 0;
2349 li->untagged = NULL;
2350 }
2351 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) {
2352 li->queued[srb->tag[1]] = NULL;
2353 li->used--;
2354 }
2355 }
2356
2357 static void
trm_reset_scsi_bus(struct trm_softc * sc)2358 trm_reset_scsi_bus(struct trm_softc *sc)
2359 {
2360 bus_space_tag_t iot = sc->sc_iot;
2361 bus_space_handle_t ioh = sc->sc_ioh;
2362 int timeout, s;
2363
2364 DPRINTF(("trm_reset_scsi_bus.........\n"));
2365
2366 s = splbio();
2367
2368 sc->sc_flag |= RESET_DEV;
2369 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI);
2370 for (timeout = 20000; timeout >= 0; timeout--) {
2371 DELAY(1);
2372 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) &
2373 INT_SCSIRESET) == 0)
2374 break;
2375 }
2376 if (timeout == 0)
2377 printf(": scsibus reset timeout\n");
2378
2379 splx(s);
2380 }
2381
2382 static void
trm_scsi_reset_detect(struct trm_softc * sc)2383 trm_scsi_reset_detect(struct trm_softc *sc)
2384 {
2385 bus_space_tag_t iot = sc->sc_iot;
2386 bus_space_handle_t ioh = sc->sc_ioh;
2387 int s;
2388
2389 DPRINTF(("trm_scsi_reset_detect...............\n"));
2390 DELAY(1000000); /* delay 1 sec */
2391
2392 s = splbio();
2393
2394 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER);
2395 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
2396
2397 if (sc->sc_flag & RESET_DEV) {
2398 sc->sc_flag |= RESET_DONE;
2399 } else {
2400 sc->sc_flag |= RESET_DETECT;
2401 sc->sc_actsrb = NULL;
2402 sc->sc_flag = 0;
2403 trm_sched(sc);
2404 }
2405 splx(s);
2406 }
2407
2408 /*
2409 * read seeprom 128 bytes to struct eeprom and check checksum.
2410 * If it is wrong, update with default value.
2411 */
2412 static void
trm_check_eeprom(struct trm_softc * sc,struct trm_nvram * eeprom)2413 trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom)
2414 {
2415 struct nvram_target *target;
2416 uint16_t *ep;
2417 uint16_t chksum;
2418 int i;
2419
2420 DPRINTF(("trm_check_eeprom......\n"));
2421 trm_eeprom_read_all(sc, eeprom);
2422 ep = (uint16_t *)eeprom;
2423 chksum = 0;
2424 for (i = 0; i < 64; i++)
2425 chksum += le16toh(*ep++);
2426
2427 if (chksum != TRM_NVRAM_CKSUM) {
2428 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n"));
2429 /*
2430 * Checksum error, load default
2431 */
2432 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF;
2433 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8;
2434 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF;
2435 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8;
2436 eeprom->subclass = 0x00;
2437 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF;
2438 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8;
2439 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF;
2440 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8;
2441 eeprom->reserved0 = 0x00;
2442
2443 for (i = 0, target = eeprom->target;
2444 i < TRM_MAX_TARGETS;
2445 i++, target++) {
2446 target->config0 = 0x77;
2447 target->period = 0x00;
2448 target->config2 = 0x00;
2449 target->config3 = 0x00;
2450 }
2451
2452 eeprom->scsi_id = 7;
2453 eeprom->channel_cfg = 0x0F;
2454 eeprom->delay_time = 0;
2455 eeprom->max_tag = 4;
2456 eeprom->reserved1 = 0x15;
2457 eeprom->boot_target = 0;
2458 eeprom->boot_lun = 0;
2459 eeprom->reserved2 = 0;
2460 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3));
2461
2462 chksum = 0;
2463 ep = (uint16_t *)eeprom;
2464 for (i = 0; i < 63; i++)
2465 chksum += le16toh(*ep++);
2466
2467 chksum = TRM_NVRAM_CKSUM - chksum;
2468 eeprom->checksum0 = chksum & 0xFF;
2469 eeprom->checksum1 = chksum >> 8;
2470
2471 trm_eeprom_write_all(sc, eeprom);
2472 }
2473 }
2474
2475 /*
2476 * write struct eeprom 128 bytes to seeprom
2477 */
2478 static void
trm_eeprom_write_all(struct trm_softc * sc,struct trm_nvram * eeprom)2479 trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom)
2480 {
2481 bus_space_tag_t iot = sc->sc_iot;
2482 bus_space_handle_t ioh = sc->sc_ioh;
2483 uint8_t *sbuf = (uint8_t *)eeprom;
2484 uint8_t addr;
2485
2486 /* Enable SEEPROM */
2487 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL,
2488 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM);
2489
2490 /*
2491 * Write enable
2492 */
2493 trm_eeprom_write_cmd(sc, 0x04, 0xFF);
2494 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0);
2495 trm_eeprom_wait();
2496
2497 for (addr = 0; addr < 128; addr++, sbuf++)
2498 trm_eeprom_set_data(sc, addr, *sbuf);
2499
2500 /*
2501 * Write disable
2502 */
2503 trm_eeprom_write_cmd(sc, 0x04, 0x00);
2504 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0);
2505 trm_eeprom_wait();
2506
2507 /* Disable SEEPROM */
2508 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL,
2509 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM);
2510 }
2511
2512 /*
2513 * write one byte to seeprom
2514 */
2515 static void
trm_eeprom_set_data(struct trm_softc * sc,uint8_t addr,uint8_t data)2516 trm_eeprom_set_data(struct trm_softc *sc, uint8_t addr, uint8_t data)
2517 {
2518 bus_space_tag_t iot = sc->sc_iot;
2519 bus_space_handle_t ioh = sc->sc_ioh;
2520 int i;
2521 uint8_t send;
2522
2523 /*
2524 * Send write command & address
2525 */
2526 trm_eeprom_write_cmd(sc, 0x05, addr);
2527 /*
2528 * Write data
2529 */
2530 for (i = 0; i < 8; i++, data <<= 1) {
2531 send = NVR_SELECT;
2532 if (data & 0x80) /* Start from bit 7 */
2533 send |= NVR_BITOUT;
2534
2535 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send);
2536 trm_eeprom_wait();
2537 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK);
2538 trm_eeprom_wait();
2539 }
2540 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT);
2541 trm_eeprom_wait();
2542 /*
2543 * Disable chip select
2544 */
2545 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0);
2546 trm_eeprom_wait();
2547 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT);
2548 trm_eeprom_wait();
2549 /*
2550 * Wait for write ready
2551 */
2552 for (;;) {
2553 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM,
2554 NVR_SELECT | NVR_CLOCK);
2555 trm_eeprom_wait();
2556 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT);
2557 trm_eeprom_wait();
2558 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN)
2559 break;
2560 }
2561 /*
2562 * Disable chip select
2563 */
2564 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0);
2565 }
2566
2567 /*
2568 * read seeprom 128 bytes to struct eeprom
2569 */
2570 static void
trm_eeprom_read_all(struct trm_softc * sc,struct trm_nvram * eeprom)2571 trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom)
2572 {
2573 bus_space_tag_t iot = sc->sc_iot;
2574 bus_space_handle_t ioh = sc->sc_ioh;
2575 uint8_t *sbuf = (uint8_t *)eeprom;
2576 uint8_t addr;
2577
2578 /*
2579 * Enable SEEPROM
2580 */
2581 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL,
2582 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM);
2583
2584 for (addr = 0; addr < 128; addr++)
2585 *sbuf++ = trm_eeprom_get_data(sc, addr);
2586
2587 /*
2588 * Disable SEEPROM
2589 */
2590 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL,
2591 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM);
2592 }
2593
2594 /*
2595 * read one byte from seeprom
2596 */
2597 static uint8_t
trm_eeprom_get_data(struct trm_softc * sc,uint8_t addr)2598 trm_eeprom_get_data(struct trm_softc *sc, uint8_t addr)
2599 {
2600 bus_space_tag_t iot = sc->sc_iot;
2601 bus_space_handle_t ioh = sc->sc_ioh;
2602 int i;
2603 uint8_t read, data = 0;
2604
2605 /*
2606 * Send read command & address
2607 */
2608 trm_eeprom_write_cmd(sc, 0x06, addr);
2609
2610 for (i = 0; i < 8; i++) { /* Read data */
2611 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM,
2612 NVR_SELECT | NVR_CLOCK);
2613 trm_eeprom_wait();
2614 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT);
2615 /*
2616 * Get data bit while falling edge
2617 */
2618 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM);
2619 data <<= 1;
2620 if (read & NVR_BITIN)
2621 data |= 1;
2622
2623 trm_eeprom_wait();
2624 }
2625 /*
2626 * Disable chip select
2627 */
2628 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0);
2629 return data;
2630 }
2631
2632 /*
2633 * write SB and Op Code into seeprom
2634 */
2635 static void
trm_eeprom_write_cmd(struct trm_softc * sc,uint8_t cmd,uint8_t addr)2636 trm_eeprom_write_cmd(struct trm_softc *sc, uint8_t cmd, uint8_t addr)
2637 {
2638 bus_space_tag_t iot = sc->sc_iot;
2639 bus_space_handle_t ioh = sc->sc_ioh;
2640 int i;
2641 uint8_t send;
2642
2643 /* Program SB+OP code */
2644 for (i = 0; i < 3; i++, cmd <<= 1) {
2645 send = NVR_SELECT;
2646 if (cmd & 0x04) /* Start from bit 2 */
2647 send |= NVR_BITOUT;
2648
2649 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send);
2650 trm_eeprom_wait();
2651 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK);
2652 trm_eeprom_wait();
2653 }
2654
2655 /* Program address */
2656 for (i = 0; i < 7; i++, addr <<= 1) {
2657 send = NVR_SELECT;
2658 if (addr & 0x40) /* Start from bit 6 */
2659 send |= NVR_BITOUT;
2660
2661 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send);
2662 trm_eeprom_wait();
2663 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK);
2664 trm_eeprom_wait();
2665 }
2666 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT);
2667 trm_eeprom_wait();
2668 }
2669