1 /*-
2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * This driver exists largely as a result of other people's efforts.
29 * Much of register handling is based on NetBSD CMI8x38 audio driver
30 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
31 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
32 * registers and the 8738 mixer devices. His Linux driver was also a
33 * useful reference point.
34 *
35 * TODO: MIDI
36 *
37 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
38 *
39 * This card/code does not always manage to sample at 44100 - actual
40 * rate drifts slightly between recordings (usually 0-3%). No
41 * differences visible in register dumps between times that work and
42 * those that don't.
43 */
44
45 #ifdef HAVE_KERNEL_OPTION_HEADERS
46 #include "opt_snd.h"
47 #endif
48
49 #include <dev/sound/pcm/sound.h>
50 #include <dev/sound/pci/cmireg.h>
51 #include <dev/sound/pci/sb.h>
52
53 #include <bus/pci/pcireg.h>
54 #include <bus/pci/pcivar.h>
55
56 #include <sys/sysctl.h>
57 #include <dev/sound/midi/mpu401.h>
58
59 #include "mixer_if.h"
60 #include "mpufoi_if.h"
61
62 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/cmi.c 254263 2013-08-12 23:30:01Z scottl $");
63
64 /* Supported chip ID's */
65 #define CMI8338A_PCI_ID 0x010013f6
66 #define CMI8338B_PCI_ID 0x010113f6
67 #define CMI8738_PCI_ID 0x011113f6
68 #define CMI8738B_PCI_ID 0x011213f6
69 #define CMI120_USB_ID 0x01030d8c
70
71 /* Buffer size max is 64k for permitted DMA boundaries */
72 #define CMI_DEFAULT_BUFSZ 16384
73
74 /* Interrupts per length of buffer */
75 #define CMI_INTR_PER_BUFFER 2
76
77 /* Clarify meaning of named defines in cmireg.h */
78 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
79 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
80 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
81 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
82
83 /* Our indication of custom mixer control */
84 #define CMPCI_NON_SB16_CONTROL 0xff
85
86 /* Debugging macro's */
87 #undef DEB
88 #ifndef DEB
89 #define DEB(x) /* x */
90 #endif /* DEB */
91
92 #ifndef DEBMIX
93 #define DEBMIX(x) /* x */
94 #endif /* DEBMIX */
95
96 /* ------------------------------------------------------------------------- */
97 /* Structures */
98
99 struct sc_info;
100
101 struct sc_chinfo {
102 struct sc_info *parent;
103 struct pcm_channel *channel;
104 struct snd_dbuf *buffer;
105 u_int32_t fmt, spd, phys_buf, bps;
106 u_int32_t dma_active:1, dma_was_active:1;
107 int dir;
108 };
109
110 struct sc_info {
111 device_t dev;
112
113 bus_space_tag_t st;
114 bus_space_handle_t sh;
115 bus_dma_tag_t parent_dmat;
116 struct resource *reg, *irq;
117 int regid, irqid;
118 void *ih;
119 struct lock *lock;
120
121 int spdif_enabled;
122 unsigned int bufsz;
123 struct sc_chinfo pch, rch;
124
125 struct mpu401 *mpu;
126 mpu401_intr_t *mpu_intr;
127 struct resource *mpu_reg;
128 int mpu_regid;
129 bus_space_tag_t mpu_bt;
130 bus_space_handle_t mpu_bh;
131 };
132
133 /* Channel caps */
134
135 static u_int32_t cmi_fmt[] = {
136 SND_FORMAT(AFMT_U8, 1, 0),
137 SND_FORMAT(AFMT_U8, 2, 0),
138 SND_FORMAT(AFMT_S16_LE, 1, 0),
139 SND_FORMAT(AFMT_S16_LE, 2, 0),
140 0
141 };
142
143 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
144
145 /* ------------------------------------------------------------------------- */
146 /* Register Utilities */
147
148 static u_int32_t
cmi_rd(struct sc_info * sc,int regno,int size)149 cmi_rd(struct sc_info *sc, int regno, int size)
150 {
151 switch (size) {
152 case 1:
153 return bus_space_read_1(sc->st, sc->sh, regno);
154 case 2:
155 return bus_space_read_2(sc->st, sc->sh, regno);
156 case 4:
157 return bus_space_read_4(sc->st, sc->sh, regno);
158 default:
159 DEB(kprintf("cmi_rd: failed 0x%04x %d\n", regno, size));
160 return 0xFFFFFFFF;
161 }
162 }
163
164 static void
cmi_wr(struct sc_info * sc,int regno,u_int32_t data,int size)165 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
166 {
167 switch (size) {
168 case 1:
169 bus_space_write_1(sc->st, sc->sh, regno, data);
170 break;
171 case 2:
172 bus_space_write_2(sc->st, sc->sh, regno, data);
173 break;
174 case 4:
175 bus_space_write_4(sc->st, sc->sh, regno, data);
176 break;
177 }
178 }
179
180 static void
cmi_partial_wr4(struct sc_info * sc,int reg,int shift,u_int32_t mask,u_int32_t val)181 cmi_partial_wr4(struct sc_info *sc,
182 int reg, int shift, u_int32_t mask, u_int32_t val)
183 {
184 u_int32_t r;
185
186 r = cmi_rd(sc, reg, 4);
187 r &= ~(mask << shift);
188 r |= val << shift;
189 cmi_wr(sc, reg, r, 4);
190 }
191
192 static void
cmi_clr4(struct sc_info * sc,int reg,u_int32_t mask)193 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
194 {
195 u_int32_t r;
196
197 r = cmi_rd(sc, reg, 4);
198 r &= ~mask;
199 cmi_wr(sc, reg, r, 4);
200 }
201
202 static void
cmi_set4(struct sc_info * sc,int reg,u_int32_t mask)203 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
204 {
205 u_int32_t r;
206
207 r = cmi_rd(sc, reg, 4);
208 r |= mask;
209 cmi_wr(sc, reg, r, 4);
210 }
211
212 /* ------------------------------------------------------------------------- */
213 /* Rate Mapping */
214
215 static int cmi_rates[] = {5512, 8000, 11025, 16000,
216 22050, 32000, 44100, 48000};
217 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
218
219 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
220 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
221
222 static u_int32_t
cmpci_rate_to_regvalue(int rate)223 cmpci_rate_to_regvalue(int rate)
224 {
225 int i, r;
226
227 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
228 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
229 break;
230 }
231 }
232
233 DEB(kprintf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
234
235 r = ((i >> 1) | (i << 2)) & 0x07;
236 return r;
237 }
238
239 static int
cmpci_regvalue_to_rate(u_int32_t r)240 cmpci_regvalue_to_rate(u_int32_t r)
241 {
242 int i;
243
244 i = ((r << 1) | (r >> 2)) & 0x07;
245 DEB(kprintf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
246 return cmi_rates[i];
247 }
248
249 /* ------------------------------------------------------------------------- */
250 /* ADC/DAC control - there are 2 dma channels on 8738, either can be
251 * playback or capture. We use ch0 for playback and ch1 for capture. */
252
253 static void
cmi_dma_prog(struct sc_info * sc,struct sc_chinfo * ch,u_int32_t base)254 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
255 {
256 u_int32_t s, i, sz;
257
258 ch->phys_buf = sndbuf_getbufaddr(ch->buffer);
259
260 cmi_wr(sc, base, ch->phys_buf, 4);
261 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
262
263 s = sz / ch->bps - 1;
264 cmi_wr(sc, base + 4, s, 2);
265
266 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
267 cmi_wr(sc, base + 6, i, 2);
268 }
269
270
271 static void
cmi_ch0_start(struct sc_info * sc,struct sc_chinfo * ch)272 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
273 {
274 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
275
276 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
277 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
278 CMPCI_REG_CH0_INTR_ENABLE);
279
280 ch->dma_active = 1;
281 }
282
283 static u_int32_t
cmi_ch0_stop(struct sc_info * sc,struct sc_chinfo * ch)284 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
285 {
286 u_int32_t r = ch->dma_active;
287
288 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
289 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
290 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
291 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
292 ch->dma_active = 0;
293 return r;
294 }
295
296 static void
cmi_ch1_start(struct sc_info * sc,struct sc_chinfo * ch)297 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
298 {
299 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
300 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
301 /* Enable Interrupts */
302 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
303 CMPCI_REG_CH1_INTR_ENABLE);
304 DEB(kprintf("cmi_ch1_start: dma prog\n"));
305 ch->dma_active = 1;
306 }
307
308 static u_int32_t
cmi_ch1_stop(struct sc_info * sc,struct sc_chinfo * ch)309 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
310 {
311 u_int32_t r = ch->dma_active;
312
313 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
314 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
315 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
316 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
317 ch->dma_active = 0;
318 return r;
319 }
320
321 static void
cmi_spdif_speed(struct sc_info * sc,int speed)322 cmi_spdif_speed(struct sc_info *sc, int speed) {
323 u_int32_t fcr1, lcr, mcr;
324
325 if (speed >= 44100) {
326 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
327 lcr = CMPCI_REG_XSPDIF_ENABLE;
328 mcr = (speed == 48000) ?
329 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
330 } else {
331 fcr1 = mcr = lcr = 0;
332 }
333
334 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
335 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
336 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
337 CMPCI_REG_SPDIF0_ENABLE, fcr1);
338 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
339 CMPCI_REG_XSPDIF_ENABLE, lcr);
340 }
341
342 /* ------------------------------------------------------------------------- */
343 /* Channel Interface implementation */
344
345 static void *
cmichan_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)346 cmichan_init(kobj_t obj, void *devinfo,
347 struct snd_dbuf *b, struct pcm_channel *c, int dir)
348 {
349 struct sc_info *sc = devinfo;
350 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
351
352 ch->parent = sc;
353 ch->channel = c;
354 ch->bps = 1;
355 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
356 ch->spd = DSP_DEFAULT_SPEED;
357 ch->buffer = b;
358 ch->dma_active = 0;
359 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
360 DEB(kprintf("cmichan_init failed\n"));
361 return NULL;
362 }
363
364 ch->dir = dir;
365 snd_mtxlock(sc->lock);
366 if (ch->dir == PCMDIR_PLAY) {
367 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
368 } else {
369 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
370 }
371 snd_mtxunlock(sc->lock);
372
373 return ch;
374 }
375
376 static int
cmichan_setformat(kobj_t obj,void * data,u_int32_t format)377 cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
378 {
379 struct sc_chinfo *ch = data;
380 struct sc_info *sc = ch->parent;
381 u_int32_t f;
382
383 if (format & AFMT_S16_LE) {
384 f = CMPCI_REG_FORMAT_16BIT;
385 ch->bps = 2;
386 } else {
387 f = CMPCI_REG_FORMAT_8BIT;
388 ch->bps = 1;
389 }
390
391 if (AFMT_CHANNEL(format) > 1) {
392 f |= CMPCI_REG_FORMAT_STEREO;
393 ch->bps *= 2;
394 } else {
395 f |= CMPCI_REG_FORMAT_MONO;
396 }
397
398 snd_mtxlock(sc->lock);
399 if (ch->dir == PCMDIR_PLAY) {
400 cmi_partial_wr4(ch->parent,
401 CMPCI_REG_CHANNEL_FORMAT,
402 CMPCI_REG_CH0_FORMAT_SHIFT,
403 CMPCI_REG_CH0_FORMAT_MASK,
404 f);
405 } else {
406 cmi_partial_wr4(ch->parent,
407 CMPCI_REG_CHANNEL_FORMAT,
408 CMPCI_REG_CH1_FORMAT_SHIFT,
409 CMPCI_REG_CH1_FORMAT_MASK,
410 f);
411 }
412 snd_mtxunlock(sc->lock);
413 ch->fmt = format;
414
415 return 0;
416 }
417
418 static u_int32_t
cmichan_setspeed(kobj_t obj,void * data,u_int32_t speed)419 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
420 {
421 struct sc_chinfo *ch = data;
422 struct sc_info *sc = ch->parent;
423 u_int32_t r, rsp;
424
425 r = cmpci_rate_to_regvalue(speed);
426 snd_mtxlock(sc->lock);
427 if (ch->dir == PCMDIR_PLAY) {
428 if (speed < 44100) {
429 /* disable if req before rate change */
430 cmi_spdif_speed(ch->parent, speed);
431 }
432 cmi_partial_wr4(ch->parent,
433 CMPCI_REG_FUNC_1,
434 CMPCI_REG_DAC_FS_SHIFT,
435 CMPCI_REG_DAC_FS_MASK,
436 r);
437 if (speed >= 44100 && ch->parent->spdif_enabled) {
438 /* enable if req after rate change */
439 cmi_spdif_speed(ch->parent, speed);
440 }
441 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
442 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
443 rsp &= CMPCI_REG_DAC_FS_MASK;
444 } else {
445 cmi_partial_wr4(ch->parent,
446 CMPCI_REG_FUNC_1,
447 CMPCI_REG_ADC_FS_SHIFT,
448 CMPCI_REG_ADC_FS_MASK,
449 r);
450 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
451 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
452 rsp &= CMPCI_REG_ADC_FS_MASK;
453 }
454 snd_mtxunlock(sc->lock);
455 ch->spd = cmpci_regvalue_to_rate(r);
456
457 DEB(kprintf("cmichan_setspeed (%s) %d -> %d (%d)\n",
458 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
459 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
460
461 return ch->spd;
462 }
463
464 static u_int32_t
cmichan_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)465 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
466 {
467 struct sc_chinfo *ch = data;
468 struct sc_info *sc = ch->parent;
469
470 /* user has requested interrupts every blocksize bytes */
471 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) {
472 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER;
473 }
474 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
475
476 return blocksize;
477 }
478
479 static int
cmichan_trigger(kobj_t obj,void * data,int go)480 cmichan_trigger(kobj_t obj, void *data, int go)
481 {
482 struct sc_chinfo *ch = data;
483 struct sc_info *sc = ch->parent;
484
485 if (!PCMTRIG_COMMON(go))
486 return 0;
487
488 snd_mtxlock(sc->lock);
489 if (ch->dir == PCMDIR_PLAY) {
490 switch(go) {
491 case PCMTRIG_START:
492 cmi_ch0_start(sc, ch);
493 break;
494 case PCMTRIG_STOP:
495 case PCMTRIG_ABORT:
496 cmi_ch0_stop(sc, ch);
497 break;
498 }
499 } else {
500 switch(go) {
501 case PCMTRIG_START:
502 cmi_ch1_start(sc, ch);
503 break;
504 case PCMTRIG_STOP:
505 case PCMTRIG_ABORT:
506 cmi_ch1_stop(sc, ch);
507 break;
508 }
509 }
510 snd_mtxunlock(sc->lock);
511 return 0;
512 }
513
514 static u_int32_t
cmichan_getptr(kobj_t obj,void * data)515 cmichan_getptr(kobj_t obj, void *data)
516 {
517 struct sc_chinfo *ch = data;
518 struct sc_info *sc = ch->parent;
519 u_int32_t physptr, bufptr, sz;
520
521 snd_mtxlock(sc->lock);
522 if (ch->dir == PCMDIR_PLAY) {
523 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
524 } else {
525 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
526 }
527 snd_mtxunlock(sc->lock);
528
529 sz = sndbuf_getsize(ch->buffer);
530 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
531
532 return bufptr;
533 }
534
535 static void
cmi_intr(void * data)536 cmi_intr(void *data)
537 {
538 struct sc_info *sc = data;
539 u_int32_t intrstat;
540 u_int32_t toclear;
541
542 snd_mtxlock(sc->lock);
543 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
544 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) {
545
546 toclear = 0;
547 if (intrstat & CMPCI_REG_CH0_INTR) {
548 toclear |= CMPCI_REG_CH0_INTR_ENABLE;
549 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
550 }
551
552 if (intrstat & CMPCI_REG_CH1_INTR) {
553 toclear |= CMPCI_REG_CH1_INTR_ENABLE;
554 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
555 }
556
557 if (toclear) {
558 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear);
559 snd_mtxunlock(sc->lock);
560
561 /* Signal interrupts to channel */
562 if (intrstat & CMPCI_REG_CH0_INTR) {
563 chn_intr(sc->pch.channel);
564 }
565
566 if (intrstat & CMPCI_REG_CH1_INTR) {
567 chn_intr(sc->rch.channel);
568 }
569
570 snd_mtxlock(sc->lock);
571 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear);
572
573 }
574 }
575 if(sc->mpu_intr) {
576 (sc->mpu_intr)(sc->mpu);
577 }
578 snd_mtxunlock(sc->lock);
579 return;
580 }
581
582 static struct pcmchan_caps *
cmichan_getcaps(kobj_t obj,void * data)583 cmichan_getcaps(kobj_t obj, void *data)
584 {
585 return &cmi_caps;
586 }
587
588 static kobj_method_t cmichan_methods[] = {
589 KOBJMETHOD(channel_init, cmichan_init),
590 KOBJMETHOD(channel_setformat, cmichan_setformat),
591 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
592 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
593 KOBJMETHOD(channel_trigger, cmichan_trigger),
594 KOBJMETHOD(channel_getptr, cmichan_getptr),
595 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
596 KOBJMETHOD_END
597 };
598 CHANNEL_DECLARE(cmichan);
599
600 /* ------------------------------------------------------------------------- */
601 /* Mixer - sb16 with kinks */
602
603 static void
cmimix_wr(struct sc_info * sc,u_int8_t port,u_int8_t val)604 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
605 {
606 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
607 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
608 }
609
610 static u_int8_t
cmimix_rd(struct sc_info * sc,u_int8_t port)611 cmimix_rd(struct sc_info *sc, u_int8_t port)
612 {
613 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
614 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
615 }
616
617 struct sb16props {
618 u_int8_t rreg; /* right reg chan register */
619 u_int8_t stereo:1; /* (no explanation needed, honest) */
620 u_int8_t rec:1; /* recording source */
621 u_int8_t bits:3; /* num bits to represent maximum gain rep */
622 u_int8_t oselect; /* output select mask */
623 u_int8_t iselect; /* right input select mask */
624 };
625
626 static const struct sb16props cmt[SOUND_MIXER_NRDEVICES] = {
627 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
628 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
629 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
630 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
631 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
632 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
633 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
634 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
635 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
636 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
637 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
638 /* These controls are not implemented in CMI8738, but maybe at a
639 future date. They are not documented in C-Media documentation,
640 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
641 */
642 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
643 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
644 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
645 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
646 /* The mic pre-amp is implemented with non-SB16 compatible
647 registers. */
648 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
649 };
650
651 #define MIXER_GAIN_REG_RTOL(r) (r - 1)
652
653 static int
cmimix_init(struct snd_mixer * m)654 cmimix_init(struct snd_mixer *m)
655 {
656 struct sc_info *sc = mix_getdevinfo(m);
657 u_int32_t i,v;
658
659 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
660 if (cmt[i].bits) v |= 1 << i;
661 }
662 mix_setdevs(m, v);
663
664 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
665 if (cmt[i].rec) v |= 1 << i;
666 }
667 mix_setrecdevs(m, v);
668
669 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
670 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
671 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
672 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
673 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
674 return 0;
675 }
676
677 static int
cmimix_set(struct snd_mixer * m,unsigned dev,unsigned left,unsigned right)678 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
679 {
680 struct sc_info *sc = mix_getdevinfo(m);
681 u_int32_t r, l, max;
682 u_int8_t v;
683
684 max = (1 << cmt[dev].bits) - 1;
685
686 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
687 /* For time being this can only be one thing (mic in
688 * mic/aux reg) */
689 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
690 l = left * max / 100;
691 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
692 v |= ((l << 1) | (~l >> 3)) & 0x0f;
693 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
694 return 0;
695 }
696
697 l = (left * max / 100) << (8 - cmt[dev].bits);
698 if (cmt[dev].stereo) {
699 r = (right * max / 100) << (8 - cmt[dev].bits);
700 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
701 cmimix_wr(sc, cmt[dev].rreg, r);
702 DEBMIX(kprintf("Mixer stereo write dev %d reg 0x%02x "\
703 "value 0x%02x:0x%02x\n",
704 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
705 } else {
706 r = l;
707 cmimix_wr(sc, cmt[dev].rreg, l);
708 DEBMIX(kprintf("Mixer mono write dev %d reg 0x%02x " \
709 "value 0x%02x:0x%02x\n",
710 dev, cmt[dev].rreg, l, l));
711 }
712
713 /* Zero gain does not mute channel from output, but this does... */
714 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
715 if (l == 0 && r == 0) {
716 v &= ~cmt[dev].oselect;
717 } else {
718 v |= cmt[dev].oselect;
719 }
720 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
721
722 return 0;
723 }
724
725 static u_int32_t
cmimix_setrecsrc(struct snd_mixer * m,u_int32_t src)726 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
727 {
728 struct sc_info *sc = mix_getdevinfo(m);
729 u_int32_t i, ml, sl;
730
731 ml = sl = 0;
732 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
733 if ((1<<i) & src) {
734 if (cmt[i].stereo) {
735 sl |= cmt[i].iselect;
736 } else {
737 ml |= cmt[i].iselect;
738 }
739 }
740 }
741 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
742 DEBMIX(kprintf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
743 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
744 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
745 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
746 DEBMIX(kprintf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
747 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
748
749 return src;
750 }
751
752 /* Optional SPDIF support. */
753
754 static int
cmi_initsys(struct sc_info * sc)755 cmi_initsys(struct sc_info* sc)
756 {
757 /* XXX: an user should be able to set this with a control tool,
758 if not done before 7.0-RELEASE, this needs to be converted
759 to a device specific sysctl "dev.pcm.X.yyy" via
760 device_get_sysctl_*() as discussed on multimedia@ in msg-id
761 <861wujij2q.fsf@xps.des.no> */
762 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
763 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
764 OID_AUTO, "spdif_enabled", CTLFLAG_RW,
765 &sc->spdif_enabled, 0,
766 "enable SPDIF output at 44.1 kHz and above");
767
768 return 0;
769 }
770
771 /* ------------------------------------------------------------------------- */
772 static kobj_method_t cmi_mixer_methods[] = {
773 KOBJMETHOD(mixer_init, cmimix_init),
774 KOBJMETHOD(mixer_set, cmimix_set),
775 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
776 KOBJMETHOD_END
777 };
778 MIXER_DECLARE(cmi_mixer);
779
780 /*
781 * mpu401 functions
782 */
783
784 static unsigned char
cmi_mread(struct mpu401 * arg,void * sc,int reg)785 cmi_mread(struct mpu401 *arg, void *sc, int reg)
786 {
787 unsigned int d;
788
789 d = bus_space_read_1(0,0, 0x330 + reg);
790 /* printf("cmi_mread: reg %x %x\n",reg, d);
791 */
792 return d;
793 }
794
795 static void
cmi_mwrite(struct mpu401 * arg,void * sc,int reg,unsigned char b)796 cmi_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b)
797 {
798
799 bus_space_write_1(0,0,0x330 + reg , b);
800 }
801
802 static int
cmi_muninit(struct mpu401 * arg,void * cookie)803 cmi_muninit(struct mpu401 *arg, void *cookie)
804 {
805 struct sc_info *sc = cookie;
806
807 snd_mtxlock(sc->lock);
808 sc->mpu_intr = 0;
809 sc->mpu = 0;
810 snd_mtxunlock(sc->lock);
811
812 return 0;
813 }
814
815 static kobj_method_t cmi_mpu_methods[] = {
816 KOBJMETHOD(mpufoi_read, cmi_mread),
817 KOBJMETHOD(mpufoi_write, cmi_mwrite),
818 KOBJMETHOD(mpufoi_uninit, cmi_muninit),
819 KOBJMETHOD_END
820 };
821
822 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0);
823
824 static void
cmi_midiattach(struct sc_info * sc)825 cmi_midiattach(struct sc_info *sc) {
826 /*
827 const struct {
828 int port,bits;
829 } *p, ports[] = {
830 {0x330,0},
831 {0x320,1},
832 {0x310,2},
833 {0x300,3},
834 {0,0} } ;
835 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does
836 anyone know how to bus_space tag?
837 */
838 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
839 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL,
840 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT);
841 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL,
842 0 << CMPCI_REG_VMPUSEL_SHIFT );
843 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
844 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr);
845 }
846
847
848
849 /* ------------------------------------------------------------------------- */
850 /* Power and reset */
851
852 static void
cmi_power(struct sc_info * sc,int state)853 cmi_power(struct sc_info *sc, int state)
854 {
855 switch (state) {
856 case 0: /* full power */
857 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
858 break;
859 default:
860 /* power off */
861 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
862 break;
863 }
864 }
865
866 static int
cmi_init(struct sc_info * sc)867 cmi_init(struct sc_info *sc)
868 {
869 /* Effect reset */
870 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
871 DELAY(100);
872 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
873
874 /* Disable interrupts and channels */
875 cmi_clr4(sc, CMPCI_REG_FUNC_0,
876 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
877 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
878 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
879
880 /* Configure DMA channels, ch0 = play, ch1 = capture */
881 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
882 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
883
884 /* Attempt to enable 4 Channel output */
885 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
886
887 /* Disable SPDIF1 - not compatible with config */
888 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
889 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
890
891 return 0;
892 }
893
894 static void
cmi_uninit(struct sc_info * sc)895 cmi_uninit(struct sc_info *sc)
896 {
897 /* Disable interrupts and channels */
898 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
899 CMPCI_REG_CH0_INTR_ENABLE |
900 CMPCI_REG_CH1_INTR_ENABLE |
901 CMPCI_REG_TDMA_INTR_ENABLE);
902 cmi_clr4(sc, CMPCI_REG_FUNC_0,
903 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
904 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
905
906 if( sc->mpu )
907 sc->mpu_intr = 0;
908 }
909
910 /* ------------------------------------------------------------------------- */
911 /* Bus and device registration */
912 static int
cmi_probe(device_t dev)913 cmi_probe(device_t dev)
914 {
915 switch(pci_get_devid(dev)) {
916 case CMI8338A_PCI_ID:
917 device_set_desc(dev, "CMedia CMI8338A");
918 return BUS_PROBE_DEFAULT;
919 case CMI8338B_PCI_ID:
920 device_set_desc(dev, "CMedia CMI8338B");
921 return BUS_PROBE_DEFAULT;
922 case CMI8738_PCI_ID:
923 device_set_desc(dev, "CMedia CMI8738");
924 return BUS_PROBE_DEFAULT;
925 case CMI8738B_PCI_ID:
926 device_set_desc(dev, "CMedia CMI8738B");
927 return BUS_PROBE_DEFAULT;
928 case CMI120_USB_ID:
929 device_set_desc(dev, "CMedia CMI120");
930 return BUS_PROBE_DEFAULT;
931 default:
932 return ENXIO;
933 }
934 }
935
936 static int
cmi_attach(device_t dev)937 cmi_attach(device_t dev)
938 {
939 struct sc_info *sc;
940 char status[SND_STATUSLEN];
941
942 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
943 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc");
944 pci_enable_busmaster(dev);
945
946 sc->dev = dev;
947 sc->regid = PCIR_BAR(0);
948 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,
949 RF_ACTIVE);
950 if (!sc->reg) {
951 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
952 goto bad;
953 }
954 sc->st = rman_get_bustag(sc->reg);
955 sc->sh = rman_get_bushandle(sc->reg);
956
957 if (0)
958 cmi_midiattach(sc);
959
960 sc->irqid = 0;
961 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
962 RF_ACTIVE | RF_SHAREABLE);
963 if (!sc->irq ||
964 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) {
965 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
966 goto bad;
967 }
968
969 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536);
970
971 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
972 /*boundary*/0,
973 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
974 /*highaddr*/BUS_SPACE_MAXADDR,
975 /*maxsize*/sc->bufsz, /*nsegments*/1,
976 /*maxsegz*/0x3ffff, /*flags*/0,
977 &sc->parent_dmat) != 0) {
978 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
979 goto bad;
980 }
981
982 cmi_power(sc, 0);
983 if (cmi_init(sc))
984 goto bad;
985
986 if (mixer_init(dev, &cmi_mixer_class, sc))
987 goto bad;
988
989 if (pcm_register(dev, sc, 1, 1))
990 goto bad;
991
992 cmi_initsys(sc);
993
994 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
995 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
996
997 ksnprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s",
998 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi));
999 pcm_setstatus(dev, status);
1000
1001 DEB(kprintf("cmi_attach: succeeded\n"));
1002 return 0;
1003
1004 bad:
1005 if (sc->parent_dmat)
1006 bus_dma_tag_destroy(sc->parent_dmat);
1007 if (sc->ih)
1008 bus_teardown_intr(dev, sc->irq, sc->ih);
1009 if (sc->irq)
1010 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1011 if (sc->reg)
1012 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1013 if (sc->lock)
1014 snd_mtxfree(sc->lock);
1015 if (sc)
1016 kfree(sc, M_DEVBUF);
1017
1018 return ENXIO;
1019 }
1020
1021 static int
cmi_detach(device_t dev)1022 cmi_detach(device_t dev)
1023 {
1024 struct sc_info *sc;
1025 int r;
1026
1027 r = pcm_unregister(dev);
1028 if (r) return r;
1029
1030 sc = pcm_getdevinfo(dev);
1031 cmi_uninit(sc);
1032 cmi_power(sc, 3);
1033
1034 bus_dma_tag_destroy(sc->parent_dmat);
1035 bus_teardown_intr(dev, sc->irq, sc->ih);
1036 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1037 if(sc->mpu)
1038 mpu401_uninit(sc->mpu);
1039 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1040 if (sc->mpu_reg)
1041 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg);
1042
1043 snd_mtxfree(sc->lock);
1044 kfree(sc, M_DEVBUF);
1045
1046 return 0;
1047 }
1048
1049 static int
cmi_suspend(device_t dev)1050 cmi_suspend(device_t dev)
1051 {
1052 struct sc_info *sc = pcm_getdevinfo(dev);
1053
1054 snd_mtxlock(sc->lock);
1055 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
1056 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
1057 cmi_power(sc, 3);
1058 snd_mtxunlock(sc->lock);
1059 return 0;
1060 }
1061
1062 static int
cmi_resume(device_t dev)1063 cmi_resume(device_t dev)
1064 {
1065 struct sc_info *sc = pcm_getdevinfo(dev);
1066
1067 snd_mtxlock(sc->lock);
1068 cmi_power(sc, 0);
1069 if (cmi_init(sc) != 0) {
1070 device_printf(dev, "unable to reinitialize the card\n");
1071 snd_mtxunlock(sc->lock);
1072 return ENXIO;
1073 }
1074
1075 if (mixer_reinit(dev) == -1) {
1076 device_printf(dev, "unable to reinitialize the mixer\n");
1077 snd_mtxunlock(sc->lock);
1078 return ENXIO;
1079 }
1080
1081 if (sc->pch.dma_was_active) {
1082 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
1083 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
1084 cmi_ch0_start(sc, &sc->pch);
1085 }
1086
1087 if (sc->rch.dma_was_active) {
1088 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
1089 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
1090 cmi_ch1_start(sc, &sc->rch);
1091 }
1092 snd_mtxunlock(sc->lock);
1093 return 0;
1094 }
1095
1096 static device_method_t cmi_methods[] = {
1097 DEVMETHOD(device_probe, cmi_probe),
1098 DEVMETHOD(device_attach, cmi_attach),
1099 DEVMETHOD(device_detach, cmi_detach),
1100 DEVMETHOD(device_resume, cmi_resume),
1101 DEVMETHOD(device_suspend, cmi_suspend),
1102 { 0, 0 }
1103 };
1104
1105 static driver_t cmi_driver = {
1106 "pcm",
1107 cmi_methods,
1108 PCM_SOFTC_SIZE
1109 };
1110
1111 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, NULL, NULL);
1112 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1113 MODULE_DEPEND(snd_cmi, midi, 1,1,1);
1114 MODULE_VERSION(snd_cmi, 1);
1115