1 /*	$NetBSD: intel_bios.h,v 1.2 2021/12/18 23:45:29 riastradh Exp $	*/
2 
3 /*
4  * Copyright © 2016-2019 Intel Corporation
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23  * SOFTWARE.
24  */
25 
26 /*
27  * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away
28  * the VBT from the rest of the driver. Add the parsed, clean data to struct
29  * intel_vbt_data within struct drm_i915_private.
30  */
31 
32 #ifndef _INTEL_BIOS_H_
33 #define _INTEL_BIOS_H_
34 
35 #include <linux/types.h>
36 
37 #include <drm/i915_drm.h>
38 
39 struct drm_i915_private;
40 struct intel_crtc_state;
41 struct intel_encoder;
42 enum port;
43 
44 enum intel_backlight_type {
45 	INTEL_BACKLIGHT_PMIC,
46 	INTEL_BACKLIGHT_LPSS,
47 	INTEL_BACKLIGHT_DISPLAY_DDI,
48 	INTEL_BACKLIGHT_DSI_DCS,
49 	INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE,
50 	INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE,
51 };
52 
53 struct edp_power_seq {
54 	u16 t1_t3;
55 	u16 t8;
56 	u16 t9;
57 	u16 t10;
58 	u16 t11_t12;
59 } __packed;
60 
61 /*
62  * MIPI Sequence Block definitions
63  *
64  * Note the VBT spec has AssertReset / DeassertReset swapped from their
65  * usual naming, we use the proper names here to avoid confusion when
66  * reading the code.
67  */
68 enum mipi_seq {
69 	MIPI_SEQ_END = 0,
70 	MIPI_SEQ_DEASSERT_RESET,	/* Spec says MipiAssertResetPin */
71 	MIPI_SEQ_INIT_OTP,
72 	MIPI_SEQ_DISPLAY_ON,
73 	MIPI_SEQ_DISPLAY_OFF,
74 	MIPI_SEQ_ASSERT_RESET,		/* Spec says MipiDeassertResetPin */
75 	MIPI_SEQ_BACKLIGHT_ON,		/* sequence block v2+ */
76 	MIPI_SEQ_BACKLIGHT_OFF,		/* sequence block v2+ */
77 	MIPI_SEQ_TEAR_ON,		/* sequence block v2+ */
78 	MIPI_SEQ_TEAR_OFF,		/* sequence block v3+ */
79 	MIPI_SEQ_POWER_ON,		/* sequence block v3+ */
80 	MIPI_SEQ_POWER_OFF,		/* sequence block v3+ */
81 	MIPI_SEQ_MAX
82 };
83 
84 enum mipi_seq_element {
85 	MIPI_SEQ_ELEM_END = 0,
86 	MIPI_SEQ_ELEM_SEND_PKT,
87 	MIPI_SEQ_ELEM_DELAY,
88 	MIPI_SEQ_ELEM_GPIO,
89 	MIPI_SEQ_ELEM_I2C,		/* sequence block v2+ */
90 	MIPI_SEQ_ELEM_SPI,		/* sequence block v3+ */
91 	MIPI_SEQ_ELEM_PMIC,		/* sequence block v3+ */
92 	MIPI_SEQ_ELEM_MAX
93 };
94 
95 #define MIPI_DSI_UNDEFINED_PANEL_ID	0
96 #define MIPI_DSI_GENERIC_PANEL_ID	1
97 
98 struct mipi_config {
99 	u16 panel_id;
100 
101 	/* General Params */
102 	u32 enable_dithering:1;
103 	u32 rsvd1:1;
104 	u32 is_bridge:1;
105 
106 	u32 panel_arch_type:2;
107 	u32 is_cmd_mode:1;
108 
109 #define NON_BURST_SYNC_PULSE	0x1
110 #define NON_BURST_SYNC_EVENTS	0x2
111 #define BURST_MODE		0x3
112 	u32 video_transfer_mode:2;
113 
114 	u32 cabc_supported:1;
115 #define PPS_BLC_PMIC   0
116 #define PPS_BLC_SOC    1
117 	u32 pwm_blc:1;
118 
119 	/* Bit 13:10 */
120 #define PIXEL_FORMAT_RGB565			0x1
121 #define PIXEL_FORMAT_RGB666			0x2
122 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
123 #define PIXEL_FORMAT_RGB888			0x4
124 	u32 videomode_color_format:4;
125 
126 	/* Bit 15:14 */
127 #define ENABLE_ROTATION_0	0x0
128 #define ENABLE_ROTATION_90	0x1
129 #define ENABLE_ROTATION_180	0x2
130 #define ENABLE_ROTATION_270	0x3
131 	u32 rotation:2;
132 	u32 bta_enabled:1;
133 	u32 rsvd2:15;
134 
135 	/* 2 byte Port Description */
136 #define DUAL_LINK_NOT_SUPPORTED	0
137 #define DUAL_LINK_FRONT_BACK	1
138 #define DUAL_LINK_PIXEL_ALT	2
139 	u16 dual_link:2;
140 	u16 lane_cnt:2;
141 	u16 pixel_overlap:3;
142 	u16 rgb_flip:1;
143 #define DL_DCS_PORT_A			0x00
144 #define DL_DCS_PORT_C			0x01
145 #define DL_DCS_PORT_A_AND_C		0x02
146 	u16 dl_dcs_cabc_ports:2;
147 	u16 dl_dcs_backlight_ports:2;
148 	u16 rsvd3:4;
149 
150 	u16 rsvd4;
151 
152 	u8 rsvd5;
153 	u32 target_burst_mode_freq;
154 	u32 dsi_ddr_clk;
155 	u32 bridge_ref_clk;
156 
157 #define  BYTE_CLK_SEL_20MHZ		0
158 #define  BYTE_CLK_SEL_10MHZ		1
159 #define  BYTE_CLK_SEL_5MHZ		2
160 	u8 byte_clk_sel:2;
161 
162 	u8 rsvd6:6;
163 
164 	/* DPHY Flags */
165 	u16 dphy_param_valid:1;
166 	u16 eot_pkt_disabled:1;
167 	u16 enable_clk_stop:1;
168 	u16 rsvd7:13;
169 
170 	u32 hs_tx_timeout;
171 	u32 lp_rx_timeout;
172 	u32 turn_around_timeout;
173 	u32 device_reset_timer;
174 	u32 master_init_timer;
175 	u32 dbi_bw_timer;
176 	u32 lp_byte_clk_val;
177 
178 	/*  4 byte Dphy Params */
179 	u32 prepare_cnt:6;
180 	u32 rsvd8:2;
181 	u32 clk_zero_cnt:8;
182 	u32 trail_cnt:5;
183 	u32 rsvd9:3;
184 	u32 exit_zero_cnt:6;
185 	u32 rsvd10:2;
186 
187 	u32 clk_lane_switch_cnt;
188 	u32 hl_switch_cnt;
189 
190 	u32 rsvd11[6];
191 
192 	/* timings based on dphy spec */
193 	u8 tclk_miss;
194 	u8 tclk_post;
195 	u8 rsvd12;
196 	u8 tclk_pre;
197 	u8 tclk_prepare;
198 	u8 tclk_settle;
199 	u8 tclk_term_enable;
200 	u8 tclk_trail;
201 	u16 tclk_prepare_clkzero;
202 	u8 rsvd13;
203 	u8 td_term_enable;
204 	u8 teot;
205 	u8 ths_exit;
206 	u8 ths_prepare;
207 	u16 ths_prepare_hszero;
208 	u8 rsvd14;
209 	u8 ths_settle;
210 	u8 ths_skip;
211 	u8 ths_trail;
212 	u8 tinit;
213 	u8 tlpx;
214 	u8 rsvd15[3];
215 
216 	/* GPIOs */
217 	u8 panel_enable;
218 	u8 bl_enable;
219 	u8 pwm_enable;
220 	u8 reset_r_n;
221 	u8 pwr_down_r;
222 	u8 stdby_r_n;
223 
224 } __packed;
225 
226 /* all delays have a unit of 100us */
227 struct mipi_pps_data {
228 	u16 panel_on_delay;
229 	u16 bl_enable_delay;
230 	u16 bl_disable_delay;
231 	u16 panel_off_delay;
232 	u16 panel_power_cycle_delay;
233 } __packed;
234 
235 void intel_bios_init(struct drm_i915_private *dev_priv);
236 void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
237 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
238 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
239 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
240 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
241 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
242 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
243 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
244 bool intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
245 				     enum port port);
246 bool intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
247 				  enum port port);
248 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port);
249 bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
250 			       struct intel_crtc_state *crtc_state,
251 			       int dsc_max_bpc);
252 
253 #endif /* _INTEL_BIOS_H_ */
254